1 /* linux/arch/arm/mach-s3c2440/mach-rx3715.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.handhelds.org/projects/rx3715.html
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/timer.h>
19 #include <linux/init.h>
20 #include <linux/tty.h>
21 #include <linux/console.h>
22 #include <linux/sysdev.h>
23 #include <linux/platform_device.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial.h>
26 #include <linux/io.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/nand_ecc.h>
30 #include <linux/mtd/partitions.h>
31
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/irq.h>
35
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/mach-types.h>
39
40 #include <plat/regs-serial.h>
41 #include <mach/regs-gpio.h>
42 #include <mach/regs-lcd.h>
43
44 #include <mach/h1940.h>
45 #include <plat/nand.h>
46 #include <mach/fb.h>
47
48 #include <plat/clock.h>
49 #include <plat/devs.h>
50 #include <plat/cpu.h>
51 #include <plat/pm.h>
52
53 static struct map_desc rx3715_iodesc[] __initdata = {
54 /* dump ISA space somewhere unused */
55
56 {
57 .virtual = (u32)S3C24XX_VA_ISA_WORD,
58 .pfn = __phys_to_pfn(S3C2410_CS3),
59 .length = SZ_1M,
60 .type = MT_DEVICE,
61 }, {
62 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
63 .pfn = __phys_to_pfn(S3C2410_CS3),
64 .length = SZ_1M,
65 .type = MT_DEVICE,
66 },
67 };
68
69
70 static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
71 [0] = {
72 .name = "fclk",
73 .divisor = 0,
74 .min_baud = 0,
75 .max_baud = 0,
76 }
77 };
78
79 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
80 [0] = {
81 .hwport = 0,
82 .flags = 0,
83 .ucon = 0x3c5,
84 .ulcon = 0x03,
85 .ufcon = 0x51,
86 .clocks = rx3715_serial_clocks,
87 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
88 },
89 [1] = {
90 .hwport = 1,
91 .flags = 0,
92 .ucon = 0x3c5,
93 .ulcon = 0x03,
94 .ufcon = 0x00,
95 .clocks = rx3715_serial_clocks,
96 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
97 },
98 /* IR port */
99 [2] = {
100 .hwport = 2,
101 .uart_flags = UPF_CONS_FLOW,
102 .ucon = 0x3c5,
103 .ulcon = 0x43,
104 .ufcon = 0x51,
105 .clocks = rx3715_serial_clocks,
106 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
107 }
108 };
109
110 /* framebuffer lcd controller information */
111
112 static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
113 .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
114 S3C2410_LCDCON5_FRM565 |
115 S3C2410_LCDCON5_HWSWP,
116
117 .type = S3C2410_LCDCON1_TFT,
118 .width = 240,
119 .height = 320,
120
121 .pixclock = 260000,
122 .xres = 240,
123 .yres = 320,
124 .bpp = 16,
125 .left_margin = 36,
126 .right_margin = 36,
127 .hsync_len = 8,
128 .upper_margin = 6,
129 .lower_margin = 7,
130 .vsync_len = 3,
131 };
132
133 static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
134
135 .displays = &rx3715_lcdcfg,
136 .num_displays = 1,
137 .default_display = 0,
138
139 .lpcsel = 0xf82,
140
141 .gpccon = 0xaa955699,
142 .gpccon_mask = 0xffc003cc,
143 .gpcup = 0x0000ffff,
144 .gpcup_mask = 0xffffffff,
145
146 .gpdcon = 0xaa95aaa1,
147 .gpdcon_mask = 0xffc0fff0,
148 .gpdup = 0x0000faff,
149 .gpdup_mask = 0xffffffff,
150 };
151
152 static struct mtd_partition rx3715_nand_part[] = {
153 [0] = {
154 .name = "Whole Flash",
155 .offset = 0,
156 .size = MTDPART_SIZ_FULL,
157 .mask_flags = MTD_WRITEABLE,
158 }
159 };
160
161 static struct s3c2410_nand_set rx3715_nand_sets[] = {
162 [0] = {
163 .name = "Internal",
164 .nr_chips = 1,
165 .nr_partitions = ARRAY_SIZE(rx3715_nand_part),
166 .partitions = rx3715_nand_part,
167 },
168 };
169
170 static struct s3c2410_platform_nand rx3715_nand_info = {
171 .tacls = 25,
172 .twrph0 = 50,
173 .twrph1 = 15,
174 .nr_sets = ARRAY_SIZE(rx3715_nand_sets),
175 .sets = rx3715_nand_sets,
176 };
177
178 static struct platform_device *rx3715_devices[] __initdata = {
179 &s3c_device_usb,
180 &s3c_device_lcd,
181 &s3c_device_wdt,
182 &s3c_device_i2c0,
183 &s3c_device_iis,
184 &s3c_device_nand,
185 };
186
rx3715_map_io(void)187 static void __init rx3715_map_io(void)
188 {
189 s3c_device_nand.dev.platform_data = &rx3715_nand_info;
190
191 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
192 s3c24xx_init_clocks(16934000);
193 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
194 }
195
rx3715_init_irq(void)196 static void __init rx3715_init_irq(void)
197 {
198 s3c24xx_init_irq();
199 }
200
rx3715_init_machine(void)201 static void __init rx3715_init_machine(void)
202 {
203 #ifdef CONFIG_PM_H1940
204 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
205 #endif
206 s3c2410_pm_init();
207
208 s3c24xx_fb_set_platdata(&rx3715_fb_info);
209 platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
210 }
211
212 MACHINE_START(RX3715, "IPAQ-RX3715")
213 /* Maintainer: Ben Dooks <ben@fluff.org> */
214 .phys_io = S3C2410_PA_UART,
215 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
216 .boot_params = S3C2410_SDRAM_PA + 0x100,
217 .map_io = rx3715_map_io,
218 .init_irq = rx3715_init_irq,
219 .init_machine = rx3715_init_machine,
220 .timer = &s3c24xx_timer,
221 MACHINE_END
222