1 /* 2 * File: include/asm-blackfin/mach-bf518/defBF514.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: 8 * 9 * Rev: 10 * 11 * Modified: 12 * 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2, or (at your option) 18 * any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; see the file COPYING. 27 * If not, write to the Free Software Foundation, 28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 */ 30 31 #ifndef _DEF_BF514_H 32 #define _DEF_BF514_H 33 34 /* Include all Core registers and bit definitions */ 35 #include <asm/def_LPBlackfin.h> 36 37 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ 38 39 /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ 40 #include "defBF51x_base.h" 41 42 /* The following are the #defines needed by ADSP-BF514 that are not in the common header */ 43 44 /* SDH Registers */ 45 46 #define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ 47 #define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ 48 #define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ 49 #define SDH_COMMAND 0xFFC0390C /* SDH Command */ 50 #define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ 51 #define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ 52 #define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ 53 #define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ 54 #define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ 55 #define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ 56 #define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ 57 #define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ 58 #define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ 59 #define SDH_STATUS 0xFFC03934 /* SDH Status */ 60 #define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ 61 #define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ 62 #define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ 63 #define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ 64 #define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ 65 #define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ 66 #define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ 67 #define SDH_CFG 0xFFC039C8 /* SDH Configuration */ 68 #define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ 69 #define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ 70 #define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ 71 #define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ 72 #define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ 73 #define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ 74 #define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ 75 #define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ 76 #define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ 77 78 /* Removable Storage Interface Registers */ 79 80 #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ 81 #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ 82 #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ 83 #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ 84 #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ 85 #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ 86 #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ 87 #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ 88 #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ 89 #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ 90 #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ 91 #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ 92 #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ 93 #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ 94 #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ 95 #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ 96 #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ 97 #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ 98 #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ 99 #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ 100 #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ 101 #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ 102 #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ 103 #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ 104 #define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ 105 #define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ 106 #define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ 107 #define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ 108 #define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ 109 #define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ 110 #define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ 111 #define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ 112 113 #endif /* _DEF_BF514_H */ 114