1/* Boot entry point for MN10300 kernel 2 * 3 * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public Licence 8 * as published by the Free Software Foundation; either version 9 * 2 of the Licence, or (at your option) any later version. 10 */ 11 12#include <linux/threads.h> 13#include <linux/linkage.h> 14#include <linux/serial_reg.h> 15#include <asm/thread_info.h> 16#include <asm/page.h> 17#include <asm/pgtable.h> 18#include <asm/frame.inc> 19#include <asm/param.h> 20#include <asm/unit/serial.h> 21 22 .section .text.head,"ax" 23 24############################################################################### 25# 26# bootloader entry point 27# 28############################################################################### 29 .globl _start 30 .type _start,@function 31_start: 32 # save commandline pointer 33 mov d0,a3 34 35 # preload the PGD pointer register 36 mov swapper_pg_dir,d0 37 mov d0,(PTBR) 38 39 # turn on the TLBs 40 mov MMUCTR_IIV|MMUCTR_DIV,d0 41 mov d0,(MMUCTR) 42 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0 43 mov d0,(MMUCTR) 44 45 # turn on AM33v2 exception handling mode and set the trap table base 46 movhu (CPUP),d0 47 or CPUP_EXM_AM33V2,d0 48 movhu d0,(CPUP) 49 mov CONFIG_INTERRUPT_VECTOR_BASE,d0 50 mov d0,(TBR) 51 52 # invalidate and enable both of the caches 53 mov CHCTR,a0 54 clr d0 55 movhu d0,(a0) # turn off first 56 mov CHCTR_ICINV|CHCTR_DCINV,d0 57 movhu d0,(a0) 58 setlb 59 mov (a0),d0 60 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy 61 lne 62 63#ifndef CONFIG_MN10300_CACHE_DISABLED 64#ifdef CONFIG_MN10300_CACHE_WBACK 65#ifndef CONFIG_MN10300_CACHE_WBACK_NOWRALLOC 66 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 67#else 68 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0 69#endif /* CACHE_DISABLED */ 70#else 71 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 72#endif /* WBACK */ 73 movhu d0,(a0) # enable 74#endif /* NOWRALLOC */ 75 76 # turn on RTS on the debug serial port if applicable 77#ifdef CONFIG_MN10300_UNIT_ASB2305 78 bset UART_MCR_RTS,(ASB2305_DEBUG_MCR) 79#endif 80 81 # clear the BSS area 82 mov __bss_start,a0 83 mov __bss_stop,a1 84 clr d0 85bssclear: 86 cmp a1,a0 87 bge bssclear_end 88 mov d0,(a0) 89 inc4 a0 90 bra bssclear 91bssclear_end: 92 93 # retrieve the parameters (including command line) before we overwrite 94 # them 95 cmp 0xabadcafe,d1 96 bne __no_parameters 97 98__copy_parameters: 99 mov redboot_command_line,a0 100 mov a0,a1 101 add COMMAND_LINE_SIZE,a1 1021: 103 movbu (a3),d0 104 inc a3 105 movbu d0,(a0) 106 inc a0 107 cmp a1,a0 108 blt 1b 109 110 mov redboot_platform_name,a0 111 mov a0,a1 112 add COMMAND_LINE_SIZE,a1 113 mov d2,a3 1141: 115 movbu (a3),d0 116 inc a3 117 movbu d0,(a0) 118 inc a0 119 cmp a1,a0 120 blt 1b 121 122__no_parameters: 123 124 # set up the registers with recognisable rubbish in them 125 mov init_thread_union+THREAD_SIZE-12,sp 126 127 mov 0xea01eaea,d0 128 mov d0,(4,sp) # EPSW save area 129 mov 0xea02eaea,d0 130 mov d0,(8,sp) # PC save area 131 132 mov 0xeb0060ed,d0 133 mov d0,mdr 134 mov 0xeb0061ed,d0 135 mov d0,mdrq 136 mov 0xeb0062ed,d0 137 mov d0,mcrh 138 mov 0xeb0063ed,d0 139 mov d0,mcrl 140 mov 0xeb0064ed,d0 141 mov d0,mcvf 142 mov 0xed0065ed,a3 143 mov a3,usp 144 145 mov 0xed00e0ed,e0 146 mov 0xed00e1ed,e1 147 mov 0xed00e2ed,e2 148 mov 0xed00e3ed,e3 149 mov 0xed00e4ed,e4 150 mov 0xed00e5ed,e5 151 mov 0xed00e6ed,e6 152 mov 0xed00e7ed,e7 153 154 mov 0xed00d0ed,d0 155 mov 0xed00d1ed,d1 156 mov 0xed00d2ed,d2 157 mov 0xed00d3ed,d3 158 mov 0xed00a0ed,a0 159 mov 0xed00a1ed,a1 160 mov 0xed00a2ed,a2 161 mov 0,a3 162 163 # set up the initial kernel stack 164 SAVE_ALL 165 mov 0xffffffff,d0 166 mov d0,(REG_ORIG_D0,fp) 167 168 # put different recognisable rubbish in the regs 169 mov 0xfb0060ed,d0 170 mov d0,mdr 171 mov 0xfb0061ed,d0 172 mov d0,mdrq 173 mov 0xfb0062ed,d0 174 mov d0,mcrh 175 mov 0xfb0063ed,d0 176 mov d0,mcrl 177 mov 0xfb0064ed,d0 178 mov d0,mcvf 179 mov 0xfd0065ed,a0 180 mov a0,usp 181 182 mov 0xfd00e0ed,e0 183 mov 0xfd00e1ed,e1 184 mov 0xfd00e2ed,e2 185 mov 0xfd00e3ed,e3 186 mov 0xfd00e4ed,e4 187 mov 0xfd00e5ed,e5 188 mov 0xfd00e6ed,e6 189 mov 0xfd00e7ed,e7 190 191 mov 0xfd00d0ed,d0 192 mov 0xfd00d1ed,d1 193 mov 0xfd00d2ed,d2 194 mov 0xfd00d3ed,d3 195 mov 0xfd00a0ed,a0 196 mov 0xfd00a1ed,a1 197 mov 0xfd00a2ed,a2 198 199 # we may be holding current in E2 200#ifdef CONFIG_MN10300_CURRENT_IN_E2 201 mov init_task,e2 202#endif 203 204 # initialise the processor and the unit 205 call processor_init[],0 206 call unit_init[],0 207 208#ifdef CONFIG_GDBSTUB 209 call gdbstub_init[],0 210 211#ifdef CONFIG_GDBSTUB_IMMEDIATE 212 .globl __gdbstub_pause 213__gdbstub_pause: 214 bra __gdbstub_pause 215#endif 216#endif 217 218 jmp start_kernel 219 .size _start, _start-. 220ENTRY(__head_end) 221 222/* 223 * This is initialized to disallow all access to the low 2G region 224 * - the high 2G region is managed directly by the MMU 225 * - range 0x70000000-0x7C000000 are initialised for use by VMALLOC 226 */ 227 .section .bss 228 .balign PAGE_SIZE 229ENTRY(swapper_pg_dir) 230 .space PTRS_PER_PGD*4 231 232/* 233 * The page tables are initialized to only 8MB here - the final page 234 * tables are set up later depending on memory size. 235 */ 236 237 .balign PAGE_SIZE 238ENTRY(empty_zero_page) 239 .space PAGE_SIZE 240 241 .balign PAGE_SIZE 242ENTRY(empty_bad_page) 243 .space PAGE_SIZE 244 245 .balign PAGE_SIZE 246ENTRY(empty_bad_pte_table) 247 .space PAGE_SIZE 248 249 .balign PAGE_SIZE 250ENTRY(large_page_table) 251 .space PAGE_SIZE 252 253 .balign PAGE_SIZE 254ENTRY(kernel_vmalloc_ptes) 255 .space ((VMALLOC_END-VMALLOC_START)/PAGE_SIZE)*4 256