1 /*
2 * Copyright 2007 David Gibson, IBM Corporation.
3 *
4 * Based on earlier code:
5 * Matt Porter <mporter@kernel.crashing.org>
6 * Copyright 2002-2005 MontaVista Software Inc.
7 *
8 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
9 * Copyright (c) 2003, 2004 Zultys Technologies
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16 #include <stddef.h>
17 #include "types.h"
18 #include "string.h"
19 #include "stdio.h"
20 #include "ops.h"
21 #include "reg.h"
22 #include "dcr.h"
23
chip_11_errata(unsigned long memsize)24 static unsigned long chip_11_errata(unsigned long memsize)
25 {
26 unsigned long pvr;
27
28 pvr = mfpvr();
29
30 switch (pvr & 0xf0000ff0) {
31 case 0x40000850:
32 case 0x400008d0:
33 case 0x200008d0:
34 memsize -= 4096;
35 break;
36 default:
37 break;
38 }
39
40 return memsize;
41 }
42
43 /* Read the 4xx SDRAM controller to get size of system memory. */
ibm4xx_sdram_fixup_memsize(void)44 void ibm4xx_sdram_fixup_memsize(void)
45 {
46 int i;
47 unsigned long memsize, bank_config;
48
49 memsize = 0;
50 for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
51 bank_config = SDRAM0_READ(sdram_bxcr[i]);
52 if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
53 memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
54 }
55
56 memsize = chip_11_errata(memsize);
57 dt_fixup_memory(0, memsize);
58 }
59
60 /* Read the 440SPe MQ controller to get size of system memory. */
61 #define DCRN_MQ0_B0BAS 0x40
62 #define DCRN_MQ0_B1BAS 0x41
63 #define DCRN_MQ0_B2BAS 0x42
64 #define DCRN_MQ0_B3BAS 0x43
65
ibm440spe_decode_bas(u32 bas)66 static u64 ibm440spe_decode_bas(u32 bas)
67 {
68 u64 base = ((u64)(bas & 0xFFE00000u)) << 2;
69
70 /* open coded because I'm paranoid about invalid values */
71 switch ((bas >> 4) & 0xFFF) {
72 case 0:
73 return 0;
74 case 0xffc:
75 return base + 0x000800000ull;
76 case 0xff8:
77 return base + 0x001000000ull;
78 case 0xff0:
79 return base + 0x002000000ull;
80 case 0xfe0:
81 return base + 0x004000000ull;
82 case 0xfc0:
83 return base + 0x008000000ull;
84 case 0xf80:
85 return base + 0x010000000ull;
86 case 0xf00:
87 return base + 0x020000000ull;
88 case 0xe00:
89 return base + 0x040000000ull;
90 case 0xc00:
91 return base + 0x080000000ull;
92 case 0x800:
93 return base + 0x100000000ull;
94 }
95 printf("Memory BAS value 0x%08x unsupported !\n", bas);
96 return 0;
97 }
98
ibm440spe_fixup_memsize(void)99 void ibm440spe_fixup_memsize(void)
100 {
101 u64 banktop, memsize = 0;
102
103 /* Ultimately, we should directly construct the memory node
104 * so we are able to handle holes in the memory address space
105 */
106 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS));
107 if (banktop > memsize)
108 memsize = banktop;
109 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS));
110 if (banktop > memsize)
111 memsize = banktop;
112 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS));
113 if (banktop > memsize)
114 memsize = banktop;
115 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS));
116 if (banktop > memsize)
117 memsize = banktop;
118
119 dt_fixup_memory(0, memsize);
120 }
121
122
123 /* 4xx DDR1/2 Denali memory controller support */
124 /* DDR0 registers */
125 #define DDR0_02 2
126 #define DDR0_08 8
127 #define DDR0_10 10
128 #define DDR0_14 14
129 #define DDR0_42 42
130 #define DDR0_43 43
131
132 /* DDR0_02 */
133 #define DDR_START 0x1
134 #define DDR_START_SHIFT 0
135 #define DDR_MAX_CS_REG 0x3
136 #define DDR_MAX_CS_REG_SHIFT 24
137 #define DDR_MAX_COL_REG 0xf
138 #define DDR_MAX_COL_REG_SHIFT 16
139 #define DDR_MAX_ROW_REG 0xf
140 #define DDR_MAX_ROW_REG_SHIFT 8
141 /* DDR0_08 */
142 #define DDR_DDR2_MODE 0x1
143 #define DDR_DDR2_MODE_SHIFT 0
144 /* DDR0_10 */
145 #define DDR_CS_MAP 0x3
146 #define DDR_CS_MAP_SHIFT 8
147 /* DDR0_14 */
148 #define DDR_REDUC 0x1
149 #define DDR_REDUC_SHIFT 16
150 /* DDR0_42 */
151 #define DDR_APIN 0x7
152 #define DDR_APIN_SHIFT 24
153 /* DDR0_43 */
154 #define DDR_COL_SZ 0x7
155 #define DDR_COL_SZ_SHIFT 8
156 #define DDR_BANK8 0x1
157 #define DDR_BANK8_SHIFT 0
158
159 #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
160
ibm4xx_denali_fixup_memsize(void)161 void ibm4xx_denali_fixup_memsize(void)
162 {
163 u32 val, max_cs, max_col, max_row;
164 u32 cs, col, row, bank, dpath;
165 unsigned long memsize;
166
167 val = SDRAM0_READ(DDR0_02);
168 if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
169 fatal("DDR controller is not initialized\n");
170
171 /* get maximum cs col and row values */
172 max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
173 max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
174 max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
175
176 /* get CS value */
177 val = SDRAM0_READ(DDR0_10);
178
179 val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
180 cs = 0;
181 while (val) {
182 if (val & 0x1)
183 cs++;
184 val = val >> 1;
185 }
186
187 if (!cs)
188 fatal("No memory installed\n");
189 if (cs > max_cs)
190 fatal("DDR wrong CS configuration\n");
191
192 /* get data path bytes */
193 val = SDRAM0_READ(DDR0_14);
194
195 if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
196 dpath = 8; /* 64 bits */
197 else
198 dpath = 4; /* 32 bits */
199
200 /* get address pins (rows) */
201 val = SDRAM0_READ(DDR0_42);
202
203 row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
204 if (row > max_row)
205 fatal("DDR wrong APIN configuration\n");
206 row = max_row - row;
207
208 /* get collomn size and banks */
209 val = SDRAM0_READ(DDR0_43);
210
211 col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
212 if (col > max_col)
213 fatal("DDR wrong COL configuration\n");
214 col = max_col - col;
215
216 if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
217 bank = 8; /* 8 banks */
218 else
219 bank = 4; /* 4 banks */
220
221 memsize = cs * (1 << (col+row)) * bank * dpath;
222 memsize = chip_11_errata(memsize);
223 dt_fixup_memory(0, memsize);
224 }
225
226 #define SPRN_DBCR0_40X 0x3F2
227 #define SPRN_DBCR0_44X 0x134
228 #define DBCR0_RST_SYSTEM 0x30000000
229
ibm44x_dbcr_reset(void)230 void ibm44x_dbcr_reset(void)
231 {
232 unsigned long tmp;
233
234 asm volatile (
235 "mfspr %0,%1\n"
236 "oris %0,%0,%2@h\n"
237 "mtspr %1,%0"
238 : "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
239 );
240
241 }
242
ibm40x_dbcr_reset(void)243 void ibm40x_dbcr_reset(void)
244 {
245 unsigned long tmp;
246
247 asm volatile (
248 "mfspr %0,%1\n"
249 "oris %0,%0,%2@h\n"
250 "mtspr %1,%0"
251 : "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
252 );
253 }
254
255 #define EMAC_RESET 0x20000000
ibm4xx_quiesce_eth(u32 * emac0,u32 * emac1)256 void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
257 {
258 /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
259 * do this for us
260 */
261 if (emac0)
262 *emac0 = EMAC_RESET;
263 if (emac1)
264 *emac1 = EMAC_RESET;
265
266 mtdcr(DCRN_MAL0_CFG, MAL_RESET);
267 while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)
268 ; /* loop until reset takes effect */
269 }
270
271 /* Read 4xx EBC bus bridge registers to get mappings of the peripheral
272 * banks into the OPB address space */
ibm4xx_fixup_ebc_ranges(const char * ebc)273 void ibm4xx_fixup_ebc_ranges(const char *ebc)
274 {
275 void *devp;
276 u32 bxcr;
277 u32 ranges[EBC_NUM_BANKS*4];
278 u32 *p = ranges;
279 int i;
280
281 for (i = 0; i < EBC_NUM_BANKS; i++) {
282 mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
283 bxcr = mfdcr(DCRN_EBC0_CFGDATA);
284
285 if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
286 *p++ = i;
287 *p++ = 0;
288 *p++ = bxcr & EBC_BXCR_BAS;
289 *p++ = EBC_BXCR_BANK_SIZE(bxcr);
290 }
291 }
292
293 devp = finddevice(ebc);
294 if (! devp)
295 fatal("Couldn't locate EBC node %s\n\r", ebc);
296
297 setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
298 }
299
300 /* Calculate 440GP clocks */
ibm440gp_fixup_clocks(unsigned int sys_clk,unsigned int ser_clk)301 void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
302 {
303 u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
304 u32 cr0 = mfdcr(DCRN_CPC0_CR0);
305 u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
306 u32 opdv = CPC0_SYS0_OPDV(sys0);
307 u32 epdv = CPC0_SYS0_EPDV(sys0);
308
309 if (sys0 & CPC0_SYS0_BYPASS) {
310 /* Bypass system PLL */
311 cpu = plb = sys_clk;
312 } else {
313 if (sys0 & CPC0_SYS0_EXTSL)
314 /* PerClk */
315 m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
316 else
317 /* CPU clock */
318 m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
319 cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0);
320 plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0);
321 }
322
323 opb = plb / opdv;
324 ebc = opb / epdv;
325
326 /* FIXME: Check if this is for all 440GP, or just Ebony */
327 if ((mfpvr() & 0xf0000fff) == 0x40000440)
328 /* Rev. B 440GP, use external system clock */
329 tb = sys_clk;
330 else
331 /* Rev. C 440GP, errata force us to use internal clock */
332 tb = cpu;
333
334 if (cr0 & CPC0_CR0_U0EC)
335 /* External UART clock */
336 uart0 = ser_clk;
337 else
338 /* Internal UART clock */
339 uart0 = plb / CPC0_CR0_UDIV(cr0);
340
341 if (cr0 & CPC0_CR0_U1EC)
342 /* External UART clock */
343 uart1 = ser_clk;
344 else
345 /* Internal UART clock */
346 uart1 = plb / CPC0_CR0_UDIV(cr0);
347
348 printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
349 (sys_clk + 500000) / 1000000, sys_clk);
350
351 dt_fixup_cpu_clocks(cpu, tb, 0);
352
353 dt_fixup_clock("/plb", plb);
354 dt_fixup_clock("/plb/opb", opb);
355 dt_fixup_clock("/plb/opb/ebc", ebc);
356 dt_fixup_clock("/plb/opb/serial@40000200", uart0);
357 dt_fixup_clock("/plb/opb/serial@40000300", uart1);
358 }
359
360 #define SPRN_CCR1 0x378
361
__fix_zero(u32 v,u32 def)362 static inline u32 __fix_zero(u32 v, u32 def)
363 {
364 return v ? v : def;
365 }
366
__ibm440eplike_fixup_clocks(unsigned int sys_clk,unsigned int tmr_clk,int per_clk_from_opb)367 static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk,
368 unsigned int tmr_clk,
369 int per_clk_from_opb)
370 {
371 /* PLL config */
372 u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
373 u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
374
375 /* Dividers */
376 u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
377 u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16);
378 u32 fwdvb = __fix_zero((plld >> 8) & 7, 8);
379 u32 lfbdv = __fix_zero(plld & 0x3f, 64);
380 u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8);
381 u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8);
382 u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4);
383 u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4);
384
385 /* Input clocks for primary dividers */
386 u32 clk_a, clk_b;
387
388 /* Resulting clocks */
389 u32 cpu, plb, opb, ebc, vco;
390
391 /* Timebase */
392 u32 ccr1, tb = tmr_clk;
393
394 if (pllc & 0x40000000) {
395 u32 m;
396
397 /* Feedback path */
398 switch ((pllc >> 24) & 7) {
399 case 0:
400 /* PLLOUTx */
401 m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
402 break;
403 case 1:
404 /* CPU */
405 m = fwdva * pradv0;
406 break;
407 case 5:
408 /* PERClk */
409 m = fwdvb * prbdv0 * opbdv0 * perdv0;
410 break;
411 default:
412 printf("WARNING ! Invalid PLL feedback source !\n");
413 goto bypass;
414 }
415 m *= fbdv;
416 vco = sys_clk * m;
417 clk_a = vco / fwdva;
418 clk_b = vco / fwdvb;
419 } else {
420 bypass:
421 /* Bypass system PLL */
422 vco = 0;
423 clk_a = clk_b = sys_clk;
424 }
425
426 cpu = clk_a / pradv0;
427 plb = clk_b / prbdv0;
428 opb = plb / opbdv0;
429 ebc = (per_clk_from_opb ? opb : plb) / perdv0;
430
431 /* Figure out timebase. Either CPU or default TmrClk */
432 ccr1 = mfspr(SPRN_CCR1);
433
434 /* If passed a 0 tmr_clk, force CPU clock */
435 if (tb == 0) {
436 ccr1 &= ~0x80u;
437 mtspr(SPRN_CCR1, ccr1);
438 }
439 if ((ccr1 & 0x0080) == 0)
440 tb = cpu;
441
442 dt_fixup_cpu_clocks(cpu, tb, 0);
443 dt_fixup_clock("/plb", plb);
444 dt_fixup_clock("/plb/opb", opb);
445 dt_fixup_clock("/plb/opb/ebc", ebc);
446
447 return plb;
448 }
449
eplike_fixup_uart_clk(int index,const char * path,unsigned int ser_clk,unsigned int plb_clk)450 static void eplike_fixup_uart_clk(int index, const char *path,
451 unsigned int ser_clk,
452 unsigned int plb_clk)
453 {
454 unsigned int sdr;
455 unsigned int clock;
456
457 switch (index) {
458 case 0:
459 sdr = SDR0_READ(DCRN_SDR0_UART0);
460 break;
461 case 1:
462 sdr = SDR0_READ(DCRN_SDR0_UART1);
463 break;
464 case 2:
465 sdr = SDR0_READ(DCRN_SDR0_UART2);
466 break;
467 case 3:
468 sdr = SDR0_READ(DCRN_SDR0_UART3);
469 break;
470 default:
471 return;
472 }
473
474 if (sdr & 0x00800000u)
475 clock = ser_clk;
476 else
477 clock = plb_clk / __fix_zero(sdr & 0xff, 256);
478
479 dt_fixup_clock(path, clock);
480 }
481
ibm440ep_fixup_clocks(unsigned int sys_clk,unsigned int ser_clk,unsigned int tmr_clk)482 void ibm440ep_fixup_clocks(unsigned int sys_clk,
483 unsigned int ser_clk,
484 unsigned int tmr_clk)
485 {
486 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
487
488 /* serial clocks beed fixup based on int/ext */
489 eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
490 eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
491 eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
492 eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk);
493 }
494
ibm440gx_fixup_clocks(unsigned int sys_clk,unsigned int ser_clk,unsigned int tmr_clk)495 void ibm440gx_fixup_clocks(unsigned int sys_clk,
496 unsigned int ser_clk,
497 unsigned int tmr_clk)
498 {
499 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
500
501 /* serial clocks beed fixup based on int/ext */
502 eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
503 eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
504 }
505
ibm440spe_fixup_clocks(unsigned int sys_clk,unsigned int ser_clk,unsigned int tmr_clk)506 void ibm440spe_fixup_clocks(unsigned int sys_clk,
507 unsigned int ser_clk,
508 unsigned int tmr_clk)
509 {
510 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
511
512 /* serial clocks beed fixup based on int/ext */
513 eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk);
514 eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk);
515 eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk);
516 }
517
ibm405gp_fixup_clocks(unsigned int sys_clk,unsigned int ser_clk)518 void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
519 {
520 u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
521 u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
522 u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
523 u32 psr = mfdcr(DCRN_405_CPC0_PSR);
524 u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
525 u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
526
527 fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
528 fbdv = (pllmr & 0x1e000000) >> 25;
529 if (fbdv == 0)
530 fbdv = 16;
531 cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
532 opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
533 ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
534 epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
535 udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
536
537 /* check for 405GPr */
538 if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
539 fwdvb = 8 - (pllmr & 0x00000007);
540 if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
541 if (psr & 0x00000020) /* New mode enable */
542 m = fwdvb * 2 * ppdv;
543 else
544 m = fwdvb * cbdv * ppdv;
545 else if (psr & 0x00000020) /* New mode enable */
546 if (psr & 0x00000800) /* PerClk synch mode */
547 m = fwdvb * 2 * epdv;
548 else
549 m = fbdv * fwdv;
550 else if (epdv == fbdv)
551 m = fbdv * cbdv * epdv;
552 else
553 m = fbdv * fwdvb * cbdv;
554
555 cpu = sys_clk * m / fwdv;
556 plb = sys_clk * m / (fwdvb * cbdv);
557 } else {
558 m = fwdv * fbdv * cbdv;
559 cpu = sys_clk * m / fwdv;
560 plb = cpu / cbdv;
561 }
562 opb = plb / opdv;
563 ebc = plb / epdv;
564
565 if (cpc0_cr0 & 0x80)
566 /* uart0 uses the external clock */
567 uart0 = ser_clk;
568 else
569 uart0 = cpu / udiv;
570
571 if (cpc0_cr0 & 0x40)
572 /* uart1 uses the external clock */
573 uart1 = ser_clk;
574 else
575 uart1 = cpu / udiv;
576
577 /* setup the timebase clock to tick at the cpu frequency */
578 cpc0_cr1 = cpc0_cr1 & ~0x00800000;
579 mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
580 tb = cpu;
581
582 dt_fixup_cpu_clocks(cpu, tb, 0);
583 dt_fixup_clock("/plb", plb);
584 dt_fixup_clock("/plb/opb", opb);
585 dt_fixup_clock("/plb/ebc", ebc);
586 dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
587 dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
588 }
589
590
ibm405ep_fixup_clocks(unsigned int sys_clk)591 void ibm405ep_fixup_clocks(unsigned int sys_clk)
592 {
593 u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
594 u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
595 u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
596 u32 cpu, plb, opb, ebc, uart0, uart1;
597 u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
598 u32 pllmr0_ccdv, tb, m;
599
600 fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
601 fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
602 fbdv = (pllmr1 & 0x00f00000) >> 20;
603 if (fbdv == 0)
604 fbdv = 16;
605
606 cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
607 epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */
608 opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
609
610 m = fbdv * fwdvb;
611
612 pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
613 if (pllmr1 & 0x80000000)
614 cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
615 else
616 cpu = sys_clk / pllmr0_ccdv;
617
618 plb = cpu / cbdv;
619 opb = plb / opdv;
620 ebc = plb / epdv;
621 tb = cpu;
622 uart0 = cpu / (cpc0_ucr & 0x0000007f);
623 uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
624
625 dt_fixup_cpu_clocks(cpu, tb, 0);
626 dt_fixup_clock("/plb", plb);
627 dt_fixup_clock("/plb/opb", opb);
628 dt_fixup_clock("/plb/ebc", ebc);
629 dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
630 dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
631 }
632