1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 12 * 13 * This file contains the low-level support and setup for the 14 * PowerPC platform, including trap and interrupt dispatch. 15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.) 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License 19 * as published by the Free Software Foundation; either version 20 * 2 of the License, or (at your option) any later version. 21 * 22 */ 23 24#include <asm/reg.h> 25#include <asm/page.h> 26#include <asm/mmu.h> 27#include <asm/pgtable.h> 28#include <asm/cputable.h> 29#include <asm/cache.h> 30#include <asm/thread_info.h> 31#include <asm/ppc_asm.h> 32#include <asm/asm-offsets.h> 33#include <asm/ptrace.h> 34#include <asm/bug.h> 35 36/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ 37#define LOAD_BAT(n, reg, RA, RB) \ 38 /* see the comment for clear_bats() -- Cort */ \ 39 li RA,0; \ 40 mtspr SPRN_IBAT##n##U,RA; \ 41 mtspr SPRN_DBAT##n##U,RA; \ 42 lwz RA,(n*16)+0(reg); \ 43 lwz RB,(n*16)+4(reg); \ 44 mtspr SPRN_IBAT##n##U,RA; \ 45 mtspr SPRN_IBAT##n##L,RB; \ 46 beq 1f; \ 47 lwz RA,(n*16)+8(reg); \ 48 lwz RB,(n*16)+12(reg); \ 49 mtspr SPRN_DBAT##n##U,RA; \ 50 mtspr SPRN_DBAT##n##L,RB; \ 511: 52 53 .section .text.head, "ax" 54 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f 55 .stabs "head_32.S",N_SO,0,0,0f 560: 57_ENTRY(_stext); 58 59/* 60 * _start is defined this way because the XCOFF loader in the OpenFirmware 61 * on the powermac expects the entry point to be a procedure descriptor. 62 */ 63_ENTRY(_start); 64 /* 65 * These are here for legacy reasons, the kernel used to 66 * need to look like a coff function entry for the pmac 67 * but we're always started by some kind of bootloader now. 68 * -- Cort 69 */ 70 nop /* used by __secondary_hold on prep (mtx) and chrp smp */ 71 nop /* used by __secondary_hold on prep (mtx) and chrp smp */ 72 nop 73 74/* PMAC 75 * Enter here with the kernel text, data and bss loaded starting at 76 * 0, running with virtual == physical mapping. 77 * r5 points to the prom entry point (the client interface handler 78 * address). Address translation is turned on, with the prom 79 * managing the hash table. Interrupts are disabled. The stack 80 * pointer (r1) points to just below the end of the half-meg region 81 * from 0x380000 - 0x400000, which is mapped in already. 82 * 83 * If we are booted from MacOS via BootX, we enter with the kernel 84 * image loaded somewhere, and the following values in registers: 85 * r3: 'BooX' (0x426f6f58) 86 * r4: virtual address of boot_infos_t 87 * r5: 0 88 * 89 * PREP 90 * This is jumped to on prep systems right after the kernel is relocated 91 * to its proper place in memory by the boot loader. The expected layout 92 * of the regs is: 93 * r3: ptr to residual data 94 * r4: initrd_start or if no initrd then 0 95 * r5: initrd_end - unused if r4 is 0 96 * r6: Start of command line string 97 * r7: End of command line string 98 * 99 * This just gets a minimal mmu environment setup so we can call 100 * start_here() to do the real work. 101 * -- Cort 102 */ 103 104 .globl __start 105__start: 106/* 107 * We have to do any OF calls before we map ourselves to KERNELBASE, 108 * because OF may have I/O devices mapped into that area 109 * (particularly on CHRP). 110 */ 111#ifdef CONFIG_PPC_MULTIPLATFORM 112 cmpwi 0,r5,0 113 beq 1f 114 115 /* find out where we are now */ 116 bcl 20,31,$+4 1170: mflr r8 /* r8 = runtime addr here */ 118 addis r8,r8,(_stext - 0b)@ha 119 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */ 120 bl prom_init 121 trap 122#endif 123 124/* 125 * Check for BootX signature when supporting PowerMac and branch to 126 * appropriate trampoline if it's present 127 */ 128#ifdef CONFIG_PPC_PMAC 1291: lis r31,0x426f 130 ori r31,r31,0x6f58 131 cmpw 0,r3,r31 132 bne 1f 133 bl bootx_init 134 trap 135#endif /* CONFIG_PPC_PMAC */ 136 1371: mr r31,r3 /* save parameters */ 138 mr r30,r4 139 li r24,0 /* cpu # */ 140 141/* 142 * early_init() does the early machine identification and does 143 * the necessary low-level setup and clears the BSS 144 * -- Cort <cort@fsmlabs.com> 145 */ 146 bl early_init 147 148/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains 149 * the physical address we are running at, returned by early_init() 150 */ 151 bl mmu_off 152__after_mmu_off: 153 bl clear_bats 154 bl flush_tlbs 155 156 bl initial_bats 157#if defined(CONFIG_BOOTX_TEXT) 158 bl setup_disp_bat 159#endif 160#ifdef CONFIG_PPC_EARLY_DEBUG_CPM 161 bl setup_cpm_bat 162#endif 163 164/* 165 * Call setup_cpu for CPU 0 and initialize 6xx Idle 166 */ 167 bl reloc_offset 168 li r24,0 /* cpu# */ 169 bl call_setup_cpu /* Call setup_cpu for this CPU */ 170#ifdef CONFIG_6xx 171 bl reloc_offset 172 bl init_idle_6xx 173#endif /* CONFIG_6xx */ 174 175 176/* 177 * We need to run with _start at physical address 0. 178 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses 179 * the exception vectors at 0 (and therefore this copy 180 * overwrites OF's exception vectors with our own). 181 * The MMU is off at this point. 182 */ 183 bl reloc_offset 184 mr r26,r3 185 addis r4,r3,KERNELBASE@h /* current address of _start */ 186 lis r5,PHYSICAL_START@h 187 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */ 188 bne relocate_kernel 189/* 190 * we now have the 1st 16M of ram mapped with the bats. 191 * prep needs the mmu to be turned on here, but pmac already has it on. 192 * this shouldn't bother the pmac since it just gets turned on again 193 * as we jump to our code at KERNELBASE. -- Cort 194 * Actually no, pmac doesn't have it on any more. BootX enters with MMU 195 * off, and in other cases, we now turn it off before changing BATs above. 196 */ 197turn_on_mmu: 198 mfmsr r0 199 ori r0,r0,MSR_DR|MSR_IR 200 mtspr SPRN_SRR1,r0 201 lis r0,start_here@h 202 ori r0,r0,start_here@l 203 mtspr SPRN_SRR0,r0 204 SYNC 205 RFI /* enables MMU */ 206 207/* 208 * We need __secondary_hold as a place to hold the other cpus on 209 * an SMP machine, even when we are running a UP kernel. 210 */ 211 . = 0xc0 /* for prep bootloader */ 212 li r3,1 /* MTX only has 1 cpu */ 213 .globl __secondary_hold 214__secondary_hold: 215 /* tell the master we're here */ 216 stw r3,__secondary_hold_acknowledge@l(0) 217#ifdef CONFIG_SMP 218100: lwz r4,0(0) 219 /* wait until we're told to start */ 220 cmpw 0,r4,r3 221 bne 100b 222 /* our cpu # was at addr 0 - go */ 223 mr r24,r3 /* cpu # */ 224 b __secondary_start 225#else 226 b . 227#endif /* CONFIG_SMP */ 228 229 .globl __secondary_hold_spinloop 230__secondary_hold_spinloop: 231 .long 0 232 .globl __secondary_hold_acknowledge 233__secondary_hold_acknowledge: 234 .long -1 235 236/* 237 * Exception entry code. This code runs with address translation 238 * turned off, i.e. using physical addresses. 239 * We assume sprg3 has the physical address of the current 240 * task's thread_struct. 241 */ 242#define EXCEPTION_PROLOG \ 243 mtspr SPRN_SPRG0,r10; \ 244 mtspr SPRN_SPRG1,r11; \ 245 mfcr r10; \ 246 EXCEPTION_PROLOG_1; \ 247 EXCEPTION_PROLOG_2 248 249#define EXCEPTION_PROLOG_1 \ 250 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 251 andi. r11,r11,MSR_PR; \ 252 tophys(r11,r1); /* use tophys(r1) if kernel */ \ 253 beq 1f; \ 254 mfspr r11,SPRN_SPRG3; \ 255 lwz r11,THREAD_INFO-THREAD(r11); \ 256 addi r11,r11,THREAD_SIZE; \ 257 tophys(r11,r11); \ 2581: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ 259 260 261#define EXCEPTION_PROLOG_2 \ 262 CLR_TOP32(r11); \ 263 stw r10,_CCR(r11); /* save registers */ \ 264 stw r12,GPR12(r11); \ 265 stw r9,GPR9(r11); \ 266 mfspr r10,SPRN_SPRG0; \ 267 stw r10,GPR10(r11); \ 268 mfspr r12,SPRN_SPRG1; \ 269 stw r12,GPR11(r11); \ 270 mflr r10; \ 271 stw r10,_LINK(r11); \ 272 mfspr r12,SPRN_SRR0; \ 273 mfspr r9,SPRN_SRR1; \ 274 stw r1,GPR1(r11); \ 275 stw r1,0(r11); \ 276 tovirt(r1,r11); /* set new kernel sp */ \ 277 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ 278 MTMSRD(r10); /* (except for mach check in rtas) */ \ 279 stw r0,GPR0(r11); \ 280 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \ 281 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \ 282 stw r10,8(r11); \ 283 SAVE_4GPRS(3, r11); \ 284 SAVE_2GPRS(7, r11) 285 286/* 287 * Note: code which follows this uses cr0.eq (set if from kernel), 288 * r11, r12 (SRR0), and r9 (SRR1). 289 * 290 * Note2: once we have set r1 we are in a position to take exceptions 291 * again, and we could thus set MSR:RI at that point. 292 */ 293 294/* 295 * Exception vectors. 296 */ 297#define EXCEPTION(n, label, hdlr, xfer) \ 298 . = n; \ 299label: \ 300 EXCEPTION_PROLOG; \ 301 addi r3,r1,STACK_FRAME_OVERHEAD; \ 302 xfer(n, hdlr) 303 304#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ 305 li r10,trap; \ 306 stw r10,_TRAP(r11); \ 307 li r10,MSR_KERNEL; \ 308 copyee(r10, r9); \ 309 bl tfer; \ 310i##n: \ 311 .long hdlr; \ 312 .long ret 313 314#define COPY_EE(d, s) rlwimi d,s,0,16,16 315#define NOCOPY(d, s) 316 317#define EXC_XFER_STD(n, hdlr) \ 318 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ 319 ret_from_except_full) 320 321#define EXC_XFER_LITE(n, hdlr) \ 322 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ 323 ret_from_except) 324 325#define EXC_XFER_EE(n, hdlr) \ 326 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ 327 ret_from_except_full) 328 329#define EXC_XFER_EE_LITE(n, hdlr) \ 330 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ 331 ret_from_except) 332 333/* System reset */ 334/* core99 pmac starts the seconary here by changing the vector, and 335 putting it back to what it was (unknown_exception) when done. */ 336 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) 337 338/* Machine check */ 339/* 340 * On CHRP, this is complicated by the fact that we could get a 341 * machine check inside RTAS, and we have no guarantee that certain 342 * critical registers will have the values we expect. The set of 343 * registers that might have bad values includes all the GPRs 344 * and all the BATs. We indicate that we are in RTAS by putting 345 * a non-zero value, the address of the exception frame to use, 346 * in SPRG2. The machine check handler checks SPRG2 and uses its 347 * value if it is non-zero. If we ever needed to free up SPRG2, 348 * we could use a field in the thread_info or thread_struct instead. 349 * (Other exception handlers assume that r1 is a valid kernel stack 350 * pointer when we take an exception from supervisor mode.) 351 * -- paulus. 352 */ 353 . = 0x200 354 mtspr SPRN_SPRG0,r10 355 mtspr SPRN_SPRG1,r11 356 mfcr r10 357#ifdef CONFIG_PPC_CHRP 358 mfspr r11,SPRN_SPRG2 359 cmpwi 0,r11,0 360 bne 7f 361#endif /* CONFIG_PPC_CHRP */ 362 EXCEPTION_PROLOG_1 3637: EXCEPTION_PROLOG_2 364 addi r3,r1,STACK_FRAME_OVERHEAD 365#ifdef CONFIG_PPC_CHRP 366 mfspr r4,SPRN_SPRG2 367 cmpwi cr1,r4,0 368 bne cr1,1f 369#endif 370 EXC_XFER_STD(0x200, machine_check_exception) 371#ifdef CONFIG_PPC_CHRP 3721: b machine_check_in_rtas 373#endif 374 375/* Data access exception. */ 376 . = 0x300 377DataAccess: 378 EXCEPTION_PROLOG 379 mfspr r10,SPRN_DSISR 380 stw r10,_DSISR(r11) 381 andis. r0,r10,0xa470 /* weird error? */ 382 bne 1f /* if not, try to put a PTE */ 383 mfspr r4,SPRN_DAR /* into the hash table */ 384 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */ 385 bl hash_page 3861: lwz r5,_DSISR(r11) /* get DSISR value */ 387 mfspr r4,SPRN_DAR 388 EXC_XFER_EE_LITE(0x300, handle_page_fault) 389 390 391/* Instruction access exception. */ 392 . = 0x400 393InstructionAccess: 394 EXCEPTION_PROLOG 395 andis. r0,r9,0x4000 /* no pte found? */ 396 beq 1f /* if so, try to put a PTE */ 397 li r3,0 /* into the hash table */ 398 mr r4,r12 /* SRR0 is fault address */ 399 bl hash_page 4001: mr r4,r12 401 mr r5,r9 402 EXC_XFER_EE_LITE(0x400, handle_page_fault) 403 404/* External interrupt */ 405 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) 406 407/* Alignment exception */ 408 . = 0x600 409Alignment: 410 EXCEPTION_PROLOG 411 mfspr r4,SPRN_DAR 412 stw r4,_DAR(r11) 413 mfspr r5,SPRN_DSISR 414 stw r5,_DSISR(r11) 415 addi r3,r1,STACK_FRAME_OVERHEAD 416 EXC_XFER_EE(0x600, alignment_exception) 417 418/* Program check exception */ 419 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) 420 421/* Floating-point unavailable */ 422 . = 0x800 423FPUnavailable: 424BEGIN_FTR_SECTION 425/* 426 * Certain Freescale cores don't have a FPU and treat fp instructions 427 * as a FP Unavailable exception. Redirect to illegal/emulation handling. 428 */ 429 b ProgramCheck 430END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE) 431 EXCEPTION_PROLOG 432 beq 1f 433 bl load_up_fpu /* if from user, just load it up */ 434 b fast_exception_return 4351: addi r3,r1,STACK_FRAME_OVERHEAD 436 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) 437 438/* Decrementer */ 439 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) 440 441 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) 442 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) 443 444/* System call */ 445 . = 0xc00 446SystemCall: 447 EXCEPTION_PROLOG 448 EXC_XFER_EE_LITE(0xc00, DoSyscall) 449 450/* Single step - not used on 601 */ 451 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) 452 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) 453 454/* 455 * The Altivec unavailable trap is at 0x0f20. Foo. 456 * We effectively remap it to 0x3000. 457 * We include an altivec unavailable exception vector even if 458 * not configured for Altivec, so that you can't panic a 459 * non-altivec kernel running on a machine with altivec just 460 * by executing an altivec instruction. 461 */ 462 . = 0xf00 463 b PerformanceMonitor 464 465 . = 0xf20 466 b AltiVecUnavailable 467 468/* 469 * Handle TLB miss for instruction on 603/603e. 470 * Note: we get an alternate set of r0 - r3 to use automatically. 471 */ 472 . = 0x1000 473InstructionTLBMiss: 474/* 475 * r0: stored ctr 476 * r1: linux style pte ( later becomes ppc hardware pte ) 477 * r2: ptr to linux-style pte 478 * r3: scratch 479 */ 480 mfctr r0 481 /* Get PTE (linux-style) and check access */ 482 mfspr r3,SPRN_IMISS 483 lis r1,PAGE_OFFSET@h /* check if kernel address */ 484 cmplw 0,r1,r3 485 mfspr r2,SPRN_SPRG3 486 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ 487 lwz r2,PGDIR(r2) 488 bge- 112f 489 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ 490 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ 491 lis r2,swapper_pg_dir@ha /* if kernel address, use */ 492 addi r2,r2,swapper_pg_dir@l /* kernel page table */ 493112: tophys(r2,r2) 494 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ 495 lwz r2,0(r2) /* get pmd entry */ 496 rlwinm. r2,r2,0,0,19 /* extract address of pte page */ 497 beq- InstructionAddressInvalid /* return if no mapping */ 498 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ 499 lwz r3,0(r2) /* get linux-style pte */ 500 andc. r1,r1,r3 /* check access & ~permission */ 501 bne- InstructionAddressInvalid /* return if access not permitted */ 502 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ 503 /* 504 * NOTE! We are assuming this is not an SMP system, otherwise 505 * we would need to update the pte atomically with lwarx/stwcx. 506 */ 507 stw r3,0(r2) /* update PTE (accessed bit) */ 508 /* Convert linux-style PTE to low word of PPC-style PTE */ 509 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ 510 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ 511 and r1,r1,r2 /* writable if _RW and _DIRTY */ 512 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ 513 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ 514 ori r1,r1,0xe04 /* clear out reserved bits */ 515 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ 516BEGIN_FTR_SECTION 517 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ 518END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) 519 mtspr SPRN_RPA,r1 520 mfspr r3,SPRN_IMISS 521 tlbli r3 522 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ 523 mtcrf 0x80,r3 524 rfi 525InstructionAddressInvalid: 526 mfspr r3,SPRN_SRR1 527 rlwinm r1,r3,9,6,6 /* Get load/store bit */ 528 529 addis r1,r1,0x2000 530 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */ 531 mtctr r0 /* Restore CTR */ 532 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ 533 or r2,r2,r1 534 mtspr SPRN_SRR1,r2 535 mfspr r1,SPRN_IMISS /* Get failing address */ 536 rlwinm. r2,r2,0,31,31 /* Check for little endian access */ 537 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */ 538 xor r1,r1,r2 539 mtspr SPRN_DAR,r1 /* Set fault address */ 540 mfmsr r0 /* Restore "normal" registers */ 541 xoris r0,r0,MSR_TGPR>>16 542 mtcrf 0x80,r3 /* Restore CR0 */ 543 mtmsr r0 544 b InstructionAccess 545 546/* 547 * Handle TLB miss for DATA Load operation on 603/603e 548 */ 549 . = 0x1100 550DataLoadTLBMiss: 551/* 552 * r0: stored ctr 553 * r1: linux style pte ( later becomes ppc hardware pte ) 554 * r2: ptr to linux-style pte 555 * r3: scratch 556 */ 557 mfctr r0 558 /* Get PTE (linux-style) and check access */ 559 mfspr r3,SPRN_DMISS 560 lis r1,PAGE_OFFSET@h /* check if kernel address */ 561 cmplw 0,r1,r3 562 mfspr r2,SPRN_SPRG3 563 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ 564 lwz r2,PGDIR(r2) 565 bge- 112f 566 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ 567 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ 568 lis r2,swapper_pg_dir@ha /* if kernel address, use */ 569 addi r2,r2,swapper_pg_dir@l /* kernel page table */ 570112: tophys(r2,r2) 571 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ 572 lwz r2,0(r2) /* get pmd entry */ 573 rlwinm. r2,r2,0,0,19 /* extract address of pte page */ 574 beq- DataAddressInvalid /* return if no mapping */ 575 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ 576 lwz r3,0(r2) /* get linux-style pte */ 577 andc. r1,r1,r3 /* check access & ~permission */ 578 bne- DataAddressInvalid /* return if access not permitted */ 579 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ 580 /* 581 * NOTE! We are assuming this is not an SMP system, otherwise 582 * we would need to update the pte atomically with lwarx/stwcx. 583 */ 584 stw r3,0(r2) /* update PTE (accessed bit) */ 585 /* Convert linux-style PTE to low word of PPC-style PTE */ 586 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ 587 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ 588 and r1,r1,r2 /* writable if _RW and _DIRTY */ 589 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ 590 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ 591 ori r1,r1,0xe04 /* clear out reserved bits */ 592 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ 593BEGIN_FTR_SECTION 594 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ 595END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) 596 mtspr SPRN_RPA,r1 597 mfspr r3,SPRN_DMISS 598 tlbld r3 599 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ 600 mtcrf 0x80,r3 601 rfi 602DataAddressInvalid: 603 mfspr r3,SPRN_SRR1 604 rlwinm r1,r3,9,6,6 /* Get load/store bit */ 605 addis r1,r1,0x2000 606 mtspr SPRN_DSISR,r1 607 mtctr r0 /* Restore CTR */ 608 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ 609 mtspr SPRN_SRR1,r2 610 mfspr r1,SPRN_DMISS /* Get failing address */ 611 rlwinm. r2,r2,0,31,31 /* Check for little endian access */ 612 beq 20f /* Jump if big endian */ 613 xori r1,r1,3 61420: mtspr SPRN_DAR,r1 /* Set fault address */ 615 mfmsr r0 /* Restore "normal" registers */ 616 xoris r0,r0,MSR_TGPR>>16 617 mtcrf 0x80,r3 /* Restore CR0 */ 618 mtmsr r0 619 b DataAccess 620 621/* 622 * Handle TLB miss for DATA Store on 603/603e 623 */ 624 . = 0x1200 625DataStoreTLBMiss: 626/* 627 * r0: stored ctr 628 * r1: linux style pte ( later becomes ppc hardware pte ) 629 * r2: ptr to linux-style pte 630 * r3: scratch 631 */ 632 mfctr r0 633 /* Get PTE (linux-style) and check access */ 634 mfspr r3,SPRN_DMISS 635 lis r1,PAGE_OFFSET@h /* check if kernel address */ 636 cmplw 0,r1,r3 637 mfspr r2,SPRN_SPRG3 638 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */ 639 lwz r2,PGDIR(r2) 640 bge- 112f 641 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ 642 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ 643 lis r2,swapper_pg_dir@ha /* if kernel address, use */ 644 addi r2,r2,swapper_pg_dir@l /* kernel page table */ 645112: tophys(r2,r2) 646 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ 647 lwz r2,0(r2) /* get pmd entry */ 648 rlwinm. r2,r2,0,0,19 /* extract address of pte page */ 649 beq- DataAddressInvalid /* return if no mapping */ 650 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ 651 lwz r3,0(r2) /* get linux-style pte */ 652 andc. r1,r1,r3 /* check access & ~permission */ 653 bne- DataAddressInvalid /* return if access not permitted */ 654 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY 655 /* 656 * NOTE! We are assuming this is not an SMP system, otherwise 657 * we would need to update the pte atomically with lwarx/stwcx. 658 */ 659 stw r3,0(r2) /* update PTE (accessed/dirty bits) */ 660 /* Convert linux-style PTE to low word of PPC-style PTE */ 661 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ 662 li r1,0xe05 /* clear out reserved bits & PP lsb */ 663 andc r1,r3,r1 /* PP = user? 2: 0 */ 664BEGIN_FTR_SECTION 665 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ 666END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) 667 mtspr SPRN_RPA,r1 668 mfspr r3,SPRN_DMISS 669 tlbld r3 670 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ 671 mtcrf 0x80,r3 672 rfi 673 674#ifndef CONFIG_ALTIVEC 675#define altivec_assist_exception unknown_exception 676#endif 677 678 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE) 679 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE) 680 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 681 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE) 682 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD) 683 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) 684 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) 685 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) 686 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) 687 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 688 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 689 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 690 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 691 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE) 692 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE) 693 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE) 694 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE) 695 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE) 696 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE) 697 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE) 698 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE) 699 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE) 700 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE) 701 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE) 702 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE) 703 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE) 704 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE) 705 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE) 706 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE) 707 708 .globl mol_trampoline 709 .set mol_trampoline, i0x2f00 710 711 . = 0x3000 712 713AltiVecUnavailable: 714 EXCEPTION_PROLOG 715#ifdef CONFIG_ALTIVEC 716 bne load_up_altivec /* if from user, just load it up */ 717#endif /* CONFIG_ALTIVEC */ 718 addi r3,r1,STACK_FRAME_OVERHEAD 719 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception) 720 721PerformanceMonitor: 722 EXCEPTION_PROLOG 723 addi r3,r1,STACK_FRAME_OVERHEAD 724 EXC_XFER_STD(0xf00, performance_monitor_exception) 725 726#ifdef CONFIG_ALTIVEC 727/* Note that the AltiVec support is closely modeled after the FP 728 * support. Changes to one are likely to be applicable to the 729 * other! */ 730load_up_altivec: 731/* 732 * Disable AltiVec for the task which had AltiVec previously, 733 * and save its AltiVec registers in its thread_struct. 734 * Enables AltiVec for use in the kernel on return. 735 * On SMP we know the AltiVec units are free, since we give it up every 736 * switch. -- Kumar 737 */ 738 mfmsr r5 739 oris r5,r5,MSR_VEC@h 740 MTMSRD(r5) /* enable use of AltiVec now */ 741 isync 742/* 743 * For SMP, we don't do lazy AltiVec switching because it just gets too 744 * horrendously complex, especially when a task switches from one CPU 745 * to another. Instead we call giveup_altivec in switch_to. 746 */ 747#ifndef CONFIG_SMP 748 tophys(r6,0) 749 addis r3,r6,last_task_used_altivec@ha 750 lwz r4,last_task_used_altivec@l(r3) 751 cmpwi 0,r4,0 752 beq 1f 753 add r4,r4,r6 754 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */ 755 SAVE_32VRS(0,r10,r4) 756 mfvscr vr0 757 li r10,THREAD_VSCR 758 stvx vr0,r10,r4 759 lwz r5,PT_REGS(r4) 760 add r5,r5,r6 761 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) 762 lis r10,MSR_VEC@h 763 andc r4,r4,r10 /* disable altivec for previous task */ 764 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) 7651: 766#endif /* CONFIG_SMP */ 767 /* enable use of AltiVec after return */ 768 oris r9,r9,MSR_VEC@h 769 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ 770 li r4,1 771 li r10,THREAD_VSCR 772 stw r4,THREAD_USED_VR(r5) 773 lvx vr0,r10,r5 774 mtvscr vr0 775 REST_32VRS(0,r10,r5) 776#ifndef CONFIG_SMP 777 subi r4,r5,THREAD 778 sub r4,r4,r6 779 stw r4,last_task_used_altivec@l(r3) 780#endif /* CONFIG_SMP */ 781 /* restore registers and return */ 782 /* we haven't used ctr or xer or lr */ 783 b fast_exception_return 784 785/* 786 * giveup_altivec(tsk) 787 * Disable AltiVec for the task given as the argument, 788 * and save the AltiVec registers in its thread_struct. 789 * Enables AltiVec for use in the kernel on return. 790 */ 791 792 .globl giveup_altivec 793giveup_altivec: 794 mfmsr r5 795 oris r5,r5,MSR_VEC@h 796 SYNC 797 MTMSRD(r5) /* enable use of AltiVec now */ 798 isync 799 cmpwi 0,r3,0 800 beqlr- /* if no previous owner, done */ 801 addi r3,r3,THREAD /* want THREAD of task */ 802 lwz r5,PT_REGS(r3) 803 cmpwi 0,r5,0 804 SAVE_32VRS(0, r4, r3) 805 mfvscr vr0 806 li r4,THREAD_VSCR 807 stvx vr0,r4,r3 808 beq 1f 809 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) 810 lis r3,MSR_VEC@h 811 andc r4,r4,r3 /* disable AltiVec for previous task */ 812 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) 8131: 814#ifndef CONFIG_SMP 815 li r5,0 816 lis r4,last_task_used_altivec@ha 817 stw r5,last_task_used_altivec@l(r4) 818#endif /* CONFIG_SMP */ 819 blr 820#endif /* CONFIG_ALTIVEC */ 821 822/* 823 * This code is jumped to from the startup code to copy 824 * the kernel image to physical address PHYSICAL_START. 825 */ 826relocate_kernel: 827 addis r9,r26,klimit@ha /* fetch klimit */ 828 lwz r25,klimit@l(r9) 829 addis r25,r25,-KERNELBASE@h 830 lis r3,PHYSICAL_START@h /* Destination base address */ 831 li r6,0 /* Destination offset */ 832 li r5,0x4000 /* # bytes of memory to copy */ 833 bl copy_and_flush /* copy the first 0x4000 bytes */ 834 addi r0,r3,4f@l /* jump to the address of 4f */ 835 mtctr r0 /* in copy and do the rest. */ 836 bctr /* jump to the copy */ 8374: mr r5,r25 838 bl copy_and_flush /* copy the rest */ 839 b turn_on_mmu 840 841/* 842 * Copy routine used to copy the kernel to start at physical address 0 843 * and flush and invalidate the caches as needed. 844 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 845 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 846 */ 847_ENTRY(copy_and_flush) 848 addi r5,r5,-4 849 addi r6,r6,-4 8504: li r0,L1_CACHE_BYTES/4 851 mtctr r0 8523: addi r6,r6,4 /* copy a cache line */ 853 lwzx r0,r6,r4 854 stwx r0,r6,r3 855 bdnz 3b 856 dcbst r6,r3 /* write it to memory */ 857 sync 858 icbi r6,r3 /* flush the icache line */ 859 cmplw 0,r6,r5 860 blt 4b 861 sync /* additional sync needed on g4 */ 862 isync 863 addi r5,r5,4 864 addi r6,r6,4 865 blr 866 867#ifdef CONFIG_SMP 868#ifdef CONFIG_GEMINI 869 .globl __secondary_start_gemini 870__secondary_start_gemini: 871 mfspr r4,SPRN_HID0 872 ori r4,r4,HID0_ICFI 873 li r3,0 874 ori r3,r3,HID0_ICE 875 andc r4,r4,r3 876 mtspr SPRN_HID0,r4 877 sync 878 b __secondary_start 879#endif /* CONFIG_GEMINI */ 880 881 .globl __secondary_start_mpc86xx 882__secondary_start_mpc86xx: 883 mfspr r3, SPRN_PIR 884 stw r3, __secondary_hold_acknowledge@l(0) 885 mr r24, r3 /* cpu # */ 886 b __secondary_start 887 888 .globl __secondary_start_pmac_0 889__secondary_start_pmac_0: 890 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 891 li r24,0 892 b 1f 893 li r24,1 894 b 1f 895 li r24,2 896 b 1f 897 li r24,3 8981: 899 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0 900 set to map the 0xf0000000 - 0xffffffff region */ 901 mfmsr r0 902 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */ 903 SYNC 904 mtmsr r0 905 isync 906 907 .globl __secondary_start 908__secondary_start: 909 /* Copy some CPU settings from CPU 0 */ 910 bl __restore_cpu_setup 911 912 lis r3,-KERNELBASE@h 913 mr r4,r24 914 bl call_setup_cpu /* Call setup_cpu for this CPU */ 915#ifdef CONFIG_6xx 916 lis r3,-KERNELBASE@h 917 bl init_idle_6xx 918#endif /* CONFIG_6xx */ 919 920 /* get current_thread_info and current */ 921 lis r1,secondary_ti@ha 922 tophys(r1,r1) 923 lwz r1,secondary_ti@l(r1) 924 tophys(r2,r1) 925 lwz r2,TI_TASK(r2) 926 927 /* stack */ 928 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 929 li r0,0 930 tophys(r3,r1) 931 stw r0,0(r3) 932 933 /* load up the MMU */ 934 bl load_up_mmu 935 936 /* ptr to phys current thread */ 937 tophys(r4,r2) 938 addi r4,r4,THREAD /* phys address of our thread_struct */ 939 CLR_TOP32(r4) 940 mtspr SPRN_SPRG3,r4 941 li r3,0 942 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ 943 944 /* enable MMU and jump to start_secondary */ 945 li r4,MSR_KERNEL 946 FIX_SRR1(r4,r5) 947 lis r3,start_secondary@h 948 ori r3,r3,start_secondary@l 949 mtspr SPRN_SRR0,r3 950 mtspr SPRN_SRR1,r4 951 SYNC 952 RFI 953#endif /* CONFIG_SMP */ 954 955/* 956 * Those generic dummy functions are kept for CPUs not 957 * included in CONFIG_6xx 958 */ 959#if !defined(CONFIG_6xx) 960_ENTRY(__save_cpu_setup) 961 blr 962_ENTRY(__restore_cpu_setup) 963 blr 964#endif /* !defined(CONFIG_6xx) */ 965 966 967/* 968 * Load stuff into the MMU. Intended to be called with 969 * IR=0 and DR=0. 970 */ 971load_up_mmu: 972 sync /* Force all PTE updates to finish */ 973 isync 974 tlbia /* Clear all TLB entries */ 975 sync /* wait for tlbia/tlbie to finish */ 976 TLBSYNC /* ... on all CPUs */ 977 /* Load the SDR1 register (hash table base & size) */ 978 lis r6,_SDR1@ha 979 tophys(r6,r6) 980 lwz r6,_SDR1@l(r6) 981 mtspr SPRN_SDR1,r6 982 li r0,16 /* load up segment register values */ 983 mtctr r0 /* for context 0 */ 984 lis r3,0x2000 /* Ku = 1, VSID = 0 */ 985 li r4,0 9863: mtsrin r3,r4 987 addi r3,r3,0x111 /* increment VSID */ 988 addis r4,r4,0x1000 /* address of next segment */ 989 bdnz 3b 990 991/* Load the BAT registers with the values set up by MMU_init. 992 MMU_init takes care of whether we're on a 601 or not. */ 993 mfpvr r3 994 srwi r3,r3,16 995 cmpwi r3,1 996 lis r3,BATS@ha 997 addi r3,r3,BATS@l 998 tophys(r3,r3) 999 LOAD_BAT(0,r3,r4,r5) 1000 LOAD_BAT(1,r3,r4,r5) 1001 LOAD_BAT(2,r3,r4,r5) 1002 LOAD_BAT(3,r3,r4,r5) 1003BEGIN_MMU_FTR_SECTION 1004 LOAD_BAT(4,r3,r4,r5) 1005 LOAD_BAT(5,r3,r4,r5) 1006 LOAD_BAT(6,r3,r4,r5) 1007 LOAD_BAT(7,r3,r4,r5) 1008END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) 1009 blr 1010 1011/* 1012 * This is where the main kernel code starts. 1013 */ 1014start_here: 1015 /* ptr to current */ 1016 lis r2,init_task@h 1017 ori r2,r2,init_task@l 1018 /* Set up for using our exception vectors */ 1019 /* ptr to phys current thread */ 1020 tophys(r4,r2) 1021 addi r4,r4,THREAD /* init task's THREAD */ 1022 CLR_TOP32(r4) 1023 mtspr SPRN_SPRG3,r4 1024 li r3,0 1025 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ 1026 1027 /* stack */ 1028 lis r1,init_thread_union@ha 1029 addi r1,r1,init_thread_union@l 1030 li r0,0 1031 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 1032/* 1033 * Do early platform-specific initialization, 1034 * and set up the MMU. 1035 */ 1036 mr r3,r31 1037 mr r4,r30 1038 bl machine_init 1039 bl __save_cpu_setup 1040 bl MMU_init 1041 1042/* 1043 * Go back to running unmapped so we can load up new values 1044 * for SDR1 (hash table pointer) and the segment registers 1045 * and change to using our exception vectors. 1046 */ 1047 lis r4,2f@h 1048 ori r4,r4,2f@l 1049 tophys(r4,r4) 1050 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 1051 FIX_SRR1(r3,r5) 1052 mtspr SPRN_SRR0,r4 1053 mtspr SPRN_SRR1,r3 1054 SYNC 1055 RFI 1056/* Load up the kernel context */ 10572: bl load_up_mmu 1058 1059#ifdef CONFIG_BDI_SWITCH 1060 /* Add helper information for the Abatron bdiGDB debugger. 1061 * We do this here because we know the mmu is disabled, and 1062 * will be enabled for real in just a few instructions. 1063 */ 1064 lis r5, abatron_pteptrs@h 1065 ori r5, r5, abatron_pteptrs@l 1066 stw r5, 0xf0(r0) /* This much match your Abatron config */ 1067 lis r6, swapper_pg_dir@h 1068 ori r6, r6, swapper_pg_dir@l 1069 tophys(r5, r5) 1070 stw r6, 0(r5) 1071#endif /* CONFIG_BDI_SWITCH */ 1072 1073/* Now turn on the MMU for real! */ 1074 li r4,MSR_KERNEL 1075 FIX_SRR1(r4,r5) 1076 lis r3,start_kernel@h 1077 ori r3,r3,start_kernel@l 1078 mtspr SPRN_SRR0,r3 1079 mtspr SPRN_SRR1,r4 1080 SYNC 1081 RFI 1082 1083/* 1084 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next); 1085 * 1086 * Set up the segment registers for a new context. 1087 */ 1088_ENTRY(switch_mmu_context) 1089 lwz r3,MMCONTEXTID(r4) 1090 cmpwi cr0,r3,0 1091 blt- 4f 1092 mulli r3,r3,897 /* multiply context by skew factor */ 1093 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ 1094 addis r3,r3,0x6000 /* Set Ks, Ku bits */ 1095 li r0,NUM_USER_SEGMENTS 1096 mtctr r0 1097 1098#ifdef CONFIG_BDI_SWITCH 1099 /* Context switch the PTE pointer for the Abatron BDI2000. 1100 * The PGDIR is passed as second argument. 1101 */ 1102 lwz r4,MM_PGD(r4) 1103 lis r5, KERNELBASE@h 1104 lwz r5, 0xf0(r5) 1105 stw r4, 0x4(r5) 1106#endif 1107 li r4,0 1108 isync 11093: 1110 mtsrin r3,r4 1111 addi r3,r3,0x111 /* next VSID */ 1112 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */ 1113 addis r4,r4,0x1000 /* address of next segment */ 1114 bdnz 3b 1115 sync 1116 isync 1117 blr 11184: trap 1119 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0 1120 blr 1121 1122/* 1123 * An undocumented "feature" of 604e requires that the v bit 1124 * be cleared before changing BAT values. 1125 * 1126 * Also, newer IBM firmware does not clear bat3 and 4 so 1127 * this makes sure it's done. 1128 * -- Cort 1129 */ 1130clear_bats: 1131 li r10,0 1132 mfspr r9,SPRN_PVR 1133 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ 1134 cmpwi r9, 1 1135 beq 1f 1136 1137 mtspr SPRN_DBAT0U,r10 1138 mtspr SPRN_DBAT0L,r10 1139 mtspr SPRN_DBAT1U,r10 1140 mtspr SPRN_DBAT1L,r10 1141 mtspr SPRN_DBAT2U,r10 1142 mtspr SPRN_DBAT2L,r10 1143 mtspr SPRN_DBAT3U,r10 1144 mtspr SPRN_DBAT3L,r10 11451: 1146 mtspr SPRN_IBAT0U,r10 1147 mtspr SPRN_IBAT0L,r10 1148 mtspr SPRN_IBAT1U,r10 1149 mtspr SPRN_IBAT1L,r10 1150 mtspr SPRN_IBAT2U,r10 1151 mtspr SPRN_IBAT2L,r10 1152 mtspr SPRN_IBAT3U,r10 1153 mtspr SPRN_IBAT3L,r10 1154BEGIN_MMU_FTR_SECTION 1155 /* Here's a tweak: at this point, CPU setup have 1156 * not been called yet, so HIGH_BAT_EN may not be 1157 * set in HID0 for the 745x processors. However, it 1158 * seems that doesn't affect our ability to actually 1159 * write to these SPRs. 1160 */ 1161 mtspr SPRN_DBAT4U,r10 1162 mtspr SPRN_DBAT4L,r10 1163 mtspr SPRN_DBAT5U,r10 1164 mtspr SPRN_DBAT5L,r10 1165 mtspr SPRN_DBAT6U,r10 1166 mtspr SPRN_DBAT6L,r10 1167 mtspr SPRN_DBAT7U,r10 1168 mtspr SPRN_DBAT7L,r10 1169 mtspr SPRN_IBAT4U,r10 1170 mtspr SPRN_IBAT4L,r10 1171 mtspr SPRN_IBAT5U,r10 1172 mtspr SPRN_IBAT5L,r10 1173 mtspr SPRN_IBAT6U,r10 1174 mtspr SPRN_IBAT6L,r10 1175 mtspr SPRN_IBAT7U,r10 1176 mtspr SPRN_IBAT7L,r10 1177END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) 1178 blr 1179 1180flush_tlbs: 1181 lis r10, 0x40 11821: addic. r10, r10, -0x1000 1183 tlbie r10 1184 bgt 1b 1185 sync 1186 blr 1187 1188mmu_off: 1189 addi r4, r3, __after_mmu_off - _start 1190 mfmsr r3 1191 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */ 1192 beqlr 1193 andc r3,r3,r0 1194 mtspr SPRN_SRR0,r4 1195 mtspr SPRN_SRR1,r3 1196 sync 1197 RFI 1198 1199/* 1200 * Use the first pair of BAT registers to map the 1st 16MB 1201 * of RAM to PAGE_OFFSET. From this point on we can't safely 1202 * call OF any more. 1203 */ 1204initial_bats: 1205 lis r11,PAGE_OFFSET@h 1206 mfspr r9,SPRN_PVR 1207 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ 1208 cmpwi 0,r9,1 1209 bne 4f 1210 ori r11,r11,4 /* set up BAT registers for 601 */ 1211 li r8,0x7f /* valid, block length = 8MB */ 1212 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */ 1213 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */ 1214 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ 1215 mtspr SPRN_IBAT0L,r8 /* lower BAT register */ 1216 mtspr SPRN_IBAT1U,r9 1217 mtspr SPRN_IBAT1L,r10 1218 isync 1219 blr 1220 12214: tophys(r8,r11) 1222#ifdef CONFIG_SMP 1223 ori r8,r8,0x12 /* R/W access, M=1 */ 1224#else 1225 ori r8,r8,2 /* R/W access */ 1226#endif /* CONFIG_SMP */ 1227 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */ 1228 1229 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ 1230 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */ 1231 mtspr SPRN_IBAT0L,r8 1232 mtspr SPRN_IBAT0U,r11 1233 isync 1234 blr 1235 1236 1237#ifdef CONFIG_BOOTX_TEXT 1238setup_disp_bat: 1239 /* 1240 * setup the display bat prepared for us in prom.c 1241 */ 1242 mflr r8 1243 bl reloc_offset 1244 mtlr r8 1245 addis r8,r3,disp_BAT@ha 1246 addi r8,r8,disp_BAT@l 1247 cmpwi cr0,r8,0 1248 beqlr 1249 lwz r11,0(r8) 1250 lwz r8,4(r8) 1251 mfspr r9,SPRN_PVR 1252 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ 1253 cmpwi 0,r9,1 1254 beq 1f 1255 mtspr SPRN_DBAT3L,r8 1256 mtspr SPRN_DBAT3U,r11 1257 blr 12581: mtspr SPRN_IBAT3L,r8 1259 mtspr SPRN_IBAT3U,r11 1260 blr 1261#endif /* CONFIG_BOOTX_TEXT */ 1262 1263#ifdef CONFIG_PPC_EARLY_DEBUG_CPM 1264setup_cpm_bat: 1265 lis r8, 0xf000 1266 ori r8, r8, 0x002a 1267 mtspr SPRN_DBAT1L, r8 1268 1269 lis r11, 0xf000 1270 ori r11, r11, (BL_1M << 2) | 2 1271 mtspr SPRN_DBAT1U, r11 1272 1273 blr 1274#endif 1275 1276#ifdef CONFIG_8260 1277/* Jump into the system reset for the rom. 1278 * We first disable the MMU, and then jump to the ROM reset address. 1279 * 1280 * r3 is the board info structure, r4 is the location for starting. 1281 * I use this for building a small kernel that can load other kernels, 1282 * rather than trying to write or rely on a rom monitor that can tftp load. 1283 */ 1284 .globl m8260_gorom 1285m8260_gorom: 1286 mfmsr r0 1287 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */ 1288 sync 1289 mtmsr r0 1290 sync 1291 mfspr r11, SPRN_HID0 1292 lis r10, 0 1293 ori r10,r10,HID0_ICE|HID0_DCE 1294 andc r11, r11, r10 1295 mtspr SPRN_HID0, r11 1296 isync 1297 li r5, MSR_ME|MSR_RI 1298 lis r6,2f@h 1299 addis r6,r6,-KERNELBASE@h 1300 ori r6,r6,2f@l 1301 mtspr SPRN_SRR0,r6 1302 mtspr SPRN_SRR1,r5 1303 isync 1304 sync 1305 rfi 13062: 1307 mtlr r4 1308 blr 1309#endif 1310 1311 1312/* 1313 * We put a few things here that have to be page-aligned. 1314 * This stuff goes at the beginning of the data segment, 1315 * which is page-aligned. 1316 */ 1317 .data 1318 .globl sdata 1319sdata: 1320 .globl empty_zero_page 1321empty_zero_page: 1322 .space 4096 1323 1324 .globl swapper_pg_dir 1325swapper_pg_dir: 1326 .space PGD_TABLE_SIZE 1327 1328 .globl intercept_table 1329intercept_table: 1330 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700 1331 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0 1332 .long 0, 0, 0, i0x1300, 0, 0, 0, 0 1333 .long 0, 0, 0, 0, 0, 0, 0, 0 1334 .long 0, 0, 0, 0, 0, 0, 0, 0 1335 .long 0, 0, 0, 0, 0, 0, 0, 0 1336 1337/* Room for two PTE pointers, usually the kernel and current user pointers 1338 * to their respective root page table. 1339 */ 1340abatron_pteptrs: 1341 .space 8 1342