1 /*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7763.c
3 *
4 * SH7763 support for the clock framework
5 *
6 * Copyright (C) 2005 Paul Mundt
7 * Copyright (C) 2007 Yoshihiro Shimoda
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <asm/clock.h>
16 #include <asm/freq.h>
17 #include <asm/io.h>
18
19 static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
20 static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
21 static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
22
master_clk_init(struct clk * clk)23 static void master_clk_init(struct clk *clk)
24 {
25 clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07];
26 }
27
28 static struct clk_ops sh7763_master_clk_ops = {
29 .init = master_clk_init,
30 };
31
module_clk_recalc(struct clk * clk)32 static void module_clk_recalc(struct clk *clk)
33 {
34 int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
35 clk->rate = clk->parent->rate / p0fc_divisors[idx];
36 }
37
38 static struct clk_ops sh7763_module_clk_ops = {
39 .recalc = module_clk_recalc,
40 };
41
bus_clk_recalc(struct clk * clk)42 static void bus_clk_recalc(struct clk *clk)
43 {
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
45 clk->rate = clk->parent->rate / bfc_divisors[idx];
46 }
47
48 static struct clk_ops sh7763_bus_clk_ops = {
49 .recalc = bus_clk_recalc,
50 };
51
cpu_clk_recalc(struct clk * clk)52 static void cpu_clk_recalc(struct clk *clk)
53 {
54 clk->rate = clk->parent->rate;
55 }
56
57 static struct clk_ops sh7763_cpu_clk_ops = {
58 .recalc = cpu_clk_recalc,
59 };
60
61 static struct clk_ops *sh7763_clk_ops[] = {
62 &sh7763_master_clk_ops,
63 &sh7763_module_clk_ops,
64 &sh7763_bus_clk_ops,
65 &sh7763_cpu_clk_ops,
66 };
67
arch_init_clk_ops(struct clk_ops ** ops,int idx)68 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
69 {
70 if (idx < ARRAY_SIZE(sh7763_clk_ops))
71 *ops = sh7763_clk_ops[idx];
72 }
73
shyway_clk_recalc(struct clk * clk)74 static void shyway_clk_recalc(struct clk *clk)
75 {
76 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
77 clk->rate = clk->parent->rate / cfc_divisors[idx];
78 }
79
80 static struct clk_ops sh7763_shyway_clk_ops = {
81 .recalc = shyway_clk_recalc,
82 };
83
84 static struct clk sh7763_shyway_clk = {
85 .name = "shyway_clk",
86 .flags = CLK_ALWAYS_ENABLED,
87 .ops = &sh7763_shyway_clk_ops,
88 };
89
90 /*
91 * Additional SH7763-specific on-chip clocks that aren't already part of the
92 * clock framework
93 */
94 static struct clk *sh7763_onchip_clocks[] = {
95 &sh7763_shyway_clk,
96 };
97
sh7763_clk_init(void)98 static int __init sh7763_clk_init(void)
99 {
100 struct clk *clk = clk_get(NULL, "master_clk");
101 int i;
102
103 for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
104 struct clk *clkp = sh7763_onchip_clocks[i];
105
106 clkp->parent = clk;
107 clk_register(clkp);
108 clk_enable(clkp);
109 }
110
111 /*
112 * Now that we have the rest of the clocks registered, we need to
113 * force the parent clock to propagate so that these clocks will
114 * automatically figure out their rate. We cheat by handing the
115 * parent clock its current rate and forcing child propagation.
116 */
117 clk_set_rate(clk, clk_get_rate(clk));
118
119 clk_put(clk);
120
121 return 0;
122 }
123
124 arch_initcall(sh7763_clk_init);
125
126