1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __CXIO_HAL_H__
33 #define __CXIO_HAL_H__
34
35 #include <linux/list.h>
36 #include <linux/mutex.h>
37
38 #include "t3_cpl.h"
39 #include "t3cdev.h"
40 #include "cxgb3_ctl_defs.h"
41 #include "cxio_wr.h"
42
43 #define T3_CTRL_QP_ID FW_RI_SGEEC_START
44 #define T3_CTL_QP_TID FW_RI_TID_START
45 #define T3_CTRL_QP_SIZE_LOG2 8
46 #define T3_CTRL_CQ_ID 0
47
48 #define T3_MAX_NUM_RI (1<<15)
49 #define T3_MAX_NUM_QP (1<<15)
50 #define T3_MAX_NUM_CQ (1<<15)
51 #define T3_MAX_NUM_PD (1<<15)
52 #define T3_MAX_PBL_SIZE 256
53 #define T3_MAX_RQ_SIZE 1024
54 #define T3_MAX_QP_DEPTH (T3_MAX_RQ_SIZE-1)
55 #define T3_MAX_CQ_DEPTH 8192
56 #define T3_MAX_NUM_STAG (1<<15)
57 #define T3_MAX_MR_SIZE 0x100000000ULL
58 #define T3_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
59
60 #define T3_STAG_UNSET 0xffffffff
61
62 #define T3_MAX_DEV_NAME_LEN 32
63
64 struct cxio_hal_ctrl_qp {
65 u32 wptr;
66 u32 rptr;
67 struct mutex lock; /* for the wtpr, can sleep */
68 wait_queue_head_t waitq;/* wait for RspQ/CQE msg */
69 union t3_wr *workq; /* the work request queue */
70 dma_addr_t dma_addr; /* pci bus address of the workq */
71 DECLARE_PCI_UNMAP_ADDR(mapping)
72 void __iomem *doorbell;
73 };
74
75 struct cxio_hal_resource {
76 struct kfifo *tpt_fifo;
77 spinlock_t tpt_fifo_lock;
78 struct kfifo *qpid_fifo;
79 spinlock_t qpid_fifo_lock;
80 struct kfifo *cqid_fifo;
81 spinlock_t cqid_fifo_lock;
82 struct kfifo *pdid_fifo;
83 spinlock_t pdid_fifo_lock;
84 };
85
86 struct cxio_qpid_list {
87 struct list_head entry;
88 u32 qpid;
89 };
90
91 struct cxio_ucontext {
92 struct list_head qpids;
93 struct mutex lock;
94 };
95
96 struct cxio_rdev {
97 char dev_name[T3_MAX_DEV_NAME_LEN];
98 struct t3cdev *t3cdev_p;
99 struct rdma_info rnic_info;
100 struct adap_ports port_info;
101 struct cxio_hal_resource *rscp;
102 struct cxio_hal_ctrl_qp ctrl_qp;
103 void *ulp;
104 unsigned long qpshift;
105 u32 qpnr;
106 u32 qpmask;
107 struct cxio_ucontext uctx;
108 struct gen_pool *pbl_pool;
109 struct gen_pool *rqt_pool;
110 struct list_head entry;
111 };
112
cxio_num_stags(struct cxio_rdev * rdev_p)113 static inline int cxio_num_stags(struct cxio_rdev *rdev_p)
114 {
115 return min((int)T3_MAX_NUM_STAG, (int)((rdev_p->rnic_info.tpt_top - rdev_p->rnic_info.tpt_base) >> 5));
116 }
117
118 typedef void (*cxio_hal_ev_callback_func_t) (struct cxio_rdev * rdev_p,
119 struct sk_buff * skb);
120
121 #define RSPQ_CQID(rsp) (be32_to_cpu(rsp->cq_ptrid) & 0xffff)
122 #define RSPQ_CQPTR(rsp) ((be32_to_cpu(rsp->cq_ptrid) >> 16) & 0xffff)
123 #define RSPQ_GENBIT(rsp) ((be32_to_cpu(rsp->flags) >> 16) & 1)
124 #define RSPQ_OVERFLOW(rsp) ((be32_to_cpu(rsp->flags) >> 17) & 1)
125 #define RSPQ_AN(rsp) ((be32_to_cpu(rsp->flags) >> 18) & 1)
126 #define RSPQ_SE(rsp) ((be32_to_cpu(rsp->flags) >> 19) & 1)
127 #define RSPQ_NOTIFY(rsp) ((be32_to_cpu(rsp->flags) >> 20) & 1)
128 #define RSPQ_CQBRANCH(rsp) ((be32_to_cpu(rsp->flags) >> 21) & 1)
129 #define RSPQ_CREDIT_THRESH(rsp) ((be32_to_cpu(rsp->flags) >> 22) & 1)
130
131 struct respQ_msg_t {
132 __be32 flags; /* flit 0 */
133 __be32 cq_ptrid;
134 __be64 rsvd; /* flit 1 */
135 struct t3_cqe cqe; /* flits 2-3 */
136 };
137
138 enum t3_cq_opcode {
139 CQ_ARM_AN = 0x2,
140 CQ_ARM_SE = 0x6,
141 CQ_FORCE_AN = 0x3,
142 CQ_CREDIT_UPDATE = 0x7
143 };
144
145 int cxio_rdev_open(struct cxio_rdev *rdev);
146 void cxio_rdev_close(struct cxio_rdev *rdev);
147 int cxio_hal_cq_op(struct cxio_rdev *rdev, struct t3_cq *cq,
148 enum t3_cq_opcode op, u32 credit);
149 int cxio_create_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
150 int cxio_destroy_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
151 int cxio_resize_cq(struct cxio_rdev *rdev, struct t3_cq *cq);
152 void cxio_release_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
153 void cxio_init_ucontext(struct cxio_rdev *rdev, struct cxio_ucontext *uctx);
154 int cxio_create_qp(struct cxio_rdev *rdev, u32 kernel_domain, struct t3_wq *wq,
155 struct cxio_ucontext *uctx);
156 int cxio_destroy_qp(struct cxio_rdev *rdev, struct t3_wq *wq,
157 struct cxio_ucontext *uctx);
158 int cxio_peek_cq(struct t3_wq *wr, struct t3_cq *cq, int opcode);
159 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
160 u32 pbl_addr, u32 pbl_size);
161 int cxio_register_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
162 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
163 u8 page_size, u32 pbl_size, u32 pbl_addr);
164 int cxio_reregister_phys_mem(struct cxio_rdev *rdev, u32 * stag, u32 pdid,
165 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
166 u8 page_size, u32 pbl_size, u32 pbl_addr);
167 int cxio_dereg_mem(struct cxio_rdev *rdev, u32 stag, u32 pbl_size,
168 u32 pbl_addr);
169 int cxio_allocate_window(struct cxio_rdev *rdev, u32 * stag, u32 pdid);
170 int cxio_allocate_stag(struct cxio_rdev *rdev, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr);
171 int cxio_deallocate_window(struct cxio_rdev *rdev, u32 stag);
172 int cxio_rdma_init(struct cxio_rdev *rdev, struct t3_rdma_init_attr *attr);
173 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
174 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb);
175 u32 cxio_hal_get_pdid(struct cxio_hal_resource *rscp);
176 void cxio_hal_put_pdid(struct cxio_hal_resource *rscp, u32 pdid);
177 int __init cxio_hal_init(void);
178 void __exit cxio_hal_exit(void);
179 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count);
180 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count);
181 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
182 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
183 void cxio_flush_hw_cq(struct t3_cq *cq);
184 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
185 u8 *cqe_flushed, u64 *cookie, u32 *credit);
186
187 #define MOD "iw_cxgb3: "
188 #define PDBG(fmt, args...) pr_debug(MOD fmt, ## args)
189
190 #ifdef DEBUG
191 void cxio_dump_tpt(struct cxio_rdev *rev, u32 stag);
192 void cxio_dump_pbl(struct cxio_rdev *rev, u32 pbl_addr, uint len, u8 shift);
193 void cxio_dump_wqe(union t3_wr *wqe);
194 void cxio_dump_wce(struct t3_cqe *wce);
195 void cxio_dump_rqt(struct cxio_rdev *rdev, u32 hwtid, int nents);
196 void cxio_dump_tcb(struct cxio_rdev *rdev, u32 hwtid);
197 #endif
198
199 #endif
200