1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #ifndef _E1000_REGS_H_ 29 #define _E1000_REGS_H_ 30 31 #define E1000_CTRL 0x00000 /* Device Control - RW */ 32 #define E1000_STATUS 0x00008 /* Device Status - RO */ 33 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 34 #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 35 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 36 #define E1000_MDIC 0x00020 /* MDI Control - RW */ 37 #define E1000_SCTL 0x00024 /* SerDes Control - RW */ 38 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 39 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 40 #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 41 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ 42 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 43 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 44 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 45 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 46 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 47 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 48 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 49 #define E1000_RCTL 0x00100 /* RX Control - RW */ 50 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 51 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 52 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 53 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 54 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 55 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 56 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 57 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 58 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 59 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ 60 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 61 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 62 #define E1000_TCTL 0x00400 /* TX Control - RW */ 63 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 64 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 65 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 66 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 67 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 68 #define E1000_PBS 0x01008 /* Packet Buffer Size */ 69 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 70 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 71 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ 72 #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ 73 #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ 74 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 75 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 76 #define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) 77 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ 78 /* Split and Replication RX Control - RW */ 79 /* 80 * Convenience macros 81 * 82 * Note: "_n" is the queue number of the register to be written to. 83 * 84 * Example usage: 85 * E1000_RDBAL_REG(current_rx_queue) 86 */ 87 #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \ 88 : (0x0C000 + ((_n) * 0x40))) 89 #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \ 90 : (0x0C004 + ((_n) * 0x40))) 91 #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \ 92 : (0x0C008 + ((_n) * 0x40))) 93 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \ 94 : (0x0C00C + ((_n) * 0x40))) 95 #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \ 96 : (0x0C010 + ((_n) * 0x40))) 97 #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \ 98 : (0x0C018 + ((_n) * 0x40))) 99 #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \ 100 : (0x0C028 + ((_n) * 0x40))) 101 #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \ 102 : (0x0E000 + ((_n) * 0x40))) 103 #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \ 104 : (0x0E004 + ((_n) * 0x40))) 105 #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \ 106 : (0x0E008 + ((_n) * 0x40))) 107 #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \ 108 : (0x0E010 + ((_n) * 0x40))) 109 #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \ 110 : (0x0E018 + ((_n) * 0x40))) 111 #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ 112 : (0x0E028 + ((_n) * 0x40))) 113 #define E1000_TARC(_n) (0x03840 + (_n << 8)) 114 #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) 115 #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) 116 #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ 117 : (0x0E038 + ((_n) * 0x40))) 118 #define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \ 119 : (0x0E03C + ((_n) * 0x40))) 120 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 121 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 122 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 123 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 124 #define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */ 125 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 126 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 127 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 128 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 129 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 130 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 131 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 132 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 133 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 134 #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 135 #define E1000_DC 0x04030 /* Defer Count - R/clr */ 136 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 137 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 138 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 139 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 140 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 141 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 142 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 143 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 144 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 145 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 146 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 147 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 148 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 149 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 150 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 151 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 152 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 153 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 154 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 155 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 156 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 157 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 158 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 159 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 160 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 161 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 162 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 163 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 164 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 165 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 166 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 167 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 168 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 169 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 170 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 171 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 172 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 173 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 174 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 175 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 176 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 177 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 178 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 179 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 180 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 181 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 182 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 183 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 184 /* Interrupt Cause Rx Packet Timer Expire Count */ 185 #define E1000_ICRXPTC 0x04104 186 /* Interrupt Cause Rx Absolute Timer Expire Count */ 187 #define E1000_ICRXATC 0x04108 188 /* Interrupt Cause Tx Packet Timer Expire Count */ 189 #define E1000_ICTXPTC 0x0410C 190 /* Interrupt Cause Tx Absolute Timer Expire Count */ 191 #define E1000_ICTXATC 0x04110 192 /* Interrupt Cause Tx Queue Empty Count */ 193 #define E1000_ICTXQEC 0x04118 194 /* Interrupt Cause Tx Queue Minimum Threshold Count */ 195 #define E1000_ICTXQMTC 0x0411C 196 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 197 #define E1000_ICRXDMTC 0x04120 198 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 199 #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ 200 #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ 201 #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ 202 #define E1000_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */ 203 #define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ 204 #define E1000_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */ 205 #define E1000_RPTHC 0x04104 /* Rx Packets To Host */ 206 #define E1000_HGPTC 0x04118 /* Host Good Packets TX Count */ 207 #define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */ 208 #define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ 209 #define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ 210 #define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ 211 #define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ 212 #define E1000_LENERRS 0x04138 /* Length Errors Count */ 213 #define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ 214 #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ 215 #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ 216 #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ 217 #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ 218 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 219 #define E1000_RLPML 0x05004 /* RX Long Packet Max Length */ 220 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 221 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 222 #define E1000_RA 0x05400 /* Receive Address - RW Array */ 223 #define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW Array */ 224 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 225 (0x054E0 + ((_i - 16) * 8))) 226 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 227 (0x054E4 + ((_i - 16) * 8))) 228 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 229 #define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */ 230 #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 231 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 232 #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 233 #define E1000_MANC 0x05820 /* Management Control - RW */ 234 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 235 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 236 #define E1000_HOST_IF 0x08800 /* Host Interface */ 237 238 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 239 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 240 #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ 241 #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ 242 #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ 243 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 244 #define E1000_SWSM 0x05B50 /* SW Semaphore */ 245 #define E1000_FWSM 0x05B54 /* FW Semaphore */ 246 #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ 247 #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ 248 #define E1000_HICR 0x08F00 /* Host Inteface Control */ 249 250 /* RSS registers */ 251 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 252 #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ 253 #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ 254 #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ 255 /* MSI-X Allocation Register (_i) - RW */ 256 #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) 257 /* MSI-X Table entry addr low reg 0 - RW */ 258 #define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) 259 /* MSI-X Table entry addr upper reg 0 - RW */ 260 #define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) 261 /* MSI-X Table entry message reg 0 - RW */ 262 #define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) 263 /* MSI-X Table entry vector ctrl reg 0 - RW */ 264 #define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) 265 /* Redirection Table - RW Array */ 266 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) 267 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ 268 269 #define wr32(reg, value) (writel(value, hw->hw_addr + reg)) 270 #define rd32(reg) (readl(hw->hw_addr + reg)) 271 #define wrfl() ((void)rd32(E1000_STATUS)) 272 273 #define array_wr32(reg, offset, value) \ 274 (writel(value, hw->hw_addr + reg + ((offset) << 2))) 275 #define array_rd32(reg, offset) \ 276 (readl(hw->hw_addr + reg + ((offset) << 2))) 277 278 #endif 279