1 /* 2 * Copyright (c) 2008 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef REG_H 18 #define REG_H 19 20 #define AR_CR 0x0008 21 #define AR_CR_RXE 0x00000004 22 #define AR_CR_RXD 0x00000020 23 #define AR_CR_SWI 0x00000040 24 25 #define AR_RXDP 0x000C 26 27 #define AR_CFG 0x0014 28 #define AR_CFG_SWTD 0x00000001 29 #define AR_CFG_SWTB 0x00000002 30 #define AR_CFG_SWRD 0x00000004 31 #define AR_CFG_SWRB 0x00000008 32 #define AR_CFG_SWRG 0x00000010 33 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 34 #define AR_CFG_PHOK 0x00000100 35 #define AR_CFG_CLK_GATE_DIS 0x00000400 36 #define AR_CFG_EEBS 0x00000200 37 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 38 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 39 40 #define AR_MIRT 0x0020 41 #define AR_MIRT_VAL 0x0000ffff 42 #define AR_MIRT_VAL_S 16 43 44 #define AR_IER 0x0024 45 #define AR_IER_ENABLE 0x00000001 46 #define AR_IER_DISABLE 0x00000000 47 48 #define AR_TIMT 0x0028 49 #define AR_TIMT_LAST 0x0000ffff 50 #define AR_TIMT_LAST_S 0 51 #define AR_TIMT_FIRST 0xffff0000 52 #define AR_TIMT_FIRST_S 16 53 54 #define AR_RIMT 0x002C 55 #define AR_RIMT_LAST 0x0000ffff 56 #define AR_RIMT_LAST_S 0 57 #define AR_RIMT_FIRST 0xffff0000 58 #define AR_RIMT_FIRST_S 16 59 60 #define AR_DMASIZE_4B 0x00000000 61 #define AR_DMASIZE_8B 0x00000001 62 #define AR_DMASIZE_16B 0x00000002 63 #define AR_DMASIZE_32B 0x00000003 64 #define AR_DMASIZE_64B 0x00000004 65 #define AR_DMASIZE_128B 0x00000005 66 #define AR_DMASIZE_256B 0x00000006 67 #define AR_DMASIZE_512B 0x00000007 68 69 #define AR_TXCFG 0x0030 70 #define AR_TXCFG_DMASZ_MASK 0x00000003 71 #define AR_TXCFG_DMASZ_4B 0 72 #define AR_TXCFG_DMASZ_8B 1 73 #define AR_TXCFG_DMASZ_16B 2 74 #define AR_TXCFG_DMASZ_32B 3 75 #define AR_TXCFG_DMASZ_64B 4 76 #define AR_TXCFG_DMASZ_128B 5 77 #define AR_TXCFG_DMASZ_256B 6 78 #define AR_TXCFG_DMASZ_512B 7 79 #define AR_FTRIG 0x000003F0 80 #define AR_FTRIG_S 4 81 #define AR_FTRIG_IMMED 0x00000000 82 #define AR_FTRIG_64B 0x00000010 83 #define AR_FTRIG_128B 0x00000020 84 #define AR_FTRIG_192B 0x00000030 85 #define AR_FTRIG_256B 0x00000040 86 #define AR_FTRIG_512B 0x00000080 87 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 88 89 #define AR_RXCFG 0x0034 90 #define AR_RXCFG_CHIRP 0x00000008 91 #define AR_RXCFG_ZLFDMA 0x00000010 92 #define AR_RXCFG_DMASZ_MASK 0x00000007 93 #define AR_RXCFG_DMASZ_4B 0 94 #define AR_RXCFG_DMASZ_8B 1 95 #define AR_RXCFG_DMASZ_16B 2 96 #define AR_RXCFG_DMASZ_32B 3 97 #define AR_RXCFG_DMASZ_64B 4 98 #define AR_RXCFG_DMASZ_128B 5 99 #define AR_RXCFG_DMASZ_256B 6 100 #define AR_RXCFG_DMASZ_512B 7 101 102 #define AR_MIBC 0x0040 103 #define AR_MIBC_COW 0x00000001 104 #define AR_MIBC_FMC 0x00000002 105 #define AR_MIBC_CMC 0x00000004 106 #define AR_MIBC_MCS 0x00000008 107 108 #define AR_TOPS 0x0044 109 #define AR_TOPS_MASK 0x0000FFFF 110 111 #define AR_RXNPTO 0x0048 112 #define AR_RXNPTO_MASK 0x000003FF 113 114 #define AR_TXNPTO 0x004C 115 #define AR_TXNPTO_MASK 0x000003FF 116 #define AR_TXNPTO_QCU_MASK 0x000FFC00 117 118 #define AR_RPGTO 0x0050 119 #define AR_RPGTO_MASK 0x000003FF 120 121 #define AR_RPCNT 0x0054 122 #define AR_RPCNT_MASK 0x0000001F 123 124 #define AR_MACMISC 0x0058 125 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 126 #define AR_MACMISC_DMA_OBS 0x000001E0 127 #define AR_MACMISC_DMA_OBS_S 5 128 #define AR_MACMISC_DMA_OBS_LINE_0 0 129 #define AR_MACMISC_DMA_OBS_LINE_1 1 130 #define AR_MACMISC_DMA_OBS_LINE_2 2 131 #define AR_MACMISC_DMA_OBS_LINE_3 3 132 #define AR_MACMISC_DMA_OBS_LINE_4 4 133 #define AR_MACMISC_DMA_OBS_LINE_5 5 134 #define AR_MACMISC_DMA_OBS_LINE_6 6 135 #define AR_MACMISC_DMA_OBS_LINE_7 7 136 #define AR_MACMISC_DMA_OBS_LINE_8 8 137 #define AR_MACMISC_MISC_OBS 0x00000E00 138 #define AR_MACMISC_MISC_OBS_S 9 139 #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 140 #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 141 #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 142 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 143 #define AR_MACMISC_MISC_OBS_BUS_1 1 144 145 #define AR_GTXTO 0x0064 146 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF 147 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 148 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 149 150 #define AR_GTTM 0x0068 151 #define AR_GTTM_USEC 0x00000001 152 #define AR_GTTM_IGNORE_IDLE 0x00000002 153 #define AR_GTTM_RESET_IDLE 0x00000004 154 #define AR_GTTM_CST_USEC 0x00000008 155 156 #define AR_CST 0x006C 157 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF 158 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 159 #define AR_CST_TIMEOUT_LIMIT_S 16 160 161 #define AR_SREV_VERSION_9100 0x014 162 163 #define AR_SREV_5416_V20_OR_LATER(_ah) \ 164 (AR_SREV_9100((_ah)) || AR_SREV_5416_20_OR_LATER(_ah)) 165 #define AR_SREV_5416_V22_OR_LATER(_ah) \ 166 (AR_SREV_9100((_ah)) || AR_SREV_5416_22_OR_LATER(_ah)) 167 168 #define AR_ISR 0x0080 169 #define AR_ISR_RXOK 0x00000001 170 #define AR_ISR_RXDESC 0x00000002 171 #define AR_ISR_RXERR 0x00000004 172 #define AR_ISR_RXNOPKT 0x00000008 173 #define AR_ISR_RXEOL 0x00000010 174 #define AR_ISR_RXORN 0x00000020 175 #define AR_ISR_TXOK 0x00000040 176 #define AR_ISR_TXDESC 0x00000080 177 #define AR_ISR_TXERR 0x00000100 178 #define AR_ISR_TXNOPKT 0x00000200 179 #define AR_ISR_TXEOL 0x00000400 180 #define AR_ISR_TXURN 0x00000800 181 #define AR_ISR_MIB 0x00001000 182 #define AR_ISR_SWI 0x00002000 183 #define AR_ISR_RXPHY 0x00004000 184 #define AR_ISR_RXKCM 0x00008000 185 #define AR_ISR_SWBA 0x00010000 186 #define AR_ISR_BRSSI 0x00020000 187 #define AR_ISR_BMISS 0x00040000 188 #define AR_ISR_BNR 0x00100000 189 #define AR_ISR_RXCHIRP 0x00200000 190 #define AR_ISR_BCNMISC 0x00800000 191 #define AR_ISR_TIM 0x00800000 192 #define AR_ISR_QCBROVF 0x02000000 193 #define AR_ISR_QCBRURN 0x04000000 194 #define AR_ISR_QTRIG 0x08000000 195 #define AR_ISR_GENTMR 0x10000000 196 197 #define AR_ISR_TXMINTR 0x00080000 198 #define AR_ISR_RXMINTR 0x01000000 199 #define AR_ISR_TXINTM 0x40000000 200 #define AR_ISR_RXINTM 0x80000000 201 202 #define AR_ISR_S0 0x0084 203 #define AR_ISR_S0_QCU_TXOK 0x000003FF 204 #define AR_ISR_S0_QCU_TXOK_S 0 205 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 206 #define AR_ISR_S0_QCU_TXDESC_S 16 207 208 #define AR_ISR_S1 0x0088 209 #define AR_ISR_S1_QCU_TXERR 0x000003FF 210 #define AR_ISR_S1_QCU_TXERR_S 0 211 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 212 #define AR_ISR_S1_QCU_TXEOL_S 16 213 214 #define AR_ISR_S2 0x008c 215 #define AR_ISR_S2_QCU_TXURN 0x000003FF 216 #define AR_ISR_S2_CST 0x00400000 217 #define AR_ISR_S2_GTT 0x00800000 218 #define AR_ISR_S2_TIM 0x01000000 219 #define AR_ISR_S2_CABEND 0x02000000 220 #define AR_ISR_S2_DTIMSYNC 0x04000000 221 #define AR_ISR_S2_BCNTO 0x08000000 222 #define AR_ISR_S2_CABTO 0x10000000 223 #define AR_ISR_S2_DTIM 0x20000000 224 #define AR_ISR_S2_TSFOOR 0x40000000 225 #define AR_ISR_S2_TBTT_TIME 0x80000000 226 227 #define AR_ISR_S3 0x0090 228 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF 229 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 230 231 #define AR_ISR_S4 0x0094 232 #define AR_ISR_S4_QCU_QTRIG 0x000003FF 233 #define AR_ISR_S4_RESV0 0xFFFFFC00 234 235 #define AR_ISR_S5 0x0098 236 #define AR_ISR_S5_TIMER_TRIG 0x000000FF 237 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 238 #define AR_ISR_S5_TIM_TIMER 0x00000010 239 #define AR_ISR_S5_DTIM_TIMER 0x00000020 240 #define AR_ISR_S5_S 0x00d8 241 #define AR_IMR_S5 0x00b8 242 #define AR_IMR_S5_TIM_TIMER 0x00000010 243 #define AR_IMR_S5_DTIM_TIMER 0x00000020 244 245 246 #define AR_IMR 0x00a0 247 #define AR_IMR_RXOK 0x00000001 248 #define AR_IMR_RXDESC 0x00000002 249 #define AR_IMR_RXERR 0x00000004 250 #define AR_IMR_RXNOPKT 0x00000008 251 #define AR_IMR_RXEOL 0x00000010 252 #define AR_IMR_RXORN 0x00000020 253 #define AR_IMR_TXOK 0x00000040 254 #define AR_IMR_TXDESC 0x00000080 255 #define AR_IMR_TXERR 0x00000100 256 #define AR_IMR_TXNOPKT 0x00000200 257 #define AR_IMR_TXEOL 0x00000400 258 #define AR_IMR_TXURN 0x00000800 259 #define AR_IMR_MIB 0x00001000 260 #define AR_IMR_SWI 0x00002000 261 #define AR_IMR_RXPHY 0x00004000 262 #define AR_IMR_RXKCM 0x00008000 263 #define AR_IMR_SWBA 0x00010000 264 #define AR_IMR_BRSSI 0x00020000 265 #define AR_IMR_BMISS 0x00040000 266 #define AR_IMR_BNR 0x00100000 267 #define AR_IMR_RXCHIRP 0x00200000 268 #define AR_IMR_BCNMISC 0x00800000 269 #define AR_IMR_TIM 0x00800000 270 #define AR_IMR_QCBROVF 0x02000000 271 #define AR_IMR_QCBRURN 0x04000000 272 #define AR_IMR_QTRIG 0x08000000 273 #define AR_IMR_GENTMR 0x10000000 274 275 #define AR_IMR_TXMINTR 0x00080000 276 #define AR_IMR_RXMINTR 0x01000000 277 #define AR_IMR_TXINTM 0x40000000 278 #define AR_IMR_RXINTM 0x80000000 279 280 #define AR_IMR_S0 0x00a4 281 #define AR_IMR_S0_QCU_TXOK 0x000003FF 282 #define AR_IMR_S0_QCU_TXOK_S 0 283 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 284 #define AR_IMR_S0_QCU_TXDESC_S 16 285 286 #define AR_IMR_S1 0x00a8 287 #define AR_IMR_S1_QCU_TXERR 0x000003FF 288 #define AR_IMR_S1_QCU_TXERR_S 0 289 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 290 #define AR_IMR_S1_QCU_TXEOL_S 16 291 292 #define AR_IMR_S2 0x00ac 293 #define AR_IMR_S2_QCU_TXURN 0x000003FF 294 #define AR_IMR_S2_QCU_TXURN_S 0 295 #define AR_IMR_S2_CST 0x00400000 296 #define AR_IMR_S2_GTT 0x00800000 297 #define AR_IMR_S2_TIM 0x01000000 298 #define AR_IMR_S2_CABEND 0x02000000 299 #define AR_IMR_S2_DTIMSYNC 0x04000000 300 #define AR_IMR_S2_BCNTO 0x08000000 301 #define AR_IMR_S2_CABTO 0x10000000 302 #define AR_IMR_S2_DTIM 0x20000000 303 #define AR_IMR_S2_TSFOOR 0x40000000 304 305 #define AR_IMR_S3 0x00b0 306 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF 307 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 308 #define AR_IMR_S3_QCU_QCBRURN_S 16 309 310 #define AR_IMR_S4 0x00b4 311 #define AR_IMR_S4_QCU_QTRIG 0x000003FF 312 #define AR_IMR_S4_RESV0 0xFFFFFC00 313 314 #define AR_IMR_S5 0x00b8 315 #define AR_IMR_S5_TIMER_TRIG 0x000000FF 316 #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 317 318 319 #define AR_ISR_RAC 0x00c0 320 #define AR_ISR_S0_S 0x00c4 321 #define AR_ISR_S0_QCU_TXOK 0x000003FF 322 #define AR_ISR_S0_QCU_TXOK_S 0 323 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 324 #define AR_ISR_S0_QCU_TXDESC_S 16 325 326 #define AR_ISR_S1_S 0x00c8 327 #define AR_ISR_S1_QCU_TXERR 0x000003FF 328 #define AR_ISR_S1_QCU_TXERR_S 0 329 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 330 #define AR_ISR_S1_QCU_TXEOL_S 16 331 332 #define AR_ISR_S2_S 0x00cc 333 #define AR_ISR_S3_S 0x00d0 334 #define AR_ISR_S4_S 0x00d4 335 #define AR_ISR_S5_S 0x00d8 336 #define AR_DMADBG_0 0x00e0 337 #define AR_DMADBG_1 0x00e4 338 #define AR_DMADBG_2 0x00e8 339 #define AR_DMADBG_3 0x00ec 340 #define AR_DMADBG_4 0x00f0 341 #define AR_DMADBG_5 0x00f4 342 #define AR_DMADBG_6 0x00f8 343 #define AR_DMADBG_7 0x00fc 344 345 #define AR_NUM_QCU 10 346 #define AR_QCU_0 0x0001 347 #define AR_QCU_1 0x0002 348 #define AR_QCU_2 0x0004 349 #define AR_QCU_3 0x0008 350 #define AR_QCU_4 0x0010 351 #define AR_QCU_5 0x0020 352 #define AR_QCU_6 0x0040 353 #define AR_QCU_7 0x0080 354 #define AR_QCU_8 0x0100 355 #define AR_QCU_9 0x0200 356 357 #define AR_Q0_TXDP 0x0800 358 #define AR_Q1_TXDP 0x0804 359 #define AR_Q2_TXDP 0x0808 360 #define AR_Q3_TXDP 0x080c 361 #define AR_Q4_TXDP 0x0810 362 #define AR_Q5_TXDP 0x0814 363 #define AR_Q6_TXDP 0x0818 364 #define AR_Q7_TXDP 0x081c 365 #define AR_Q8_TXDP 0x0820 366 #define AR_Q9_TXDP 0x0824 367 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) 368 369 #define AR_Q_TXE 0x0840 370 #define AR_Q_TXE_M 0x000003FF 371 372 #define AR_Q_TXD 0x0880 373 #define AR_Q_TXD_M 0x000003FF 374 375 #define AR_Q0_CBRCFG 0x08c0 376 #define AR_Q1_CBRCFG 0x08c4 377 #define AR_Q2_CBRCFG 0x08c8 378 #define AR_Q3_CBRCFG 0x08cc 379 #define AR_Q4_CBRCFG 0x08d0 380 #define AR_Q5_CBRCFG 0x08d4 381 #define AR_Q6_CBRCFG 0x08d8 382 #define AR_Q7_CBRCFG 0x08dc 383 #define AR_Q8_CBRCFG 0x08e0 384 #define AR_Q9_CBRCFG 0x08e4 385 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) 386 #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF 387 #define AR_Q_CBRCFG_INTERVAL_S 0 388 #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 389 #define AR_Q_CBRCFG_OVF_THRESH_S 24 390 391 #define AR_Q0_RDYTIMECFG 0x0900 392 #define AR_Q1_RDYTIMECFG 0x0904 393 #define AR_Q2_RDYTIMECFG 0x0908 394 #define AR_Q3_RDYTIMECFG 0x090c 395 #define AR_Q4_RDYTIMECFG 0x0910 396 #define AR_Q5_RDYTIMECFG 0x0914 397 #define AR_Q6_RDYTIMECFG 0x0918 398 #define AR_Q7_RDYTIMECFG 0x091c 399 #define AR_Q8_RDYTIMECFG 0x0920 400 #define AR_Q9_RDYTIMECFG 0x0924 401 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) 402 #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF 403 #define AR_Q_RDYTIMECFG_DURATION_S 0 404 #define AR_Q_RDYTIMECFG_EN 0x01000000 405 406 #define AR_Q_ONESHOTARM_SC 0x0940 407 #define AR_Q_ONESHOTARM_SC_M 0x000003FF 408 #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 409 410 #define AR_Q_ONESHOTARM_CC 0x0980 411 #define AR_Q_ONESHOTARM_CC_M 0x000003FF 412 #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 413 414 #define AR_Q0_MISC 0x09c0 415 #define AR_Q1_MISC 0x09c4 416 #define AR_Q2_MISC 0x09c8 417 #define AR_Q3_MISC 0x09cc 418 #define AR_Q4_MISC 0x09d0 419 #define AR_Q5_MISC 0x09d4 420 #define AR_Q6_MISC 0x09d8 421 #define AR_Q7_MISC 0x09dc 422 #define AR_Q8_MISC 0x09e0 423 #define AR_Q9_MISC 0x09e4 424 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) 425 #define AR_Q_MISC_FSP 0x0000000F 426 #define AR_Q_MISC_FSP_ASAP 0 427 #define AR_Q_MISC_FSP_CBR 1 428 #define AR_Q_MISC_FSP_DBA_GATED 2 429 #define AR_Q_MISC_FSP_TIM_GATED 3 430 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 431 #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 432 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 433 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 434 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 435 #define AR_Q_MISC_BEACON_USE 0x00000080 436 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 437 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 438 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 439 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 440 #define AR_Q_MISC_RESV0 0xFFFFF000 441 442 #define AR_Q0_STS 0x0a00 443 #define AR_Q1_STS 0x0a04 444 #define AR_Q2_STS 0x0a08 445 #define AR_Q3_STS 0x0a0c 446 #define AR_Q4_STS 0x0a10 447 #define AR_Q5_STS 0x0a14 448 #define AR_Q6_STS 0x0a18 449 #define AR_Q7_STS 0x0a1c 450 #define AR_Q8_STS 0x0a20 451 #define AR_Q9_STS 0x0a24 452 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) 453 #define AR_Q_STS_PEND_FR_CNT 0x00000003 454 #define AR_Q_STS_RESV0 0x000000FC 455 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 456 #define AR_Q_STS_RESV1 0xFFFF0000 457 458 #define AR_Q_RDYTIMESHDN 0x0a40 459 #define AR_Q_RDYTIMESHDN_M 0x000003FF 460 461 462 #define AR_NUM_DCU 10 463 #define AR_DCU_0 0x0001 464 #define AR_DCU_1 0x0002 465 #define AR_DCU_2 0x0004 466 #define AR_DCU_3 0x0008 467 #define AR_DCU_4 0x0010 468 #define AR_DCU_5 0x0020 469 #define AR_DCU_6 0x0040 470 #define AR_DCU_7 0x0080 471 #define AR_DCU_8 0x0100 472 #define AR_DCU_9 0x0200 473 474 #define AR_D0_QCUMASK 0x1000 475 #define AR_D1_QCUMASK 0x1004 476 #define AR_D2_QCUMASK 0x1008 477 #define AR_D3_QCUMASK 0x100c 478 #define AR_D4_QCUMASK 0x1010 479 #define AR_D5_QCUMASK 0x1014 480 #define AR_D6_QCUMASK 0x1018 481 #define AR_D7_QCUMASK 0x101c 482 #define AR_D8_QCUMASK 0x1020 483 #define AR_D9_QCUMASK 0x1024 484 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) 485 #define AR_D_QCUMASK 0x000003FF 486 #define AR_D_QCUMASK_RESV0 0xFFFFFC00 487 488 #define AR_D_TXBLK_CMD 0x1038 489 #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) 490 491 #define AR_D0_LCL_IFS 0x1040 492 #define AR_D1_LCL_IFS 0x1044 493 #define AR_D2_LCL_IFS 0x1048 494 #define AR_D3_LCL_IFS 0x104c 495 #define AR_D4_LCL_IFS 0x1050 496 #define AR_D5_LCL_IFS 0x1054 497 #define AR_D6_LCL_IFS 0x1058 498 #define AR_D7_LCL_IFS 0x105c 499 #define AR_D8_LCL_IFS 0x1060 500 #define AR_D9_LCL_IFS 0x1064 501 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) 502 #define AR_D_LCL_IFS_CWMIN 0x000003FF 503 #define AR_D_LCL_IFS_CWMIN_S 0 504 #define AR_D_LCL_IFS_CWMAX 0x000FFC00 505 #define AR_D_LCL_IFS_CWMAX_S 10 506 #define AR_D_LCL_IFS_AIFS 0x0FF00000 507 #define AR_D_LCL_IFS_AIFS_S 20 508 509 #define AR_D_LCL_IFS_RESV0 0xF0000000 510 511 #define AR_D0_RETRY_LIMIT 0x1080 512 #define AR_D1_RETRY_LIMIT 0x1084 513 #define AR_D2_RETRY_LIMIT 0x1088 514 #define AR_D3_RETRY_LIMIT 0x108c 515 #define AR_D4_RETRY_LIMIT 0x1090 516 #define AR_D5_RETRY_LIMIT 0x1094 517 #define AR_D6_RETRY_LIMIT 0x1098 518 #define AR_D7_RETRY_LIMIT 0x109c 519 #define AR_D8_RETRY_LIMIT 0x10a0 520 #define AR_D9_RETRY_LIMIT 0x10a4 521 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) 522 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F 523 #define AR_D_RETRY_LIMIT_FR_SH_S 0 524 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 525 #define AR_D_RETRY_LIMIT_STA_SH_S 8 526 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 527 #define AR_D_RETRY_LIMIT_STA_LG_S 14 528 #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 529 530 #define AR_D0_CHNTIME 0x10c0 531 #define AR_D1_CHNTIME 0x10c4 532 #define AR_D2_CHNTIME 0x10c8 533 #define AR_D3_CHNTIME 0x10cc 534 #define AR_D4_CHNTIME 0x10d0 535 #define AR_D5_CHNTIME 0x10d4 536 #define AR_D6_CHNTIME 0x10d8 537 #define AR_D7_CHNTIME 0x10dc 538 #define AR_D8_CHNTIME 0x10e0 539 #define AR_D9_CHNTIME 0x10e4 540 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) 541 #define AR_D_CHNTIME_DUR 0x000FFFFF 542 #define AR_D_CHNTIME_DUR_S 0 543 #define AR_D_CHNTIME_EN 0x00100000 544 #define AR_D_CHNTIME_RESV0 0xFFE00000 545 546 #define AR_D0_MISC 0x1100 547 #define AR_D1_MISC 0x1104 548 #define AR_D2_MISC 0x1108 549 #define AR_D3_MISC 0x110c 550 #define AR_D4_MISC 0x1110 551 #define AR_D5_MISC 0x1114 552 #define AR_D6_MISC 0x1118 553 #define AR_D7_MISC 0x111c 554 #define AR_D8_MISC 0x1120 555 #define AR_D9_MISC 0x1124 556 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) 557 #define AR_D_MISC_BKOFF_THRESH 0x0000003F 558 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 559 #define AR_D_MISC_CW_RESET_EN 0x00000080 560 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 561 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 562 #define AR_D_MISC_CW_BKOFF_EN 0x00001000 563 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 564 #define AR_D_MISC_VIR_COL_HANDLING_S 14 565 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 566 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 567 #define AR_D_MISC_BEACON_USE 0x00010000 568 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 569 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 570 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 571 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 572 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 573 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 574 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 575 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 576 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 577 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 578 #define AR_D_MISC_RESV0 0xFF000000 579 580 #define AR_D_SEQNUM 0x1140 581 582 #define AR_D_GBL_IFS_SIFS 0x1030 583 #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF 584 #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF 585 586 #define AR_D_TXBLK_BASE 0x1038 587 #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF 588 #define AR_D_TXBLK_WRITE_BITMASK_S 0 589 #define AR_D_TXBLK_WRITE_SLICE 0x000F0000 590 #define AR_D_TXBLK_WRITE_SLICE_S 16 591 #define AR_D_TXBLK_WRITE_DCU 0x00F00000 592 #define AR_D_TXBLK_WRITE_DCU_S 20 593 #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 594 #define AR_D_TXBLK_WRITE_COMMAND_S 24 595 596 #define AR_D_GBL_IFS_SLOT 0x1070 597 #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF 598 #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 599 600 #define AR_D_GBL_IFS_EIFS 0x10b0 601 #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF 602 #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 603 604 #define AR_D_GBL_IFS_MISC 0x10f0 605 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 606 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 607 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 608 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 609 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 610 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 611 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 612 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 613 614 #define AR_D_FPCTL 0x1230 615 #define AR_D_FPCTL_DCU 0x0000000F 616 #define AR_D_FPCTL_DCU_S 0 617 #define AR_D_FPCTL_PREFETCH_EN 0x00000010 618 #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 619 #define AR_D_FPCTL_BURST_PREFETCH_S 5 620 621 #define AR_D_TXPSE 0x1270 622 #define AR_D_TXPSE_CTRL 0x000003FF 623 #define AR_D_TXPSE_RESV0 0x0000FC00 624 #define AR_D_TXPSE_STATUS 0x00010000 625 #define AR_D_TXPSE_RESV1 0xFFFE0000 626 627 #define AR_D_TXSLOTMASK 0x12f0 628 #define AR_D_TXSLOTMASK_NUM 0x0000000F 629 630 #define AR_CFG_LED 0x1f04 631 #define AR_CFG_SCLK_RATE_IND 0x00000003 632 #define AR_CFG_SCLK_RATE_IND_S 0 633 #define AR_CFG_SCLK_32MHZ 0x00000000 634 #define AR_CFG_SCLK_4MHZ 0x00000001 635 #define AR_CFG_SCLK_1MHZ 0x00000002 636 #define AR_CFG_SCLK_32KHZ 0x00000003 637 #define AR_CFG_LED_BLINK_SLOW 0x00000008 638 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 639 #define AR_CFG_LED_MODE_SEL 0x00000380 640 #define AR_CFG_LED_MODE_SEL_S 7 641 #define AR_CFG_LED_POWER 0x00000280 642 #define AR_CFG_LED_POWER_S 7 643 #define AR_CFG_LED_NETWORK 0x00000300 644 #define AR_CFG_LED_NETWORK_S 7 645 #define AR_CFG_LED_MODE_PROP 0x0 646 #define AR_CFG_LED_MODE_RPROP 0x1 647 #define AR_CFG_LED_MODE_SPLIT 0x2 648 #define AR_CFG_LED_MODE_RAND 0x3 649 #define AR_CFG_LED_MODE_POWER_OFF 0x4 650 #define AR_CFG_LED_MODE_POWER_ON 0x5 651 #define AR_CFG_LED_MODE_NETWORK_OFF 0x4 652 #define AR_CFG_LED_MODE_NETWORK_ON 0x6 653 #define AR_CFG_LED_ASSOC_CTL 0x00000c00 654 #define AR_CFG_LED_ASSOC_CTL_S 10 655 #define AR_CFG_LED_ASSOC_NONE 0x0 656 #define AR_CFG_LED_ASSOC_ACTIVE 0x1 657 #define AR_CFG_LED_ASSOC_PENDING 0x2 658 659 #define AR_CFG_LED_BLINK_SLOW 0x00000008 660 #define AR_CFG_LED_BLINK_SLOW_S 3 661 662 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 663 #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 664 665 #define AR_MAC_SLEEP 0x1f00 666 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 667 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 668 669 #define AR_RC 0x4000 670 #define AR_RC_AHB 0x00000001 671 #define AR_RC_APB 0x00000002 672 #define AR_RC_HOSTIF 0x00000100 673 674 #define AR_WA 0x4004 675 #define AR9285_WA_DEFAULT 0x004a05cb 676 #define AR9280_WA_DEFAULT 0x0040073f 677 #define AR_WA_DEFAULT 0x0000073f 678 679 680 #define AR_PM_STATE 0x4008 681 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 682 683 #define AR_HOST_TIMEOUT 0x4018 684 #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF 685 #define AR_HOST_TIMEOUT_APB_CNTR_S 0 686 #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 687 #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 688 689 #define AR_EEPROM 0x401c 690 #define AR_EEPROM_ABSENT 0x00000100 691 #define AR_EEPROM_CORRUPT 0x00000200 692 #define AR_EEPROM_PROT_MASK 0x03FFFC00 693 #define AR_EEPROM_PROT_MASK_S 10 694 695 #define EEPROM_PROTECT_RP_0_31 0x0001 696 #define EEPROM_PROTECT_WP_0_31 0x0002 697 #define EEPROM_PROTECT_RP_32_63 0x0004 698 #define EEPROM_PROTECT_WP_32_63 0x0008 699 #define EEPROM_PROTECT_RP_64_127 0x0010 700 #define EEPROM_PROTECT_WP_64_127 0x0020 701 #define EEPROM_PROTECT_RP_128_191 0x0040 702 #define EEPROM_PROTECT_WP_128_191 0x0080 703 #define EEPROM_PROTECT_RP_192_255 0x0100 704 #define EEPROM_PROTECT_WP_192_255 0x0200 705 #define EEPROM_PROTECT_RP_256_511 0x0400 706 #define EEPROM_PROTECT_WP_256_511 0x0800 707 #define EEPROM_PROTECT_RP_512_1023 0x1000 708 #define EEPROM_PROTECT_WP_512_1023 0x2000 709 #define EEPROM_PROTECT_RP_1024_2047 0x4000 710 #define EEPROM_PROTECT_WP_1024_2047 0x8000 711 712 #define AR_SREV \ 713 ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020) 714 715 #define AR_SREV_ID \ 716 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF) 717 #define AR_SREV_VERSION 0x000000F0 718 #define AR_SREV_VERSION_S 4 719 #define AR_SREV_REVISION 0x00000007 720 721 #define AR_SREV_ID2 0xFFFFFFFF 722 #define AR_SREV_VERSION2 0xFFFC0000 723 #define AR_SREV_VERSION2_S 18 724 #define AR_SREV_TYPE2 0x0003F000 725 #define AR_SREV_TYPE2_S 12 726 #define AR_SREV_TYPE2_CHAIN 0x00001000 727 #define AR_SREV_TYPE2_HOST_MODE 0x00002000 728 #define AR_SREV_REVISION2 0x00000F00 729 #define AR_SREV_REVISION2_S 8 730 731 #define AR_SREV_VERSION_5416_PCI 0xD 732 #define AR_SREV_VERSION_5416_PCIE 0xC 733 #define AR_SREV_REVISION_5416_10 0 734 #define AR_SREV_REVISION_5416_20 1 735 #define AR_SREV_REVISION_5416_22 2 736 #define AR_SREV_VERSION_9160 0x40 737 #define AR_SREV_REVISION_9160_10 0 738 #define AR_SREV_REVISION_9160_11 1 739 #define AR_SREV_VERSION_9280 0x80 740 #define AR_SREV_REVISION_9280_10 0 741 #define AR_SREV_REVISION_9280_20 1 742 #define AR_SREV_REVISION_9280_21 2 743 #define AR_SREV_VERSION_9285 0xC0 744 #define AR_SREV_REVISION_9285_10 0 745 #define AR_SREV_REVISION_9285_11 1 746 #define AR_SREV_REVISION_9285_12 2 747 748 #define AR_SREV_9100_OR_LATER(_ah) \ 749 (((_ah)->ah_macVersion >= AR_SREV_VERSION_5416_PCIE)) 750 #define AR_SREV_5416_20_OR_LATER(_ah) \ 751 (((_ah)->ah_macVersion >= AR_SREV_VERSION_9160) || \ 752 ((_ah)->ah_macRev >= AR_SREV_REVISION_5416_20)) 753 #define AR_SREV_5416_22_OR_LATER(_ah) \ 754 (((_ah)->ah_macVersion >= AR_SREV_VERSION_9160) || \ 755 ((_ah)->ah_macRev >= AR_SREV_REVISION_5416_22)) 756 #define AR_SREV_9160(_ah) \ 757 (((_ah)->ah_macVersion == AR_SREV_VERSION_9160)) 758 #define AR_SREV_9160_10_OR_LATER(_ah) \ 759 (((_ah)->ah_macVersion >= AR_SREV_VERSION_9160)) 760 #define AR_SREV_9160_11(_ah) \ 761 (AR_SREV_9160(_ah) && ((_ah)->ah_macRev == AR_SREV_REVISION_9160_11)) 762 #define AR_SREV_9280(_ah) \ 763 (((_ah)->ah_macVersion == AR_SREV_VERSION_9280)) 764 #define AR_SREV_9280_10_OR_LATER(_ah) \ 765 (((_ah)->ah_macVersion >= AR_SREV_VERSION_9280)) 766 #define AR_SREV_9280_20(_ah) \ 767 (((_ah)->ah_macVersion == AR_SREV_VERSION_9280) && \ 768 ((_ah)->ah_macRev >= AR_SREV_REVISION_9280_20)) 769 #define AR_SREV_9280_20_OR_LATER(_ah) \ 770 (((_ah)->ah_macVersion > AR_SREV_VERSION_9280) || \ 771 (((_ah)->ah_macVersion == AR_SREV_VERSION_9280) && \ 772 ((_ah)->ah_macRev >= AR_SREV_REVISION_9280_20))) 773 774 #define AR_SREV_9285(_ah) (((_ah)->ah_macVersion == AR_SREV_VERSION_9285)) 775 #define AR_SREV_9285_10_OR_LATER(_ah) \ 776 (((_ah)->ah_macVersion >= AR_SREV_VERSION_9285)) 777 #define AR_SREV_9285_11(_ah) \ 778 (AR_SREV_9280(ah) && ((_ah)->ah_macRev == AR_SREV_REVISION_9285_11)) 779 #define AR_SREV_9285_11_OR_LATER(_ah) \ 780 (((_ah)->ah_macVersion > AR_SREV_VERSION_9285) || \ 781 (AR_SREV_9285(ah) && ((_ah)->ah_macRev >= AR_SREV_REVISION_9285_11))) 782 #define AR_SREV_9285_12(_ah) \ 783 (AR_SREV_9280(ah) && ((_ah)->ah_macRev == AR_SREV_REVISION_9285_12)) 784 #define AR_SREV_9285_12_OR_LATER(_ah) \ 785 (((_ah)->ah_macVersion > AR_SREV_VERSION_9285) || \ 786 (AR_SREV_9285(ah) && ((_ah)->ah_macRev >= AR_SREV_REVISION_9285_12))) 787 788 #define AR_RADIO_SREV_MAJOR 0xf0 789 #define AR_RAD5133_SREV_MAJOR 0xc0 790 #define AR_RAD2133_SREV_MAJOR 0xd0 791 #define AR_RAD5122_SREV_MAJOR 0xe0 792 #define AR_RAD2122_SREV_MAJOR 0xf0 793 794 #define AR_AHB_MODE 0x4024 795 #define AR_AHB_EXACT_WR_EN 0x00000000 796 #define AR_AHB_BUF_WR_EN 0x00000001 797 #define AR_AHB_EXACT_RD_EN 0x00000000 798 #define AR_AHB_CACHELINE_RD_EN 0x00000002 799 #define AR_AHB_PREFETCH_RD_EN 0x00000004 800 #define AR_AHB_PAGE_SIZE_1K 0x00000000 801 #define AR_AHB_PAGE_SIZE_2K 0x00000008 802 #define AR_AHB_PAGE_SIZE_4K 0x00000010 803 804 #define AR_INTR_RTC_IRQ 0x00000001 805 #define AR_INTR_MAC_IRQ 0x00000002 806 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 807 #define AR_INTR_MAC_AWAKE 0x00020000 808 #define AR_INTR_MAC_ASLEEP 0x00040000 809 #define AR_INTR_SPURIOUS 0xFFFFFFFF 810 811 812 #define AR_INTR_SYNC_CAUSE_CLR 0x4028 813 814 #define AR_INTR_SYNC_CAUSE 0x4028 815 816 #define AR_INTR_SYNC_ENABLE 0x402c 817 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 818 #define AR_INTR_SYNC_ENABLE_GPIO_S 18 819 820 enum { 821 AR_INTR_SYNC_RTC_IRQ = 0x00000001, 822 AR_INTR_SYNC_MAC_IRQ = 0x00000002, 823 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, 824 AR_INTR_SYNC_APB_TIMEOUT = 0x00000008, 825 AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, 826 AR_INTR_SYNC_HOST1_FATAL = 0x00000020, 827 AR_INTR_SYNC_HOST1_PERR = 0x00000040, 828 AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, 829 AR_INTR_SYNC_RADM_CPL_EP = 0x00000100, 830 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, 831 AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, 832 AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, 833 AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, 834 AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, 835 AR_INTR_SYNC_PM_ACCESS = 0x00004000, 836 AR_INTR_SYNC_MAC_AWAKE = 0x00008000, 837 AR_INTR_SYNC_MAC_ASLEEP = 0x00010000, 838 AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, 839 AR_INTR_SYNC_ALL = 0x0003FFFF, 840 841 842 AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL | 843 AR_INTR_SYNC_HOST1_PERR | 844 AR_INTR_SYNC_RADM_CPL_EP | 845 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | 846 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | 847 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | 848 AR_INTR_SYNC_RADM_CPL_TIMEOUT | 849 AR_INTR_SYNC_LOCAL_TIMEOUT | 850 AR_INTR_SYNC_MAC_SLEEP_ACCESS), 851 852 AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, 853 854 }; 855 856 #define AR_INTR_ASYNC_MASK 0x4030 857 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 858 #define AR_INTR_ASYNC_MASK_GPIO_S 18 859 860 #define AR_INTR_SYNC_MASK 0x4034 861 #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 862 #define AR_INTR_SYNC_MASK_GPIO_S 18 863 864 #define AR_INTR_ASYNC_CAUSE_CLR 0x4038 865 #define AR_INTR_ASYNC_CAUSE 0x4038 866 867 #define AR_INTR_ASYNC_ENABLE 0x403c 868 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 869 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 870 871 #define AR_PCIE_SERDES 0x4040 872 #define AR_PCIE_SERDES2 0x4044 873 #define AR_PCIE_PM_CTRL 0x4014 874 #define AR_PCIE_PM_CTRL_ENA 0x00080000 875 876 #define AR_NUM_GPIO 14 877 #define AR928X_NUM_GPIO 10 878 879 #define AR_GPIO_IN_OUT 0x4048 880 #define AR_GPIO_IN_VAL 0x0FFFC000 881 #define AR_GPIO_IN_VAL_S 14 882 #define AR928X_GPIO_IN_VAL 0x000FFC00 883 #define AR928X_GPIO_IN_VAL_S 10 884 885 #define AR_GPIO_OE_OUT 0x404c 886 #define AR_GPIO_OE_OUT_DRV 0x3 887 #define AR_GPIO_OE_OUT_DRV_NO 0x0 888 #define AR_GPIO_OE_OUT_DRV_LOW 0x1 889 #define AR_GPIO_OE_OUT_DRV_HI 0x2 890 #define AR_GPIO_OE_OUT_DRV_ALL 0x3 891 892 #define AR_GPIO_INTR_POL 0x4050 893 #define AR_GPIO_INTR_POL_VAL 0x00001FFF 894 #define AR_GPIO_INTR_POL_VAL_S 0 895 896 #define AR_GPIO_INPUT_EN_VAL 0x4054 897 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 898 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 899 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 900 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 901 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 902 #define AR_GPIO_JTAG_DISABLE 0x00020000 903 904 #define AR_GPIO_INPUT_MUX1 0x4058 905 906 #define AR_GPIO_INPUT_MUX2 0x405c 907 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 908 #define AR_GPIO_INPUT_MUX2_CLK25_S 0 909 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 910 #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 911 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 912 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 913 914 #define AR_GPIO_OUTPUT_MUX1 0x4060 915 #define AR_GPIO_OUTPUT_MUX2 0x4064 916 #define AR_GPIO_OUTPUT_MUX3 0x4068 917 918 #define AR_INPUT_STATE 0x406c 919 920 #define AR_EEPROM_STATUS_DATA 0x407c 921 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 922 #define AR_EEPROM_STATUS_DATA_VAL_S 0 923 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 924 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 925 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 926 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 927 928 #define AR_OBS 0x4080 929 930 #define AR_PCIE_MSI 0x4094 931 #define AR_PCIE_MSI_ENABLE 0x00000001 932 933 934 #define AR_RTC_9160_PLL_DIV 0x000003ff 935 #define AR_RTC_9160_PLL_DIV_S 0 936 #define AR_RTC_9160_PLL_REFDIV 0x00003C00 937 #define AR_RTC_9160_PLL_REFDIV_S 10 938 #define AR_RTC_9160_PLL_CLKSEL 0x0000C000 939 #define AR_RTC_9160_PLL_CLKSEL_S 14 940 941 #define AR_RTC_BASE 0x00020000 942 #define AR_RTC_RC \ 943 (AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000 944 #define AR_RTC_RC_M 0x00000003 945 #define AR_RTC_RC_MAC_WARM 0x00000001 946 #define AR_RTC_RC_MAC_COLD 0x00000002 947 #define AR_RTC_RC_COLD_RESET 0x00000004 948 #define AR_RTC_RC_WARM_RESET 0x00000008 949 950 #define AR_RTC_PLL_CONTROL \ 951 (AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014 952 953 #define AR_RTC_PLL_DIV 0x0000001f 954 #define AR_RTC_PLL_DIV_S 0 955 #define AR_RTC_PLL_DIV2 0x00000020 956 #define AR_RTC_PLL_REFDIV_5 0x000000c0 957 #define AR_RTC_PLL_CLKSEL 0x00000300 958 #define AR_RTC_PLL_CLKSEL_S 8 959 960 961 962 #define AR_RTC_RESET \ 963 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) 964 #define AR_RTC_RESET_EN (0x00000001) 965 966 #define AR_RTC_STATUS \ 967 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044) 968 969 #define AR_RTC_STATUS_M \ 970 ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f) 971 972 #define AR_RTC_PM_STATUS_M 0x0000000f 973 974 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 975 #define AR_RTC_STATUS_ON 0x00000002 976 #define AR_RTC_STATUS_SLEEP 0x00000004 977 #define AR_RTC_STATUS_WAKEUP 0x00000008 978 979 #define AR_RTC_SLEEP_CLK \ 980 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048) 981 #define AR_RTC_FORCE_DERIVED_CLK 0x2 982 983 #define AR_RTC_FORCE_WAKE \ 984 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c) 985 #define AR_RTC_FORCE_WAKE_EN 0x00000001 986 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 987 988 989 #define AR_RTC_INTR_CAUSE \ 990 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050) 991 992 #define AR_RTC_INTR_ENABLE \ 993 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054) 994 995 #define AR_RTC_INTR_MASK \ 996 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058) 997 998 #define AR_SEQ_MASK 0x8060 999 1000 #define AR_AN_RF2G1_CH0 0x7810 1001 #define AR_AN_RF2G1_CH0_OB 0x03800000 1002 #define AR_AN_RF2G1_CH0_OB_S 23 1003 #define AR_AN_RF2G1_CH0_DB 0x1C000000 1004 #define AR_AN_RF2G1_CH0_DB_S 26 1005 1006 #define AR_AN_RF5G1_CH0 0x7818 1007 #define AR_AN_RF5G1_CH0_OB5 0x00070000 1008 #define AR_AN_RF5G1_CH0_OB5_S 16 1009 #define AR_AN_RF5G1_CH0_DB5 0x00380000 1010 #define AR_AN_RF5G1_CH0_DB5_S 19 1011 1012 #define AR_AN_RF2G1_CH1 0x7834 1013 #define AR_AN_RF2G1_CH1_OB 0x03800000 1014 #define AR_AN_RF2G1_CH1_OB_S 23 1015 #define AR_AN_RF2G1_CH1_DB 0x1C000000 1016 #define AR_AN_RF2G1_CH1_DB_S 26 1017 1018 #define AR_AN_RF5G1_CH1 0x783C 1019 #define AR_AN_RF5G1_CH1_OB5 0x00070000 1020 #define AR_AN_RF5G1_CH1_OB5_S 16 1021 #define AR_AN_RF5G1_CH1_DB5 0x00380000 1022 #define AR_AN_RF5G1_CH1_DB5_S 19 1023 1024 #define AR_AN_TOP2 0x7894 1025 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 1026 #define AR_AN_TOP2_XPABIAS_LVL_S 30 1027 #define AR_AN_TOP2_LOCALBIAS 0x00200000 1028 #define AR_AN_TOP2_LOCALBIAS_S 21 1029 #define AR_AN_TOP2_PWDCLKIND 0x00400000 1030 #define AR_AN_TOP2_PWDCLKIND_S 22 1031 1032 #define AR_AN_SYNTH9 0x7868 1033 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 1034 #define AR_AN_SYNTH9_REFDIVA_S 27 1035 1036 #define AR9285_AN_RF2G1 0x7820 1037 #define AR9285_AN_RF2G1_ENPACAL 0x00000800 1038 #define AR9285_AN_RF2G1_ENPACAL_S 11 1039 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000 1040 #define AR9285_AN_RF2G1_PDPADRV1_S 25 1041 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000 1042 #define AR9285_AN_RF2G1_PDPADRV2_S 24 1043 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000 1044 #define AR9285_AN_RF2G1_PDPAOUT_S 23 1045 1046 1047 #define AR9285_AN_RF2G2 0x7824 1048 #define AR9285_AN_RF2G2_OFFCAL 0x00001000 1049 #define AR9285_AN_RF2G2_OFFCAL_S 12 1050 1051 #define AR9285_AN_RF2G3 0x7828 1052 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 1053 #define AR9285_AN_RF2G3_PDVCCOMP_S 25 1054 #define AR9285_AN_RF2G3_OB_0 0x00E00000 1055 #define AR9285_AN_RF2G3_OB_0_S 21 1056 #define AR9285_AN_RF2G3_OB_1 0x001C0000 1057 #define AR9285_AN_RF2G3_OB_1_S 18 1058 #define AR9285_AN_RF2G3_OB_2 0x00038000 1059 #define AR9285_AN_RF2G3_OB_2_S 15 1060 #define AR9285_AN_RF2G3_OB_3 0x00007000 1061 #define AR9285_AN_RF2G3_OB_3_S 12 1062 #define AR9285_AN_RF2G3_OB_4 0x00000E00 1063 #define AR9285_AN_RF2G3_OB_4_S 9 1064 1065 #define AR9285_AN_RF2G3_DB1_0 0x000001C0 1066 #define AR9285_AN_RF2G3_DB1_0_S 6 1067 #define AR9285_AN_RF2G3_DB1_1 0x00000038 1068 #define AR9285_AN_RF2G3_DB1_1_S 3 1069 #define AR9285_AN_RF2G3_DB1_2 0x00000007 1070 #define AR9285_AN_RF2G3_DB1_2_S 0 1071 #define AR9285_AN_RF2G4 0x782C 1072 #define AR9285_AN_RF2G4_DB1_3 0xE0000000 1073 #define AR9285_AN_RF2G4_DB1_3_S 29 1074 #define AR9285_AN_RF2G4_DB1_4 0x1C000000 1075 #define AR9285_AN_RF2G4_DB1_4_S 26 1076 1077 #define AR9285_AN_RF2G4_DB2_0 0x03800000 1078 #define AR9285_AN_RF2G4_DB2_0_S 23 1079 #define AR9285_AN_RF2G4_DB2_1 0x00700000 1080 #define AR9285_AN_RF2G4_DB2_1_S 20 1081 #define AR9285_AN_RF2G4_DB2_2 0x000E0000 1082 #define AR9285_AN_RF2G4_DB2_2_S 17 1083 #define AR9285_AN_RF2G4_DB2_3 0x0001C000 1084 #define AR9285_AN_RF2G4_DB2_3_S 14 1085 #define AR9285_AN_RF2G4_DB2_4 0x00003800 1086 #define AR9285_AN_RF2G4_DB2_4_S 11 1087 1088 #define AR9285_AN_RF2G6 0x7834 1089 #define AR9285_AN_RF2G6_CCOMP 0x00007800 1090 #define AR9285_AN_RF2G6_CCOMP_S 11 1091 #define AR9285_AN_RF2G6_OFFS 0x03f00000 1092 #define AR9285_AN_RF2G6_OFFS_S 20 1093 1094 #define AR9285_AN_RF2G7 0x7838 1095 #define AR9285_AN_RF2G7_PWDDB 0x00000002 1096 #define AR9285_AN_RF2G7_PWDDB_S 1 1097 #define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 1098 #define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 1099 1100 #define AR9285_AN_RF2G8 0x783C 1101 #define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 1102 #define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 1103 1104 1105 #define AR9285_AN_RF2G9 0x7840 1106 #define AR9285_AN_RXTXBB1 0x7854 1107 #define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 1108 #define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 1109 #define AR9285_AN_RXTXBB1_PDV2I 0x00000080 1110 #define AR9285_AN_RXTXBB1_PDV2I_S 7 1111 #define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 1112 #define AR9285_AN_RXTXBB1_PDDACIF_S 8 1113 #define AR9285_AN_RXTXBB1_SPARE9 0x00000001 1114 #define AR9285_AN_RXTXBB1_SPARE9_S 0 1115 1116 #define AR9285_AN_TOP2 0x7868 1117 1118 #define AR9285_AN_TOP3 0x786c 1119 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 1120 #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 1121 #define AR9285_AN_TOP3_PWDDAC 0x00800000 1122 #define AR9285_AN_TOP3_PWDDAC_S 23 1123 1124 #define AR9285_AN_TOP4 0x7870 1125 #define AR9285_AN_TOP4_DEFAULT 0x10142c00 1126 1127 #define AR_STA_ID0 0x8000 1128 #define AR_STA_ID1 0x8004 1129 #define AR_STA_ID1_SADH_MASK 0x0000FFFF 1130 #define AR_STA_ID1_STA_AP 0x00010000 1131 #define AR_STA_ID1_ADHOC 0x00020000 1132 #define AR_STA_ID1_PWR_SAV 0x00040000 1133 #define AR_STA_ID1_KSRCHDIS 0x00080000 1134 #define AR_STA_ID1_PCF 0x00100000 1135 #define AR_STA_ID1_USE_DEFANT 0x00200000 1136 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 1137 #define AR_STA_ID1_RTS_USE_DEF 0x00800000 1138 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 1139 #define AR_STA_ID1_BASE_RATE_11B 0x02000000 1140 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 1141 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 1142 #define AR_STA_ID1_KSRCH_MODE 0x10000000 1143 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 1144 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 1145 #define AR_STA_ID1_MCAST_KSRCH 0x80000000 1146 1147 #define AR_BSS_ID0 0x8008 1148 #define AR_BSS_ID1 0x800C 1149 #define AR_BSS_ID1_U16 0x0000FFFF 1150 #define AR_BSS_ID1_AID 0x07FF0000 1151 #define AR_BSS_ID1_AID_S 16 1152 1153 #define AR_BCN_RSSI_AVE 0x8010 1154 #define AR_BCN_RSSI_AVE_MASK 0x00000FFF 1155 1156 #define AR_TIME_OUT 0x8014 1157 #define AR_TIME_OUT_ACK 0x00003FFF 1158 #define AR_TIME_OUT_ACK_S 0 1159 #define AR_TIME_OUT_CTS 0x3FFF0000 1160 #define AR_TIME_OUT_CTS_S 16 1161 1162 #define AR_RSSI_THR 0x8018 1163 #define AR_RSSI_THR_MASK 0x000000FF 1164 #define AR_RSSI_THR_BM_THR 0x0000FF00 1165 #define AR_RSSI_THR_BM_THR_S 8 1166 #define AR_RSSI_BCN_WEIGHT 0x1F000000 1167 #define AR_RSSI_BCN_WEIGHT_S 24 1168 #define AR_RSSI_BCN_RSSI_RST 0x20000000 1169 1170 #define AR_USEC 0x801c 1171 #define AR_USEC_USEC 0x0000007F 1172 #define AR_USEC_TX_LAT 0x007FC000 1173 #define AR_USEC_TX_LAT_S 14 1174 #define AR_USEC_RX_LAT 0x1F800000 1175 #define AR_USEC_RX_LAT_S 23 1176 1177 #define AR_RESET_TSF 0x8020 1178 #define AR_RESET_TSF_ONCE 0x01000000 1179 1180 #define AR_MAX_CFP_DUR 0x8038 1181 #define AR_CFP_VAL 0x0000FFFF 1182 1183 #define AR_RX_FILTER 0x803C 1184 #define AR_RX_FILTER_ALL 0x00000000 1185 #define AR_RX_UCAST 0x00000001 1186 #define AR_RX_MCAST 0x00000002 1187 #define AR_RX_BCAST 0x00000004 1188 #define AR_RX_CONTROL 0x00000008 1189 #define AR_RX_BEACON 0x00000010 1190 #define AR_RX_PROM 0x00000020 1191 #define AR_RX_PROBE_REQ 0x00000080 1192 #define AR_RX_MY_BEACON 0x00000200 1193 #define AR_RX_COMPR_BAR 0x00000400 1194 #define AR_RX_COMPR_BA 0x00000800 1195 #define AR_RX_UNCOM_BA_BAR 0x00001000 1196 1197 #define AR_MCAST_FIL0 0x8040 1198 #define AR_MCAST_FIL1 0x8044 1199 1200 #define AR_DIAG_SW 0x8048 1201 #define AR_DIAG_CACHE_ACK 0x00000001 1202 #define AR_DIAG_ACK_DIS 0x00000002 1203 #define AR_DIAG_CTS_DIS 0x00000004 1204 #define AR_DIAG_ENCRYPT_DIS 0x00000008 1205 #define AR_DIAG_DECRYPT_DIS 0x00000010 1206 #define AR_DIAG_RX_DIS 0x00000020 1207 #define AR_DIAG_LOOP_BACK 0x00000040 1208 #define AR_DIAG_CORR_FCS 0x00000080 1209 #define AR_DIAG_CHAN_INFO 0x00000100 1210 #define AR_DIAG_SCRAM_SEED 0x0001FE00 1211 #define AR_DIAG_SCRAM_SEED_S 8 1212 #define AR_DIAG_FRAME_NV0 0x00020000 1213 #define AR_DIAG_OBS_PT_SEL1 0x000C0000 1214 #define AR_DIAG_OBS_PT_SEL1_S 18 1215 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 1216 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1217 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1218 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1219 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1220 #define AR_DIAG_RX_ABORT 0x02000000 1221 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1222 #define AR_DIAG_OBS_PT_SEL2 0x08000000 1223 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1224 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1225 1226 #define AR_TSF_L32 0x804c 1227 #define AR_TSF_U32 0x8050 1228 1229 #define AR_TST_ADDAC 0x8054 1230 #define AR_DEF_ANTENNA 0x8058 1231 1232 #define AR_AES_MUTE_MASK0 0x805c 1233 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1234 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 1235 #define AR_AES_MUTE_MASK0_QOS_S 16 1236 1237 #define AR_AES_MUTE_MASK1 0x8060 1238 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF 1239 1240 #define AR_GATED_CLKS 0x8064 1241 #define AR_GATED_CLKS_TX 0x00000002 1242 #define AR_GATED_CLKS_RX 0x00000004 1243 #define AR_GATED_CLKS_REG 0x00000008 1244 1245 #define AR_OBS_BUS_CTRL 0x8068 1246 #define AR_OBS_BUS_SEL_1 0x00040000 1247 #define AR_OBS_BUS_SEL_2 0x00080000 1248 #define AR_OBS_BUS_SEL_3 0x000C0000 1249 #define AR_OBS_BUS_SEL_4 0x08040000 1250 #define AR_OBS_BUS_SEL_5 0x08080000 1251 1252 #define AR_OBS_BUS_1 0x806c 1253 #define AR_OBS_BUS_1_PCU 0x00000001 1254 #define AR_OBS_BUS_1_RX_END 0x00000002 1255 #define AR_OBS_BUS_1_RX_WEP 0x00000004 1256 #define AR_OBS_BUS_1_RX_BEACON 0x00000008 1257 #define AR_OBS_BUS_1_RX_FILTER 0x00000010 1258 #define AR_OBS_BUS_1_TX_HCF 0x00000020 1259 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1260 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1261 #define AR_OBS_BUS_1_TX_HOLD 0x00000100 1262 #define AR_OBS_BUS_1_TX_FRAME 0x00000200 1263 #define AR_OBS_BUS_1_RX_FRAME 0x00000400 1264 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1265 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000 1266 #define AR_OBS_BUS_1_WEP_STATE_S 12 1267 #define AR_OBS_BUS_1_RX_STATE 0x01F00000 1268 #define AR_OBS_BUS_1_RX_STATE_S 20 1269 #define AR_OBS_BUS_1_TX_STATE 0x7E000000 1270 #define AR_OBS_BUS_1_TX_STATE_S 25 1271 1272 #define AR_LAST_TSTP 0x8080 1273 #define AR_NAV 0x8084 1274 #define AR_RTS_OK 0x8088 1275 #define AR_RTS_FAIL 0x808c 1276 #define AR_ACK_FAIL 0x8090 1277 #define AR_FCS_FAIL 0x8094 1278 #define AR_BEACON_CNT 0x8098 1279 1280 #define AR_SLEEP1 0x80d4 1281 #define AR_SLEEP1_ASSUME_DTIM 0x00080000 1282 #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 1283 #define AR_SLEEP1_CAB_TIMEOUT_S 21 1284 1285 #define AR_SLEEP2 0x80d8 1286 #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 1287 #define AR_SLEEP2_BEACON_TIMEOUT_S 21 1288 1289 #define AR_BSSMSKL 0x80e0 1290 #define AR_BSSMSKU 0x80e4 1291 1292 #define AR_TPC 0x80e8 1293 #define AR_TPC_ACK 0x0000003f 1294 #define AR_TPC_ACK_S 0x00 1295 #define AR_TPC_CTS 0x00003f00 1296 #define AR_TPC_CTS_S 0x08 1297 #define AR_TPC_CHIRP 0x003f0000 1298 #define AR_TPC_CHIRP_S 0x16 1299 1300 #define AR_TFCNT 0x80ec 1301 #define AR_RFCNT 0x80f0 1302 #define AR_RCCNT 0x80f4 1303 #define AR_CCCNT 0x80f8 1304 1305 #define AR_QUIET1 0x80fc 1306 #define AR_QUIET1_NEXT_QUIET_S 0 1307 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1308 #define AR_QUIET1_QUIET_ENABLE 0x00010000 1309 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1310 #define AR_QUIET2 0x8100 1311 #define AR_QUIET2_QUIET_PERIOD_S 0 1312 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1313 #define AR_QUIET2_QUIET_DUR_S 16 1314 #define AR_QUIET2_QUIET_DUR 0xffff0000 1315 1316 #define AR_TSF_PARM 0x8104 1317 #define AR_TSF_INCREMENT_M 0x000000ff 1318 #define AR_TSF_INCREMENT_S 0x00 1319 1320 #define AR_QOS_NO_ACK 0x8108 1321 #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f 1322 #define AR_QOS_NO_ACK_TWO_BIT_S 0 1323 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 1324 #define AR_QOS_NO_ACK_BIT_OFF_S 4 1325 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 1326 #define AR_QOS_NO_ACK_BYTE_OFF_S 7 1327 1328 #define AR_PHY_ERR 0x810c 1329 1330 #define AR_PHY_ERR_DCHIRP 0x00000008 1331 #define AR_PHY_ERR_RADAR 0x00000020 1332 #define AR_PHY_ERR_OFDM_TIMING 0x00020000 1333 #define AR_PHY_ERR_CCK_TIMING 0x02000000 1334 1335 #define AR_RXFIFO_CFG 0x8114 1336 1337 1338 #define AR_MIC_QOS_CONTROL 0x8118 1339 #define AR_MIC_QOS_SELECT 0x811c 1340 1341 #define AR_PCU_MISC 0x8120 1342 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1343 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1344 #define AR_PCU_TX_ADD_TSF 0x00000008 1345 #define AR_PCU_CCK_SIFS_MODE 0x00000010 1346 #define AR_PCU_RX_ANT_UPDT 0x00000800 1347 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1348 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1349 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1350 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 1351 #define AR_PCU_TBTT_PROTECT 0x00200000 1352 #define AR_PCU_CLEAR_VMF 0x01000000 1353 #define AR_PCU_CLEAR_BA_VALID 0x04000000 1354 1355 1356 #define AR_FILT_OFDM 0x8124 1357 #define AR_FILT_OFDM_COUNT 0x00FFFFFF 1358 1359 #define AR_FILT_CCK 0x8128 1360 #define AR_FILT_CCK_COUNT 0x00FFFFFF 1361 1362 #define AR_PHY_ERR_1 0x812c 1363 #define AR_PHY_ERR_1_COUNT 0x00FFFFFF 1364 #define AR_PHY_ERR_MASK_1 0x8130 1365 1366 #define AR_PHY_ERR_2 0x8134 1367 #define AR_PHY_ERR_2_COUNT 0x00FFFFFF 1368 #define AR_PHY_ERR_MASK_2 0x8138 1369 1370 #define AR_PHY_COUNTMAX (3 << 22) 1371 #define AR_MIBCNT_INTRMASK (3 << 22) 1372 1373 #define AR_TSF_THRESHOLD 0x813c 1374 #define AR_TSF_THRESHOLD_VAL 0x0000FFFF 1375 1376 #define AR_PHY_ERR_EIFS_MASK 8144 1377 1378 #define AR_PHY_ERR_3 0x8168 1379 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF 1380 #define AR_PHY_ERR_MASK_3 0x816c 1381 1382 #define AR_TXSIFS 0x81d0 1383 #define AR_TXSIFS_TIME 0x000000FF 1384 #define AR_TXSIFS_TX_LATENCY 0x00000F00 1385 #define AR_TXSIFS_TX_LATENCY_S 8 1386 #define AR_TXSIFS_ACK_SHIFT 0x00007000 1387 #define AR_TXSIFS_ACK_SHIFT_S 12 1388 1389 #define AR_TXOP_X 0x81ec 1390 #define AR_TXOP_X_VAL 0x000000FF 1391 1392 1393 #define AR_TXOP_0_3 0x81f0 1394 #define AR_TXOP_4_7 0x81f4 1395 #define AR_TXOP_8_11 0x81f8 1396 #define AR_TXOP_12_15 0x81fc 1397 1398 1399 #define AR_NEXT_TBTT_TIMER 0x8200 1400 #define AR_NEXT_DMA_BEACON_ALERT 0x8204 1401 #define AR_NEXT_SWBA 0x8208 1402 #define AR_NEXT_CFP 0x8208 1403 #define AR_NEXT_HCF 0x820C 1404 #define AR_NEXT_TIM 0x8210 1405 #define AR_NEXT_DTIM 0x8214 1406 #define AR_NEXT_QUIET_TIMER 0x8218 1407 #define AR_NEXT_NDP_TIMER 0x821C 1408 1409 #define AR_BEACON_PERIOD 0x8220 1410 #define AR_DMA_BEACON_PERIOD 0x8224 1411 #define AR_SWBA_PERIOD 0x8228 1412 #define AR_HCF_PERIOD 0x822C 1413 #define AR_TIM_PERIOD 0x8230 1414 #define AR_DTIM_PERIOD 0x8234 1415 #define AR_QUIET_PERIOD 0x8238 1416 #define AR_NDP_PERIOD 0x823C 1417 1418 #define AR_TIMER_MODE 0x8240 1419 #define AR_TBTT_TIMER_EN 0x00000001 1420 #define AR_DBA_TIMER_EN 0x00000002 1421 #define AR_SWBA_TIMER_EN 0x00000004 1422 #define AR_HCF_TIMER_EN 0x00000008 1423 #define AR_TIM_TIMER_EN 0x00000010 1424 #define AR_DTIM_TIMER_EN 0x00000020 1425 #define AR_QUIET_TIMER_EN 0x00000040 1426 #define AR_NDP_TIMER_EN 0x00000080 1427 #define AR_TIMER_OVERFLOW_INDEX 0x00000700 1428 #define AR_TIMER_OVERFLOW_INDEX_S 8 1429 #define AR_TIMER_THRESH 0xFFFFF000 1430 #define AR_TIMER_THRESH_S 12 1431 1432 #define AR_SLP32_MODE 0x8244 1433 #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF 1434 #define AR_SLP32_ENA 0x00100000 1435 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1436 1437 #define AR_SLP32_WAKE 0x8248 1438 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF 1439 1440 #define AR_SLP32_INC 0x824c 1441 #define AR_SLP32_TST_INC 0x000FFFFF 1442 1443 #define AR_SLP_CNT 0x8250 1444 #define AR_SLP_CYCLE_CNT 0x8254 1445 1446 #define AR_SLP_MIB_CTRL 0x8258 1447 #define AR_SLP_MIB_CLEAR 0x00000001 1448 #define AR_SLP_MIB_PENDING 0x00000002 1449 1450 #define AR_2040_MODE 0x8318 1451 #define AR_2040_JOINED_RX_CLEAR 0x00000001 1452 1453 1454 #define AR_EXTRCCNT 0x8328 1455 1456 #define AR_SELFGEN_MASK 0x832c 1457 1458 #define AR_PCU_TXBUF_CTRL 0x8340 1459 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 1460 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 1461 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 1462 1463 #define AR_KEYTABLE_0 0x8800 1464 #define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) 1465 #define AR_KEY_CACHE_SIZE 128 1466 #define AR_RSVD_KEYTABLE_ENTRIES 4 1467 #define AR_KEY_TYPE 0x00000007 1468 #define AR_KEYTABLE_TYPE_40 0x00000000 1469 #define AR_KEYTABLE_TYPE_104 0x00000001 1470 #define AR_KEYTABLE_TYPE_128 0x00000003 1471 #define AR_KEYTABLE_TYPE_TKIP 0x00000004 1472 #define AR_KEYTABLE_TYPE_AES 0x00000005 1473 #define AR_KEYTABLE_TYPE_CCM 0x00000006 1474 #define AR_KEYTABLE_TYPE_CLR 0x00000007 1475 #define AR_KEYTABLE_ANT 0x00000008 1476 #define AR_KEYTABLE_VALID 0x00008000 1477 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) 1478 #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) 1479 #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) 1480 #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) 1481 #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) 1482 #define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) 1483 #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) 1484 #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) 1485 1486 #endif 1487