Lines Matching refs:__raw_writel
250 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR, in iop13xx_atux_pci_status()
286 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atux_read_config()
315 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
317 __raw_writel(addr, IOP13XX_ATUX_OCCAR); in iop13xx_atux_write_config()
318 __raw_writel(value, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
382 __raw_writel(status, IOP13XX_ATUE_PIE_STS); in iop13xx_atue_pci_status()
407 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_read()
429 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atue_read_config()
462 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR); in iop13xx_atue_write_config()
464 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_write_config()
465 __raw_writel(value, IOP13XX_ATUE_OCCDR); in iop13xx_atue_write_config()
563 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); in iop13xx_atue_setup()
564 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0); in iop13xx_atue_setup()
565 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0); in iop13xx_atue_setup()
566 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0); in iop13xx_atue_setup()
571 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, in iop13xx_atue_setup()
573 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); in iop13xx_atue_setup()
576 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | in iop13xx_atue_setup()
582 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); in iop13xx_atue_setup()
583 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1); in iop13xx_atue_setup()
587 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1); in iop13xx_atue_setup()
589 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE | in iop13xx_atue_setup()
596 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000), in iop13xx_atue_setup()
598 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); in iop13xx_atue_setup()
608 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR); in iop13xx_atue_setup()
616 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); in iop13xx_atue_setup()
622 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); in iop13xx_atue_setup()
628 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); in iop13xx_atue_setup()
634 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); in iop13xx_atue_setup()
646 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR); in iop13xx_atue_setup()
654 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR); in iop13xx_atue_disable()
663 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0); in iop13xx_atue_disable()
664 __raw_writel(0x0, IOP13XX_ATUE_IABAR0); in iop13xx_atue_disable()
665 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0); in iop13xx_atue_disable()
666 __raw_writel(0x0, IOP13XX_ATUE_IATVR0); in iop13xx_atue_disable()
667 __raw_writel(0x0, IOP13XX_ATUE_IALR0); in iop13xx_atue_disable()
670 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); in iop13xx_atue_disable()
673 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); in iop13xx_atue_disable()
674 __raw_writel(0x0, IOP13XX_ATUE_IABAR1); in iop13xx_atue_disable()
675 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); in iop13xx_atue_disable()
676 __raw_writel(0x0, IOP13XX_ATUE_IATVR1); in iop13xx_atue_disable()
677 __raw_writel(0x0, IOP13XX_ATUE_IALR1); in iop13xx_atue_disable()
680 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); in iop13xx_atue_disable()
683 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2); in iop13xx_atue_disable()
684 __raw_writel(0x0, IOP13XX_ATUE_IABAR2); in iop13xx_atue_disable()
685 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2); in iop13xx_atue_disable()
686 __raw_writel(0x0, IOP13XX_ATUE_IATVR2); in iop13xx_atue_disable()
687 __raw_writel(0x0, IOP13XX_ATUE_IALR2); in iop13xx_atue_disable()
690 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); in iop13xx_atue_disable()
695 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); in iop13xx_atue_disable()
700 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000, in iop13xx_atue_disable()
702 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); in iop13xx_atue_disable()
723 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT, in iop13xx_atux_setup()
732 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); in iop13xx_atux_setup()
733 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0); in iop13xx_atux_setup()
734 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0); in iop13xx_atux_setup()
735 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0); in iop13xx_atux_setup()
740 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, in iop13xx_atux_setup()
742 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); in iop13xx_atux_setup()
745 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | in iop13xx_atux_setup()
751 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); in iop13xx_atux_setup()
752 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1); in iop13xx_atux_setup()
756 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1); in iop13xx_atux_setup()
758 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE | in iop13xx_atux_setup()
765 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, in iop13xx_atux_setup()
767 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); in iop13xx_atux_setup()
777 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR); in iop13xx_atux_setup()
785 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); in iop13xx_atux_setup()
791 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); in iop13xx_atux_setup()
797 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); in iop13xx_atux_setup()
803 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); in iop13xx_atux_setup()
814 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR); in iop13xx_atux_setup()
822 __raw_writel(0x0, IOP13XX_ATUX_ATUCR); in iop13xx_atux_disable()
830 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0); in iop13xx_atux_disable()
831 __raw_writel(0x0, IOP13XX_ATUX_IABAR0); in iop13xx_atux_disable()
832 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0); in iop13xx_atux_disable()
833 __raw_writel(0x0, IOP13XX_ATUX_IATVR0); in iop13xx_atux_disable()
834 __raw_writel(0x0, IOP13XX_ATUX_IALR0); in iop13xx_atux_disable()
837 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); in iop13xx_atux_disable()
840 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); in iop13xx_atux_disable()
841 __raw_writel(0x0, IOP13XX_ATUX_IABAR1); in iop13xx_atux_disable()
842 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); in iop13xx_atux_disable()
843 __raw_writel(0x0, IOP13XX_ATUX_IATVR1); in iop13xx_atux_disable()
844 __raw_writel(0x0, IOP13XX_ATUX_IALR1); in iop13xx_atux_disable()
847 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); in iop13xx_atux_disable()
850 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2); in iop13xx_atux_disable()
851 __raw_writel(0x0, IOP13XX_ATUX_IABAR2); in iop13xx_atux_disable()
852 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2); in iop13xx_atux_disable()
853 __raw_writel(0x0, IOP13XX_ATUX_IATVR2); in iop13xx_atux_disable()
854 __raw_writel(0x0, IOP13XX_ATUX_IALR2); in iop13xx_atux_disable()
857 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); in iop13xx_atux_disable()
860 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3); in iop13xx_atux_disable()
861 __raw_writel(0x0, IOP13XX_ATUX_IABAR3); in iop13xx_atux_disable()
862 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3); in iop13xx_atux_disable()
863 __raw_writel(0x0, IOP13XX_ATUX_IATVR3); in iop13xx_atux_disable()
864 __raw_writel(0x0, IOP13XX_ATUX_IALR3); in iop13xx_atux_disable()
867 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); in iop13xx_atux_disable()
872 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, in iop13xx_atux_disable()
874 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); in iop13xx_atux_disable()
968 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); in iop13xx_pci_init()
1040 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); in iop13xx_pci_setup()
1057 __raw_writel(pcsr, IOP13XX_ATUE_PCSR); in iop13xx_pci_setup()