Lines Matching refs:reg_val
559 u32 reg_val; in iop13xx_atue_setup() local
605 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR); in iop13xx_atue_setup()
606 reg_val &= ~0x7; in iop13xx_atue_setup()
607 reg_val |= func; in iop13xx_atue_setup()
608 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR); in iop13xx_atue_setup()
612 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0); in iop13xx_atue_setup()
613 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << in iop13xx_atue_setup()
615 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; in iop13xx_atue_setup()
616 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); in iop13xx_atue_setup()
618 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1); in iop13xx_atue_setup()
619 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << in iop13xx_atue_setup()
621 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; in iop13xx_atue_setup()
622 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); in iop13xx_atue_setup()
624 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2); in iop13xx_atue_setup()
625 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << in iop13xx_atue_setup()
627 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; in iop13xx_atue_setup()
628 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); in iop13xx_atue_setup()
630 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3); in iop13xx_atue_setup()
631 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << in iop13xx_atue_setup()
633 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; in iop13xx_atue_setup()
634 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); in iop13xx_atue_setup()
638 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD); in iop13xx_atue_setup()
639 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | in iop13xx_atue_setup()
641 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD); in iop13xx_atue_setup()
643 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR); in iop13xx_atue_setup()
644 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN | in iop13xx_atue_setup()
646 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR); in iop13xx_atue_setup()
651 u32 reg_val; in iop13xx_atue_disable() local
668 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0); in iop13xx_atue_disable()
669 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; in iop13xx_atue_disable()
670 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); in iop13xx_atue_disable()
678 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1); in iop13xx_atue_disable()
679 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; in iop13xx_atue_disable()
680 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); in iop13xx_atue_disable()
688 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2); in iop13xx_atue_disable()
689 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; in iop13xx_atue_disable()
690 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); in iop13xx_atue_disable()
693 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3); in iop13xx_atue_disable()
694 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; in iop13xx_atue_disable()
695 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); in iop13xx_atue_disable()
711 u32 reg_val; in iop13xx_atux_setup() local
719 reg_val = __raw_readl(IOP13XX_ATUX_PCSR); in iop13xx_atux_setup()
720 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) { in iop13xx_atux_setup()
721 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7; in iop13xx_atux_setup()
723 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT, in iop13xx_atux_setup()
774 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR); in iop13xx_atux_setup()
775 reg_val &= ~0x7; in iop13xx_atux_setup()
776 reg_val |= func; in iop13xx_atux_setup()
777 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR); in iop13xx_atux_setup()
781 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0); in iop13xx_atux_setup()
782 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << in iop13xx_atux_setup()
784 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; in iop13xx_atux_setup()
785 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); in iop13xx_atux_setup()
787 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1); in iop13xx_atux_setup()
788 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << in iop13xx_atux_setup()
790 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; in iop13xx_atux_setup()
791 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); in iop13xx_atux_setup()
793 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2); in iop13xx_atux_setup()
794 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << in iop13xx_atux_setup()
796 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; in iop13xx_atux_setup()
797 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); in iop13xx_atux_setup()
799 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3); in iop13xx_atux_setup()
800 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << in iop13xx_atux_setup()
802 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; in iop13xx_atux_setup()
803 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); in iop13xx_atux_setup()
807 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD); in iop13xx_atux_setup()
808 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | in iop13xx_atux_setup()
810 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD); in iop13xx_atux_setup()
812 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR); in iop13xx_atux_setup()
813 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN; in iop13xx_atux_setup()
814 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR); in iop13xx_atux_setup()
819 u32 reg_val; in iop13xx_atux_disable() local
835 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0); in iop13xx_atux_disable()
836 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; in iop13xx_atux_disable()
837 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); in iop13xx_atux_disable()
845 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1); in iop13xx_atux_disable()
846 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; in iop13xx_atux_disable()
847 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); in iop13xx_atux_disable()
855 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2); in iop13xx_atux_disable()
856 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; in iop13xx_atux_disable()
857 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); in iop13xx_atux_disable()
865 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3); in iop13xx_atux_disable()
866 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; in iop13xx_atux_disable()
867 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); in iop13xx_atux_disable()