3132 #undef ZERO
3133 #define ZERO(reg) writel(0, port_mmio + (reg))  macro
3141 	ZERO(0x028);	/* command */  in mv5_reset_hc_port()
3143 	ZERO(0x004);	/* timer */  in mv5_reset_hc_port()
3144 	ZERO(0x008);	/* irq err cause */  in mv5_reset_hc_port()
3145 	ZERO(0x00c);	/* irq err mask */  in mv5_reset_hc_port()
3146 	ZERO(0x010);	/* rq bah */  in mv5_reset_hc_port()
3147 	ZERO(0x014);	/* rq inp */  in mv5_reset_hc_port()
3148 	ZERO(0x018);	/* rq outp */  in mv5_reset_hc_port()
3149 	ZERO(0x01c);	/* respq bah */  in mv5_reset_hc_port()
3150 	ZERO(0x024);	/* respq outp */  in mv5_reset_hc_port()
3151 	ZERO(0x020);	/* respq inp */  in mv5_reset_hc_port()
3152 	ZERO(0x02c);	/* test control */  in mv5_reset_hc_port()
3155 #undef ZERO
3157 #define ZERO(reg) writel(0, hc_mmio + (reg))  macro
3164 	ZERO(0x00c);  in mv5_reset_one_hc()
3165 	ZERO(0x010);  in mv5_reset_one_hc()
3166 	ZERO(0x014);  in mv5_reset_one_hc()
3167 	ZERO(0x018);  in mv5_reset_one_hc()
3174 #undef ZERO
3192 #undef ZERO
3193 #define ZERO(reg) writel(0, mmio + (reg))  macro
3203 	ZERO(MV_PCI_DISC_TIMER);  in mv_reset_pci_bus()
3204 	ZERO(MV_PCI_MSI_TRIGGER);  in mv_reset_pci_bus()
3206 	ZERO(MV_PCI_SERR_MASK);  in mv_reset_pci_bus()
3207 	ZERO(hpriv->irq_cause_offset);  in mv_reset_pci_bus()
3208 	ZERO(hpriv->irq_mask_offset);  in mv_reset_pci_bus()
3209 	ZERO(MV_PCI_ERR_LOW_ADDRESS);  in mv_reset_pci_bus()
3210 	ZERO(MV_PCI_ERR_HIGH_ADDRESS);  in mv_reset_pci_bus()
3211 	ZERO(MV_PCI_ERR_ATTRIBUTE);  in mv_reset_pci_bus()
3212 	ZERO(MV_PCI_ERR_COMMAND);  in mv_reset_pci_bus()
3214 #undef ZERO
3414 #undef ZERO
3415 #define ZERO(reg) writel(0, port_mmio + (reg))  macro
3423 	ZERO(0x028);		/* command */  in mv_soc_reset_hc_port()
3425 	ZERO(0x004);		/* timer */  in mv_soc_reset_hc_port()
3426 	ZERO(0x008);		/* irq err cause */  in mv_soc_reset_hc_port()
3427 	ZERO(0x00c);		/* irq err mask */  in mv_soc_reset_hc_port()
3428 	ZERO(0x010);		/* rq bah */  in mv_soc_reset_hc_port()
3429 	ZERO(0x014);		/* rq inp */  in mv_soc_reset_hc_port()
3430 	ZERO(0x018);		/* rq outp */  in mv_soc_reset_hc_port()
3431 	ZERO(0x01c);		/* respq bah */  in mv_soc_reset_hc_port()
3432 	ZERO(0x024);		/* respq outp */  in mv_soc_reset_hc_port()
3433 	ZERO(0x020);		/* respq inp */  in mv_soc_reset_hc_port()
3434 	ZERO(0x02c);		/* test control */  in mv_soc_reset_hc_port()
3438 #undef ZERO
3440 #define ZERO(reg) writel(0, hc_mmio + (reg))  macro
3446 	ZERO(0x00c);  in mv_soc_reset_one_hc()
3447 	ZERO(0x010);  in mv_soc_reset_one_hc()
3448 	ZERO(0x014);  in mv_soc_reset_one_hc()
3452 #undef ZERO