Lines Matching refs:clk
347 static struct clk *clks[clk_max];
844 struct clk *clk; in tegra30_pll_init() local
847 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
851 clk_register_clkdev(clk, "pll_c", NULL); in tegra30_pll_init()
852 clks[pll_c] = clk; in tegra30_pll_init()
855 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra30_pll_init()
858 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", in tegra30_pll_init()
861 clk_register_clkdev(clk, "pll_c_out1", NULL); in tegra30_pll_init()
862 clks[pll_c_out1] = clk; in tegra30_pll_init()
865 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
869 clk_register_clkdev(clk, "pll_p", NULL); in tegra30_pll_init()
870 clks[pll_p] = clk; in tegra30_pll_init()
873 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", in tegra30_pll_init()
877 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", in tegra30_pll_init()
881 clk_register_clkdev(clk, "pll_p_out1", NULL); in tegra30_pll_init()
882 clks[pll_p_out1] = clk; in tegra30_pll_init()
885 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", in tegra30_pll_init()
889 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", in tegra30_pll_init()
893 clk_register_clkdev(clk, "pll_p_out2", NULL); in tegra30_pll_init()
894 clks[pll_p_out2] = clk; in tegra30_pll_init()
897 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", in tegra30_pll_init()
901 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", in tegra30_pll_init()
905 clk_register_clkdev(clk, "pll_p_out3", NULL); in tegra30_pll_init()
906 clks[pll_p_out3] = clk; in tegra30_pll_init()
909 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", in tegra30_pll_init()
913 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", in tegra30_pll_init()
917 clk_register_clkdev(clk, "pll_p_out4", NULL); in tegra30_pll_init()
918 clks[pll_p_out4] = clk; in tegra30_pll_init()
921 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, in tegra30_pll_init()
926 clk_register_clkdev(clk, "pll_m", NULL); in tegra30_pll_init()
927 clks[pll_m] = clk; in tegra30_pll_init()
930 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", in tegra30_pll_init()
933 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", in tegra30_pll_init()
936 clk_register_clkdev(clk, "pll_m_out1", NULL); in tegra30_pll_init()
937 clks[pll_m_out1] = clk; in tegra30_pll_init()
940 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
944 clk_register_clkdev(clk, "pll_x", NULL); in tegra30_pll_init()
945 clks[pll_x] = clk; in tegra30_pll_init()
948 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", in tegra30_pll_init()
950 clk_register_clkdev(clk, "pll_x_out0", NULL); in tegra30_pll_init()
951 clks[pll_x_out0] = clk; in tegra30_pll_init()
954 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
959 clk_register_clkdev(clk, "pll_u", NULL); in tegra30_pll_init()
960 clks[pll_u] = clk; in tegra30_pll_init()
965 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
969 clk_register_clkdev(clk, "pll_d", NULL); in tegra30_pll_init()
970 clks[pll_d] = clk; in tegra30_pll_init()
973 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", in tegra30_pll_init()
975 clk_register_clkdev(clk, "pll_d_out0", NULL); in tegra30_pll_init()
976 clks[pll_d_out0] = clk; in tegra30_pll_init()
979 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
983 clk_register_clkdev(clk, "pll_d2", NULL); in tegra30_pll_init()
984 clks[pll_d2] = clk; in tegra30_pll_init()
987 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", in tegra30_pll_init()
989 clk_register_clkdev(clk, "pll_d2_out0", NULL); in tegra30_pll_init()
990 clks[pll_d2_out0] = clk; in tegra30_pll_init()
993 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base, in tegra30_pll_init()
996 clk_register_clkdev(clk, "pll_a", NULL); in tegra30_pll_init()
997 clks[pll_a] = clk; in tegra30_pll_init()
1000 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", in tegra30_pll_init()
1003 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", in tegra30_pll_init()
1006 clk_register_clkdev(clk, "pll_a_out0", NULL); in tegra30_pll_init()
1007 clks[pll_a_out0] = clk; in tegra30_pll_init()
1010 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, in tegra30_pll_init()
1013 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, in tegra30_pll_init()
1016 clk_register_clkdev(clk, "pll_e", NULL); in tegra30_pll_init()
1017 clks[pll_e] = clk; in tegra30_pll_init()
1031 struct clk *clk; in tegra30_audio_clk_init() local
1034 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, in tegra30_audio_clk_init()
1036 clk_register_clkdev(clk, "spdif_in_sync", NULL); in tegra30_audio_clk_init()
1037 clks[spdif_in_sync] = clk; in tegra30_audio_clk_init()
1040 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); in tegra30_audio_clk_init()
1041 clk_register_clkdev(clk, "i2s0_sync", NULL); in tegra30_audio_clk_init()
1042 clks[i2s0_sync] = clk; in tegra30_audio_clk_init()
1045 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); in tegra30_audio_clk_init()
1046 clk_register_clkdev(clk, "i2s1_sync", NULL); in tegra30_audio_clk_init()
1047 clks[i2s1_sync] = clk; in tegra30_audio_clk_init()
1050 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); in tegra30_audio_clk_init()
1051 clk_register_clkdev(clk, "i2s2_sync", NULL); in tegra30_audio_clk_init()
1052 clks[i2s2_sync] = clk; in tegra30_audio_clk_init()
1055 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); in tegra30_audio_clk_init()
1056 clk_register_clkdev(clk, "i2s3_sync", NULL); in tegra30_audio_clk_init()
1057 clks[i2s3_sync] = clk; in tegra30_audio_clk_init()
1060 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); in tegra30_audio_clk_init()
1061 clk_register_clkdev(clk, "i2s4_sync", NULL); in tegra30_audio_clk_init()
1062 clks[i2s4_sync] = clk; in tegra30_audio_clk_init()
1065 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); in tegra30_audio_clk_init()
1066 clk_register_clkdev(clk, "vimclk_sync", NULL); in tegra30_audio_clk_init()
1067 clks[vimclk_sync] = clk; in tegra30_audio_clk_init()
1070 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, in tegra30_audio_clk_init()
1073 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, in tegra30_audio_clk_init()
1076 clk_register_clkdev(clk, "audio0", NULL); in tegra30_audio_clk_init()
1077 clks[audio0] = clk; in tegra30_audio_clk_init()
1080 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, in tegra30_audio_clk_init()
1083 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, in tegra30_audio_clk_init()
1086 clk_register_clkdev(clk, "audio1", NULL); in tegra30_audio_clk_init()
1087 clks[audio1] = clk; in tegra30_audio_clk_init()
1090 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, in tegra30_audio_clk_init()
1093 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, in tegra30_audio_clk_init()
1096 clk_register_clkdev(clk, "audio2", NULL); in tegra30_audio_clk_init()
1097 clks[audio2] = clk; in tegra30_audio_clk_init()
1100 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, in tegra30_audio_clk_init()
1103 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, in tegra30_audio_clk_init()
1106 clk_register_clkdev(clk, "audio3", NULL); in tegra30_audio_clk_init()
1107 clks[audio3] = clk; in tegra30_audio_clk_init()
1110 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, in tegra30_audio_clk_init()
1113 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, in tegra30_audio_clk_init()
1116 clk_register_clkdev(clk, "audio4", NULL); in tegra30_audio_clk_init()
1117 clks[audio4] = clk; in tegra30_audio_clk_init()
1120 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, in tegra30_audio_clk_init()
1123 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, in tegra30_audio_clk_init()
1126 clk_register_clkdev(clk, "spdif", NULL); in tegra30_audio_clk_init()
1127 clks[spdif] = clk; in tegra30_audio_clk_init()
1130 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", in tegra30_audio_clk_init()
1132 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", in tegra30_audio_clk_init()
1135 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", in tegra30_audio_clk_init()
1139 clk_register_clkdev(clk, "audio0_2x", NULL); in tegra30_audio_clk_init()
1140 clks[audio0_2x] = clk; in tegra30_audio_clk_init()
1143 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", in tegra30_audio_clk_init()
1145 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", in tegra30_audio_clk_init()
1148 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", in tegra30_audio_clk_init()
1152 clk_register_clkdev(clk, "audio1_2x", NULL); in tegra30_audio_clk_init()
1153 clks[audio1_2x] = clk; in tegra30_audio_clk_init()
1156 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", in tegra30_audio_clk_init()
1158 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", in tegra30_audio_clk_init()
1161 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", in tegra30_audio_clk_init()
1165 clk_register_clkdev(clk, "audio2_2x", NULL); in tegra30_audio_clk_init()
1166 clks[audio2_2x] = clk; in tegra30_audio_clk_init()
1169 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", in tegra30_audio_clk_init()
1171 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", in tegra30_audio_clk_init()
1174 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", in tegra30_audio_clk_init()
1178 clk_register_clkdev(clk, "audio3_2x", NULL); in tegra30_audio_clk_init()
1179 clks[audio3_2x] = clk; in tegra30_audio_clk_init()
1182 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", in tegra30_audio_clk_init()
1184 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", in tegra30_audio_clk_init()
1187 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", in tegra30_audio_clk_init()
1191 clk_register_clkdev(clk, "audio4_2x", NULL); in tegra30_audio_clk_init()
1192 clks[audio4_2x] = clk; in tegra30_audio_clk_init()
1195 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", in tegra30_audio_clk_init()
1197 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", in tegra30_audio_clk_init()
1200 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", in tegra30_audio_clk_init()
1204 clk_register_clkdev(clk, "spdif_2x", NULL); in tegra30_audio_clk_init()
1205 clks[spdif_2x] = clk; in tegra30_audio_clk_init()
1210 struct clk *clk; in tegra30_pmc_clk_init() local
1213 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, in tegra30_pmc_clk_init()
1217 clks[clk_out_1_mux] = clk; in tegra30_pmc_clk_init()
1218 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, in tegra30_pmc_clk_init()
1221 clk_register_clkdev(clk, "extern1", "clk_out_1"); in tegra30_pmc_clk_init()
1222 clks[clk_out_1] = clk; in tegra30_pmc_clk_init()
1225 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, in tegra30_pmc_clk_init()
1229 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, in tegra30_pmc_clk_init()
1232 clk_register_clkdev(clk, "extern2", "clk_out_2"); in tegra30_pmc_clk_init()
1233 clks[clk_out_2] = clk; in tegra30_pmc_clk_init()
1236 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, in tegra30_pmc_clk_init()
1240 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, in tegra30_pmc_clk_init()
1243 clk_register_clkdev(clk, "extern3", "clk_out_3"); in tegra30_pmc_clk_init()
1244 clks[clk_out_3] = clk; in tegra30_pmc_clk_init()
1248 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, in tegra30_pmc_clk_init()
1251 clk = clk_register_gate(NULL, "blink", "blink_override", 0, in tegra30_pmc_clk_init()
1254 clk_register_clkdev(clk, "blink", NULL); in tegra30_pmc_clk_init()
1255 clks[blink] = clk; in tegra30_pmc_clk_init()
1272 struct clk *clk; in tegra30_super_clk_init() local
1278 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", in tegra30_super_clk_init()
1281 clk_register_clkdev(clk, "pll_p_cclkg", NULL); in tegra30_super_clk_init()
1287 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", in tegra30_super_clk_init()
1290 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL); in tegra30_super_clk_init()
1296 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", in tegra30_super_clk_init()
1299 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); in tegra30_super_clk_init()
1302 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, in tegra30_super_clk_init()
1307 clk_register_clkdev(clk, "cclk_g", NULL); in tegra30_super_clk_init()
1308 clks[cclk_g] = clk; in tegra30_super_clk_init()
1314 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", in tegra30_super_clk_init()
1317 clk_register_clkdev(clk, "pll_p_cclklp", NULL); in tegra30_super_clk_init()
1323 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", in tegra30_super_clk_init()
1326 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); in tegra30_super_clk_init()
1332 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", in tegra30_super_clk_init()
1335 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL); in tegra30_super_clk_init()
1338 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, in tegra30_super_clk_init()
1344 clk_register_clkdev(clk, "cclk_lp", NULL); in tegra30_super_clk_init()
1345 clks[cclk_lp] = clk; in tegra30_super_clk_init()
1348 clk = tegra_clk_register_super_mux("sclk", sclk_parents, in tegra30_super_clk_init()
1353 clk_register_clkdev(clk, "sclk", NULL); in tegra30_super_clk_init()
1354 clks[sclk] = clk; in tegra30_super_clk_init()
1357 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, in tegra30_super_clk_init()
1360 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, in tegra30_super_clk_init()
1363 clk_register_clkdev(clk, "hclk", NULL); in tegra30_super_clk_init()
1364 clks[hclk] = clk; in tegra30_super_clk_init()
1367 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, in tegra30_super_clk_init()
1370 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, in tegra30_super_clk_init()
1373 clk_register_clkdev(clk, "pclk", NULL); in tegra30_super_clk_init()
1374 clks[pclk] = clk; in tegra30_super_clk_init()
1377 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", in tegra30_super_clk_init()
1379 clk_register_clkdev(clk, "twd", NULL); in tegra30_super_clk_init()
1380 clks[twd] = clk; in tegra30_super_clk_init()
1494 struct clk *clk; in tegra30_periph_clk_init() local
1498 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34, in tegra30_periph_clk_init()
1500 clk_register_clkdev(clk, NULL, "tegra-apbdma"); in tegra30_periph_clk_init()
1501 clks[apbdma] = clk; in tegra30_periph_clk_init()
1504 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", in tegra30_periph_clk_init()
1508 clk_register_clkdev(clk, NULL, "rtc-tegra"); in tegra30_periph_clk_init()
1509 clks[rtc] = clk; in tegra30_periph_clk_init()
1512 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1514 clk_register_clkdev(clk, NULL, "timer"); in tegra30_periph_clk_init()
1515 clks[timer] = clk; in tegra30_periph_clk_init()
1518 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", in tegra30_periph_clk_init()
1522 clk_register_clkdev(clk, NULL, "tegra-kbc"); in tegra30_periph_clk_init()
1523 clks[kbc] = clk; in tegra30_periph_clk_init()
1526 clk = tegra_clk_register_periph_gate("csus", "clk_m", in tegra30_periph_clk_init()
1530 clk_register_clkdev(clk, "csus", "tengra_camera"); in tegra30_periph_clk_init()
1531 clks[csus] = clk; in tegra30_periph_clk_init()
1534 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29, in tegra30_periph_clk_init()
1536 clk_register_clkdev(clk, "vcp", "tegra-avp"); in tegra30_periph_clk_init()
1537 clks[vcp] = clk; in tegra30_periph_clk_init()
1540 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1542 clk_register_clkdev(clk, "bsea", "tegra-avp"); in tegra30_periph_clk_init()
1543 clks[bsea] = clk; in tegra30_periph_clk_init()
1546 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1548 clk_register_clkdev(clk, "bsev", "tegra-aes"); in tegra30_periph_clk_init()
1549 clks[bsev] = clk; in tegra30_periph_clk_init()
1552 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1554 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); in tegra30_periph_clk_init()
1555 clks[usbd] = clk; in tegra30_periph_clk_init()
1558 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1560 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); in tegra30_periph_clk_init()
1561 clks[usb2] = clk; in tegra30_periph_clk_init()
1564 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1566 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); in tegra30_periph_clk_init()
1567 clks[usb3] = clk; in tegra30_periph_clk_init()
1570 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, in tegra30_periph_clk_init()
1573 clk_register_clkdev(clk, "dsia", "tegradc.0"); in tegra30_periph_clk_init()
1574 clks[dsia] = clk; in tegra30_periph_clk_init()
1577 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, in tegra30_periph_clk_init()
1580 clk_register_clkdev(clk, "csi", "tegra_camera"); in tegra30_periph_clk_init()
1581 clks[csi] = clk; in tegra30_periph_clk_init()
1584 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, in tegra30_periph_clk_init()
1586 clk_register_clkdev(clk, "isp", "tegra_camera"); in tegra30_periph_clk_init()
1587 clks[isp] = clk; in tegra30_periph_clk_init()
1590 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1592 clk_register_clkdev(clk, "pcie", "tegra-pcie"); in tegra30_periph_clk_init()
1593 clks[pcie] = clk; in tegra30_periph_clk_init()
1596 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, in tegra30_periph_clk_init()
1598 clk_register_clkdev(clk, "afi", "tegra-pcie"); in tegra30_periph_clk_init()
1599 clks[afi] = clk; in tegra30_periph_clk_init()
1602 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0, in tegra30_periph_clk_init()
1604 clk_register_clkdev(clk, "pciex", "tegra-pcie"); in tegra30_periph_clk_init()
1605 clks[pciex] = clk; in tegra30_periph_clk_init()
1608 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", in tegra30_periph_clk_init()
1612 clk_register_clkdev(clk, NULL, "kfuse-tegra"); in tegra30_periph_clk_init()
1613 clks[kfuse] = clk; in tegra30_periph_clk_init()
1616 clk = tegra_clk_register_periph_gate("fuse", "clk_m", in tegra30_periph_clk_init()
1620 clk_register_clkdev(clk, "fuse", "fuse-tegra"); in tegra30_periph_clk_init()
1621 clks[fuse] = clk; in tegra30_periph_clk_init()
1624 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", in tegra30_periph_clk_init()
1628 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra"); in tegra30_periph_clk_init()
1629 clks[fuse_burn] = clk; in tegra30_periph_clk_init()
1632 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0, in tegra30_periph_clk_init()
1635 clk_register_clkdev(clk, "apbif", "tegra30-ahub"); in tegra30_periph_clk_init()
1636 clks[apbif] = clk; in tegra30_periph_clk_init()
1639 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", in tegra30_periph_clk_init()
1643 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda"); in tegra30_periph_clk_init()
1644 clks[hda2hdmi] = clk; in tegra30_periph_clk_init()
1647 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m", in tegra30_periph_clk_init()
1651 clk_register_clkdev(clk, NULL, "tegra_sata_cold"); in tegra30_periph_clk_init()
1652 clks[sata_cold] = clk; in tegra30_periph_clk_init()
1655 clk = tegra_clk_register_periph_gate("dtv", "clk_m", in tegra30_periph_clk_init()
1659 clk_register_clkdev(clk, NULL, "dtv"); in tegra30_periph_clk_init()
1660 clks[dtv] = clk; in tegra30_periph_clk_init()
1663 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, in tegra30_periph_clk_init()
1667 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, in tegra30_periph_clk_init()
1669 clk_register_clkdev(clk, "emc", NULL); in tegra30_periph_clk_init()
1670 clks[emc] = clk; in tegra30_periph_clk_init()
1674 clk = tegra_clk_register_periph(data->name, data->parent_names, in tegra30_periph_clk_init()
1677 clk_register_clkdev(clk, data->con_id, data->dev_id); in tegra30_periph_clk_init()
1678 clks[data->clk_id] = clk; in tegra30_periph_clk_init()
1683 clk = tegra_clk_register_periph_nodiv(data->name, in tegra30_periph_clk_init()
1687 clk_register_clkdev(clk, data->con_id, data->dev_id); in tegra30_periph_clk_init()
1688 clks[data->clk_id] = clk; in tegra30_periph_clk_init()
1694 struct clk *clk; in tegra30_fixed_clk_init() local
1697 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, in tegra30_fixed_clk_init()
1699 clk_register_clkdev(clk, "clk_32k", NULL); in tegra30_fixed_clk_init()
1700 clks[clk_32k] = clk; in tegra30_fixed_clk_init()
1703 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", in tegra30_fixed_clk_init()
1705 clk_register_clkdev(clk, "clk_m_div2", NULL); in tegra30_fixed_clk_init()
1706 clks[clk_m_div2] = clk; in tegra30_fixed_clk_init()
1709 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", in tegra30_fixed_clk_init()
1711 clk_register_clkdev(clk, "clk_m_div4", NULL); in tegra30_fixed_clk_init()
1712 clks[clk_m_div4] = clk; in tegra30_fixed_clk_init()
1715 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_fixed_clk_init()
1717 clk_register_clkdev(clk, "cml0", NULL); in tegra30_fixed_clk_init()
1718 clks[cml0] = clk; in tegra30_fixed_clk_init()
1721 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_fixed_clk_init()
1723 clk_register_clkdev(clk, "cml1", NULL); in tegra30_fixed_clk_init()
1724 clks[cml1] = clk; in tegra30_fixed_clk_init()
1729 struct clk *clk; in tegra30_osc_clk_init() local
1735 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, in tegra30_osc_clk_init()
1737 clk_register_clkdev(clk, "clk_m", NULL); in tegra30_osc_clk_init()
1738 clks[clk_m] = clk; in tegra30_osc_clk_init()
1742 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", in tegra30_osc_clk_init()
1744 clk_register_clkdev(clk, "pll_ref", NULL); in tegra30_osc_clk_init()
1745 clks[pll_ref] = clk; in tegra30_osc_clk_init()