Lines Matching refs:clk
53 struct clk *clk; in realview_clk_init() local
56 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); in realview_clk_init()
57 clk_register_clkdev(clk, "apb_pclk", NULL); in realview_clk_init()
60 clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT, in realview_clk_init()
62 clk_register_clkdev(clk, NULL, "dev:uart0"); in realview_clk_init()
63 clk_register_clkdev(clk, NULL, "dev:uart1"); in realview_clk_init()
64 clk_register_clkdev(clk, NULL, "dev:uart2"); in realview_clk_init()
65 clk_register_clkdev(clk, NULL, "fpga:kmi0"); in realview_clk_init()
66 clk_register_clkdev(clk, NULL, "fpga:kmi1"); in realview_clk_init()
67 clk_register_clkdev(clk, NULL, "fpga:mmc0"); in realview_clk_init()
68 clk_register_clkdev(clk, NULL, "dev:ssp0"); in realview_clk_init()
74 clk_register_clkdev(clk, NULL, "dev:uart3"); in realview_clk_init()
75 clk_register_clkdev(clk, NULL, "dev:uart4"); in realview_clk_init()
77 clk_register_clkdev(clk, NULL, "fpga:uart3"); in realview_clk_init()
81 clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT, in realview_clk_init()
83 clk_register_clkdev(clk, NULL, "sp804"); in realview_clk_init()
87 clk = icst_clk_register(NULL, &realview_osc0_desc, sysbase); in realview_clk_init()
89 clk = icst_clk_register(NULL, &realview_osc4_desc, sysbase); in realview_clk_init()
91 clk_register_clkdev(clk, NULL, "dev:clcd"); in realview_clk_init()
92 clk_register_clkdev(clk, NULL, "issp:clcd"); in realview_clk_init()