145 	struct sahara_hw_desc	*hw_desc[SAHARA_MAX_HW_DESC];  member
375 		dev_dbg(dev->device, "\thdr = 0x%08x\n", dev->hw_desc[i]->hdr);  in sahara_dump_descriptors()
376 		dev_dbg(dev->device, "\tlen1 = %u\n", dev->hw_desc[i]->len1);  in sahara_dump_descriptors()
377 		dev_dbg(dev->device, "\tp1 = 0x%08x\n", dev->hw_desc[i]->p1);  in sahara_dump_descriptors()
378 		dev_dbg(dev->device, "\tlen2 = %u\n", dev->hw_desc[i]->len2);  in sahara_dump_descriptors()
379 		dev_dbg(dev->device, "\tp2 = 0x%08x\n", dev->hw_desc[i]->p2);  in sahara_dump_descriptors()
381 			dev->hw_desc[i]->next);  in sahara_dump_descriptors()
445 			dev->hw_desc[0]->len1 = AES_BLOCK_SIZE;  in sahara_hw_descriptor_create()
446 			dev->hw_desc[0]->p1 = dev->iv_phys_base;  in sahara_hw_descriptor_create()
448 			dev->hw_desc[0]->len1 = 0;  in sahara_hw_descriptor_create()
449 			dev->hw_desc[0]->p1 = 0;  in sahara_hw_descriptor_create()
451 		dev->hw_desc[0]->len2 = ctx->keylen;  in sahara_hw_descriptor_create()
452 		dev->hw_desc[0]->p2 = dev->key_phys_base;  in sahara_hw_descriptor_create()
453 		dev->hw_desc[0]->next = dev->hw_phys_desc[1];  in sahara_hw_descriptor_create()
455 	dev->hw_desc[0]->hdr = sahara_aes_key_hdr(dev);  in sahara_hw_descriptor_create()
479 	dev->hw_desc[1]->p1 = dev->hw_phys_link[0];  in sahara_hw_descriptor_create()
493 	dev->hw_desc[1]->p2 = dev->hw_phys_link[i];  in sahara_hw_descriptor_create()
507 	dev->hw_desc[1]->hdr = sahara_aes_data_link_hdr(dev);  in sahara_hw_descriptor_create()
508 	dev->hw_desc[1]->len1 = dev->total;  in sahara_hw_descriptor_create()
509 	dev->hw_desc[1]->len2 = dev->total;  in sahara_hw_descriptor_create()
510 	dev->hw_desc[1]->next = 0;  in sahara_hw_descriptor_create()
932 	dev->hw_desc[0] = dma_alloc_coherent(&pdev->dev,  in sahara_probe()
935 	if (!dev->hw_desc[0]) {  in sahara_probe()
939 	dev->hw_desc[1] = dev->hw_desc[0] + 1;  in sahara_probe()
1023 			  dev->hw_desc[0], dev->hw_phys_desc[0]);  in sahara_probe()
1040 			  dev->hw_desc[0], dev->hw_phys_desc[0]);  in sahara_remove()