246 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)  in imx_dmav1_readl()  function
286 		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),  in imxdma_sg_next()
287 		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),  in imxdma_sg_next()
288 		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));  in imxdma_sg_next()
305 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &  in imxdma_enable_hw()
307 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |  in imxdma_enable_hw()
316 			tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));  in imxdma_enable_hw()
337 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |  in imxdma_disable_hw()
339 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &  in imxdma_disable_hw()
366 	disr = imx_dmav1_readl(imxdma, DMA_DISR);  in imxdma_err_handler()
368 	err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |  in imxdma_err_handler()
369 		   imx_dmav1_readl(imxdma, DMA_DRTOSR) |  in imxdma_err_handler()
370 		   imx_dmav1_readl(imxdma, DMA_DSESR)  |  in imxdma_err_handler()
371 		   imx_dmav1_readl(imxdma, DMA_DBOSR);  in imxdma_err_handler()
383 		if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {  in imxdma_err_handler()
387 		if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {  in imxdma_err_handler()
391 		if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {  in imxdma_err_handler()
395 		if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {  in imxdma_err_handler()
436 			tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));  in dma_irq_handle_channel()
482 	disr = imx_dmav1_readl(imxdma, DMA_DISR);  in dma_irq_handler()