125 	void __iomem		*dca_base;  member
164 			writew(id, ioatdca->dca_base + (i * 4));  in ioat_dca_add_requester()
166 			writeb(0, ioatdca->dca_base + (i * 4) + 2);  in ioat_dca_add_requester()
188 			writew(0, ioatdca->dca_base + (i * 4));  in ioat_dca_remove_requester()
298 	ioatdca->dca_base = iobase + 0x54;  in ioat_dca_init()
338 			      readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);  in ioat2_dca_add_requester()
364 			      readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);  in ioat2_dca_remove_requester()
442 	ioatdca->dca_base = iobase + dca_offset;  in ioat2_dca_init()
446 	csi_fsb_control = readw(ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);  in ioat2_dca_init()
450 		       ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);  in ioat2_dca_init()
452 	pcie_control = readw(ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);  in ioat2_dca_init()
456 		       ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);  in ioat2_dca_init()
463 	tag_map = readl(ioatdca->dca_base + IOAT_APICID_TAG_MAP_OFFSET);  in ioat2_dca_init()
514 			      readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);  in ioat3_dca_add_requester()
540 			      readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);  in ioat3_dca_remove_requester()
663 	ioatdca->dca_base = iobase + dca_offset;  in ioat3_dca_init()
667 	csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);  in ioat3_dca_init()
671 		       ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);  in ioat3_dca_init()
673 	pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);  in ioat3_dca_init()
677 		       ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);  in ioat3_dca_init()
685 		readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW);  in ioat3_dca_init()
687 		readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH);  in ioat3_dca_init()