385 		edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n",  in numrank()
398 		edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",  in numrow()
411 		edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",  in numcol()
479 			edac_dbg(1, "Associated %02x.%02x.%d with %p\n",  in get_pdev_slot_func()
528 	edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",  in get_dimm_config()
535 		edac_dbg(0, "Memory mirror is enabled\n");  in get_dimm_config()
538 		edac_dbg(0, "Memory mirror is disabled\n");  in get_dimm_config()
544 		edac_dbg(0, "Lockstep is enabled\n");  in get_dimm_config()
548 		edac_dbg(0, "Lockstep is disabled\n");  in get_dimm_config()
553 		edac_dbg(0, "address map is on closed page mode\n");  in get_dimm_config()
556 		edac_dbg(0, "address map is on open page mode\n");  in get_dimm_config()
564 			edac_dbg(0, "Memory is registered\n");  in get_dimm_config()
567 			edac_dbg(0, "Memory is unregistered\n");  in get_dimm_config()
571 		edac_dbg(0, "Cannot determine memory type\n");  in get_dimm_config()
586 			edac_dbg(4, "Channel #%d  MTR%d = %x\n", i, j, mtr);  in get_dimm_config()
598 …edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\…  in get_dimm_config()
639 	edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm);  in get_memory_layout()
648 	edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tohm);  in get_memory_layout()
671 		edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",  in get_memory_layout()
687 			edac_dbg(0, "SAD#%d, interleave #%d: %d\n",  in get_memory_layout()
705 …edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT:…  in get_memory_layout()
730 			edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",  in get_memory_layout()
755 			edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",  in get_memory_layout()
769 				edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",  in get_memory_layout()
861 		edac_dbg(0, "SAD interleave #%d: %d\n",  in get_memory_error_data()
864 	edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",  in get_memory_error_data()
892 	edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",  in get_memory_error_data()
980 …edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (off…  in get_memory_error_data()
1025 		edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",  in get_memory_error_data()
1050 	edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",  in get_memory_error_data()
1072 	edac_dbg(0, "\n");  in sbridge_put_devices()
1077 		edac_dbg(0, "Removing dev %02x:%02x.%d\n",  in sbridge_put_devices()
1185 	edac_dbg(0, "Detected dev %02x:%d.%d PCI ID %04x:%04x\n",  in sbridge_get_onedevice()
1304 		edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",  in mci_bind_devs()
1450 	edac_dbg(0, "%s\n", msg);  in sbridge_mce_output_error()
1597 		edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);  in sbridge_unregister_mci()
1605 	edac_dbg(0, "MC: mci = %p, dev = %p\n",  in sbridge_unregister_mci()
1611 	edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);  in sbridge_unregister_mci()
1642 	edac_dbg(0, "MC: mci = %p, dev = %p\n",  in sbridge_register_mci()
1678 		edac_dbg(0, "MC: failed edac_mc_add_mc()\n");  in sbridge_register_mci()
1724 		edac_dbg(0, "Registering MC#%d (%d of %d)\n",  in sbridge_probe()
1755 	edac_dbg(0, "\n");  in sbridge_remove()
1804 	edac_dbg(2, "\n");  in sbridge_init()
1828 	edac_dbg(2, "\n");  in sbridge_exit()