889 		temp = REG_READ(map->dpll);  in cdv_intel_crtc_dpms()
891 			REG_WRITE(map->dpll, temp);  in cdv_intel_crtc_dpms()
892 			REG_READ(map->dpll);  in cdv_intel_crtc_dpms()
895 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in cdv_intel_crtc_dpms()
896 			REG_READ(map->dpll);  in cdv_intel_crtc_dpms()
899 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in cdv_intel_crtc_dpms()
900 			REG_READ(map->dpll);  in cdv_intel_crtc_dpms()
975 		temp = REG_READ(map->dpll);  in cdv_intel_crtc_dpms()
977 			REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);  in cdv_intel_crtc_dpms()
978 			REG_READ(map->dpll);  in cdv_intel_crtc_dpms()
1039 	u32 dpll = 0, dspcntr, pipeconf;  in cdv_intel_crtc_mode_set()  local
1120 	dpll = DPLL_VGA_MODE_DIS;  in cdv_intel_crtc_mode_set()
1124 		dpll |= 3;  in cdv_intel_crtc_mode_set()
1137 	dpll |= DPLL_SYNCLOCK_ENABLE;  in cdv_intel_crtc_mode_set()
1183 	REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);  in cdv_intel_crtc_mode_set()
1184 	REG_READ(map->dpll);  in cdv_intel_crtc_mode_set()
1219 	dpll |= DPLL_VCO_ENABLE;  in cdv_intel_crtc_mode_set()
1228 	REG_WRITE(map->dpll,  in cdv_intel_crtc_mode_set()
1229 		(REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);  in cdv_intel_crtc_mode_set()
1230 	REG_READ(map->dpll);  in cdv_intel_crtc_mode_set()
1234 	if (!(REG_READ(map->dpll) & DPLL_LOCK)) {  in cdv_intel_crtc_mode_set()
1307 	crtc_state->saveDPLL = REG_READ(map->dpll);  in cdv_intel_crtc_save()
1371 		REG_READ(map->dpll),  in cdv_intel_crtc_restore()
1406 		REG_WRITE(map->dpll,  in cdv_intel_crtc_restore()
1408 		REG_READ(map->dpll);  in cdv_intel_crtc_restore()
1410 				REG_READ(map->dpll));  in cdv_intel_crtc_restore()
1420 	REG_WRITE(map->dpll, crtc_state->saveDPLL);  in cdv_intel_crtc_restore()
1421 	REG_READ(map->dpll);  in cdv_intel_crtc_restore()
1631 	u32 dpll;  in cdv_intel_crtc_clock_get()  local
1638 		dpll = REG_READ(map->dpll);  in cdv_intel_crtc_clock_get()
1639 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in cdv_intel_crtc_clock_get()
1646 		dpll = p->dpll;  in cdv_intel_crtc_clock_get()
1647 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in cdv_intel_crtc_clock_get()
1662 		    ffs((dpll &  in cdv_intel_crtc_clock_get()
1667 			dev_err(dev->dev, "PLL %d\n", dpll);  in cdv_intel_crtc_clock_get()
1671 		if ((dpll & PLL_REF_INPUT_MASK) ==  in cdv_intel_crtc_clock_get()
1678 		if (dpll & PLL_P1_DIVIDE_BY_TWO)  in cdv_intel_crtc_clock_get()
1682 			    ((dpll &  in cdv_intel_crtc_clock_get()
1686 		if (dpll & PLL_P2_DIVIDE_BY_4)  in cdv_intel_crtc_clock_get()