187 		temp = REG_READ(map->dpll);  in oaktrail_crtc_dpms()
189 			REG_WRITE(map->dpll, temp);  in oaktrail_crtc_dpms()
190 			REG_READ(map->dpll);  in oaktrail_crtc_dpms()
193 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in oaktrail_crtc_dpms()
194 			REG_READ(map->dpll);  in oaktrail_crtc_dpms()
197 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in oaktrail_crtc_dpms()
198 			REG_READ(map->dpll);  in oaktrail_crtc_dpms()
247 		temp = REG_READ(map->dpll);  in oaktrail_crtc_dpms()
249 			REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);  in oaktrail_crtc_dpms()
250 			REG_READ(map->dpll);  in oaktrail_crtc_dpms()
301 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;  in oaktrail_crtc_mode_set()  local
423 	dpll = 0;		/*BIT16 = 0 for 100MHz reference */  in oaktrail_crtc_mode_set()
437 	dpll |= DPLL_VGA_MODE_DIS;  in oaktrail_crtc_mode_set()
440 	dpll |= DPLL_VCO_ENABLE;  in oaktrail_crtc_mode_set()
443 		dpll |= DPLLA_MODE_LVDS;  in oaktrail_crtc_mode_set()
445 		dpll |= DPLLB_MODE_DAC_SERIAL;  in oaktrail_crtc_mode_set()
451 		dpll |= DPLL_DVO_HIGH_SPEED;  in oaktrail_crtc_mode_set()
452 		dpll |=  in oaktrail_crtc_mode_set()
459 	dpll |= (1 << (clock.p1 - 2)) << 17;  in oaktrail_crtc_mode_set()
461 	dpll |= DPLL_VCO_ENABLE;  in oaktrail_crtc_mode_set()
465 	if (dpll & DPLL_VCO_ENABLE) {  in oaktrail_crtc_mode_set()
467 		REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);  in oaktrail_crtc_mode_set()
468 		REG_READ(map->dpll);  in oaktrail_crtc_mode_set()
474 	REG_WRITE(map->dpll, dpll);  in oaktrail_crtc_mode_set()
475 	REG_READ(map->dpll);  in oaktrail_crtc_mode_set()
480 	REG_WRITE(map->dpll, dpll);  in oaktrail_crtc_mode_set()
481 	REG_READ(map->dpll);  in oaktrail_crtc_mode_set()