182 	    (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {  in psb_intel_find_best_PLL()
189 		if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==  in psb_intel_find_best_PLL()
273 	dspcntr = REG_READ(map->cntr);  in psb_intel_pipe_set_base()
299 	REG_READ(map->base);  in psb_intel_pipe_set_base()
334 		temp = REG_READ(map->dpll);  in psb_intel_crtc_dpms()
337 			REG_READ(map->dpll);  in psb_intel_crtc_dpms()
341 			REG_READ(map->dpll);  in psb_intel_crtc_dpms()
345 			REG_READ(map->dpll);  in psb_intel_crtc_dpms()
351 		temp = REG_READ(map->conf);  in psb_intel_crtc_dpms()
356 		temp = REG_READ(map->cntr);  in psb_intel_crtc_dpms()
361 			REG_WRITE(map->base, REG_READ(map->base));  in psb_intel_crtc_dpms()
379 		temp = REG_READ(map->cntr);  in psb_intel_crtc_dpms()
384 			REG_WRITE(map->base, REG_READ(map->base));  in psb_intel_crtc_dpms()
385 			REG_READ(map->base);  in psb_intel_crtc_dpms()
389 		temp = REG_READ(map->conf);  in psb_intel_crtc_dpms()
392 			REG_READ(map->conf);  in psb_intel_crtc_dpms()
398 		temp = REG_READ(map->dpll);  in psb_intel_crtc_dpms()
401 			REG_READ(map->dpll);  in psb_intel_crtc_dpms()
465 	pfit_control = REG_READ(PFIT_CONTROL);  in psb_intel_panel_fitter_pipe()
571 	pipeconf = REG_READ(map->conf);  in psb_intel_crtc_mode_set()
595 		REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
604 		u32 lvds = REG_READ(LVDS);  in psb_intel_crtc_mode_set()
625 		REG_READ(LVDS);  in psb_intel_crtc_mode_set()
630 	REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
637 	REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
662 	REG_READ(map->conf);  in psb_intel_crtc_mode_set()
742 	crtc_state->saveDSPCNTR = REG_READ(map->cntr);  in psb_intel_crtc_save()
743 	crtc_state->savePIPECONF = REG_READ(map->conf);  in psb_intel_crtc_save()
744 	crtc_state->savePIPESRC = REG_READ(map->src);  in psb_intel_crtc_save()
745 	crtc_state->saveFP0 = REG_READ(map->fp0);  in psb_intel_crtc_save()
746 	crtc_state->saveFP1 = REG_READ(map->fp1);  in psb_intel_crtc_save()
747 	crtc_state->saveDPLL = REG_READ(map->dpll);  in psb_intel_crtc_save()
748 	crtc_state->saveHTOTAL = REG_READ(map->htotal);  in psb_intel_crtc_save()
749 	crtc_state->saveHBLANK = REG_READ(map->hblank);  in psb_intel_crtc_save()
750 	crtc_state->saveHSYNC = REG_READ(map->hsync);  in psb_intel_crtc_save()
751 	crtc_state->saveVTOTAL = REG_READ(map->vtotal);  in psb_intel_crtc_save()
752 	crtc_state->saveVBLANK = REG_READ(map->vblank);  in psb_intel_crtc_save()
753 	crtc_state->saveVSYNC = REG_READ(map->vsync);  in psb_intel_crtc_save()
754 	crtc_state->saveDSPSTRIDE = REG_READ(map->stride);  in psb_intel_crtc_save()
757 	crtc_state->saveDSPSIZE = REG_READ(map->size);  in psb_intel_crtc_save()
758 	crtc_state->saveDSPPOS = REG_READ(map->pos);  in psb_intel_crtc_save()
760 	crtc_state->saveDSPBASE = REG_READ(map->base);  in psb_intel_crtc_save()
764 		crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));  in psb_intel_crtc_save()
788 		REG_READ(map->dpll);  in psb_intel_crtc_restore()
793 	REG_READ(map->fp0);  in psb_intel_crtc_restore()
796 	REG_READ(map->fp1);  in psb_intel_crtc_restore()
799 	REG_READ(map->dpll);  in psb_intel_crtc_restore()
1030 		dpll = REG_READ(map->dpll);  in psb_intel_crtc_clock_get()
1032 			fp = REG_READ(map->fp0);  in psb_intel_crtc_clock_get()
1034 			fp = REG_READ(map->fp1);  in psb_intel_crtc_clock_get()
1035 		is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);  in psb_intel_crtc_clock_get()
1107 		htot = REG_READ(map->htotal);  in psb_intel_crtc_mode_get()
1108 		hsync = REG_READ(map->hsync);  in psb_intel_crtc_mode_get()
1109 		vtot = REG_READ(map->vtotal);  in psb_intel_crtc_mode_get()
1110 		vsync = REG_READ(map->vsync);  in psb_intel_crtc_mode_get()