334 		temp = REG_READ(map->dpll);  in psb_intel_crtc_dpms()
336 			REG_WRITE(map->dpll, temp);  in psb_intel_crtc_dpms()
337 			REG_READ(map->dpll);  in psb_intel_crtc_dpms()
340 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in psb_intel_crtc_dpms()
341 			REG_READ(map->dpll);  in psb_intel_crtc_dpms()
344 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in psb_intel_crtc_dpms()
345 			REG_READ(map->dpll);  in psb_intel_crtc_dpms()
398 		temp = REG_READ(map->dpll);  in psb_intel_crtc_dpms()
400 			REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);  in psb_intel_crtc_dpms()
401 			REG_READ(map->dpll);  in psb_intel_crtc_dpms()
488 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;  in psb_intel_crtc_mode_set()  local
532 	dpll = DPLL_VGA_MODE_DIS;  in psb_intel_crtc_mode_set()
534 		dpll |= DPLLB_MODE_LVDS;  in psb_intel_crtc_mode_set()
535 		dpll |= DPLL_DVO_HIGH_SPEED;  in psb_intel_crtc_mode_set()
537 		dpll |= DPLLB_MODE_DAC_SERIAL;  in psb_intel_crtc_mode_set()
541 		dpll |= DPLL_DVO_HIGH_SPEED;  in psb_intel_crtc_mode_set()
542 		dpll |=  in psb_intel_crtc_mode_set()
547 	dpll |= (1 << (clock.p1 - 1)) << 16;  in psb_intel_crtc_mode_set()
550 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;  in psb_intel_crtc_mode_set()
553 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;  in psb_intel_crtc_mode_set()
556 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;  in psb_intel_crtc_mode_set()
559 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;  in psb_intel_crtc_mode_set()
566 		dpll |= 3;  in psb_intel_crtc_mode_set()
568 	dpll |= PLL_REF_INPUT_DREFCLK;  in psb_intel_crtc_mode_set()
583 	dpll |= DPLL_VCO_ENABLE;  in psb_intel_crtc_mode_set()
592 	if (dpll & DPLL_VCO_ENABLE) {  in psb_intel_crtc_mode_set()
594 		REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);  in psb_intel_crtc_mode_set()
595 		REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
629 	REG_WRITE(map->dpll, dpll);  in psb_intel_crtc_mode_set()
630 	REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
635 	REG_WRITE(map->dpll, dpll);  in psb_intel_crtc_mode_set()
637 	REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
747 	crtc_state->saveDPLL = REG_READ(map->dpll);  in psb_intel_crtc_save()
786 		REG_WRITE(map->dpll,  in psb_intel_crtc_restore()
788 		REG_READ(map->dpll);  in psb_intel_crtc_restore()
798 	REG_WRITE(map->dpll, crtc_state->saveDPLL);  in psb_intel_crtc_restore()
799 	REG_READ(map->dpll);  in psb_intel_crtc_restore()
1023 	u32 dpll;  in psb_intel_crtc_clock_get()  local
1030 		dpll = REG_READ(map->dpll);  in psb_intel_crtc_clock_get()
1031 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in psb_intel_crtc_clock_get()
1038 		dpll = p->dpll;  in psb_intel_crtc_clock_get()
1040 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in psb_intel_crtc_clock_get()
1055 		    ffs((dpll &  in psb_intel_crtc_clock_get()
1060 		if ((dpll & PLL_REF_INPUT_MASK) ==  in psb_intel_crtc_clock_get()
1067 		if (dpll & PLL_P1_DIVIDE_BY_TWO)  in psb_intel_crtc_clock_get()
1071 			    ((dpll &  in psb_intel_crtc_clock_get()
1075 		if (dpll & PLL_P2_DIVIDE_BY_4)  in psb_intel_crtc_clock_get()