Lines Matching refs:INTEL_VGA_DEVICE
134 #define INTEL_VGA_DEVICE(id, info) { \ macro
320 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
321 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
322 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
323 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
324 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
325 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
326 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
327 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
328 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
329 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
330 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
331 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
332 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
333 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
334 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
335 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
336 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
337 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
338 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
339 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
340 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
341 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
342 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
343 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
344 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
345 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
346 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
347 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
348 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
349 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
350 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
351 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
352 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
353 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
354 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
355 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
356 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
357 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
358 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
359 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
360 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
361 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
362 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
364 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
365 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
366 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
367 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
368 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
369 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
370 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
371 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
372 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
373 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
374 INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
375 INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
376 INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
377 INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
378 INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
379 INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
380 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
381 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
382 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
383 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
384 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
385 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
386 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
387 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
388 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
389 INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
390 INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
391 INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
392 INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
393 INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
394 INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
395 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
396 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
397 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
398 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
399 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
400 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
401 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
402 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
403 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
404 INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
405 INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
406 INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
407 INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
408 INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
409 INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
410 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
411 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
412 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
413 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
414 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
415 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
416 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
417 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
418 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
419 INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
420 INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
421 INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
422 INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
423 INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
424 INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
425 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
426 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
427 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
428 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
429 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
430 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),