Lines Matching refs:regfile
73 dev_priv->regfile.saveVGA0 = I915_READ(VGA0); in i915_save_vga()
74 dev_priv->regfile.saveVGA1 = I915_READ(VGA1); in i915_save_vga()
75 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD); in i915_save_vga()
76 dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev)); in i915_save_vga()
79 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK); in i915_save_vga()
82 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ); in i915_save_vga()
83 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) { in i915_save_vga()
98 dev_priv->regfile.saveCR[i] = in i915_save_vga()
101 dev_priv->regfile.saveCR[0x11] &= ~0x80; in i915_save_vga()
105 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX); in i915_save_vga()
107 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0); in i915_save_vga()
109 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX); in i915_save_vga()
114 dev_priv->regfile.saveGR[i] = in i915_save_vga()
117 dev_priv->regfile.saveGR[0x10] = in i915_save_vga()
119 dev_priv->regfile.saveGR[0x11] = in i915_save_vga()
121 dev_priv->regfile.saveGR[0x18] = in i915_save_vga()
126 dev_priv->regfile.saveSR[i] = in i915_save_vga()
137 I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL); in i915_restore_vga()
139 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0); in i915_restore_vga()
140 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1); in i915_restore_vga()
141 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD); in i915_restore_vga()
146 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR); in i915_restore_vga()
147 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) { in i915_restore_vga()
160 dev_priv->regfile.saveSR[i]); in i915_restore_vga()
164 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]); in i915_restore_vga()
166 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]); in i915_restore_vga()
171 dev_priv->regfile.saveGR[i]); in i915_restore_vga()
174 dev_priv->regfile.saveGR[0x10]); in i915_restore_vga()
176 dev_priv->regfile.saveGR[0x11]); in i915_restore_vga()
178 dev_priv->regfile.saveGR[0x18]); in i915_restore_vga()
183 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0); in i915_restore_vga()
185 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20); in i915_restore_vga()
189 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK); in i915_restore_vga()
198 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
207 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); in i915_save_display()
208 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); in i915_save_display()
209 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); in i915_save_display()
210 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL); in i915_save_display()
211 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2); in i915_save_display()
213 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); in i915_save_display()
215 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); in i915_save_display()
216 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); in i915_save_display()
217 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); in i915_save_display()
218 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL); in i915_save_display()
220 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); in i915_save_display()
222 dev_priv->regfile.saveLVDS = I915_READ(LVDS); in i915_save_display()
226 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL); in i915_save_display()
229 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); in i915_save_display()
230 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); in i915_save_display()
231 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); in i915_save_display()
233 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); in i915_save_display()
234 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); in i915_save_display()
235 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR); in i915_save_display()
241 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE); in i915_save_display()
243 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE); in i915_save_display()
245 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); in i915_save_display()
246 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); in i915_save_display()
247 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); in i915_save_display()
248 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); in i915_save_display()
263 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()
270 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2); in i915_restore_display()
276 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); in i915_restore_display()
278 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); in i915_restore_display()
281 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL); in i915_restore_display()
284 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL); in i915_restore_display()
285 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2); in i915_restore_display()
289 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2); in i915_restore_display()
290 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL); in i915_restore_display()
291 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); in i915_restore_display()
292 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); in i915_restore_display()
293 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); in i915_restore_display()
294 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); in i915_restore_display()
296 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY); in i915_restore_display()
298 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS); in i915_restore_display()
299 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL); in i915_restore_display()
300 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL); in i915_restore_display()
301 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); in i915_restore_display()
302 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); in i915_restore_display()
303 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); in i915_restore_display()
304 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL); in i915_restore_display()
311 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE); in i915_restore_display()
313 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE); in i915_restore_display()
315 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE); in i915_restore_display()
316 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE); in i915_restore_display()
317 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2); in i915_restore_display()
318 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); in i915_restore_display()
333 pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB); in i915_save_state()
342 dev_priv->regfile.saveDEIER = I915_READ(DEIER); in i915_save_state()
343 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR); in i915_save_state()
344 dev_priv->regfile.saveGTIER = I915_READ(GTIER); in i915_save_state()
345 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR); in i915_save_state()
346 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR); in i915_save_state()
347 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR); in i915_save_state()
348 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY = in i915_save_state()
350 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG); in i915_save_state()
352 dev_priv->regfile.saveIER = I915_READ(IER); in i915_save_state()
353 dev_priv->regfile.saveIMR = I915_READ(IMR); in i915_save_state()
360 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); in i915_save_state()
363 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); in i915_save_state()
367 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2)); in i915_save_state()
368 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2)); in i915_save_state()
371 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2)); in i915_save_state()
383 pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB); in i915_restore_state()
393 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER); in i915_restore_state()
394 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR); in i915_restore_state()
395 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER); in i915_restore_state()
396 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR); in i915_restore_state()
397 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR); in i915_restore_state()
398 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR); in i915_restore_state()
399 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG); in i915_restore_state()
401 I915_WRITE(IER, dev_priv->regfile.saveIER); in i915_restore_state()
402 I915_WRITE(IMR, dev_priv->regfile.saveIMR); in i915_restore_state()
407 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000); in i915_restore_state()
410 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); in i915_restore_state()
413 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]); in i915_restore_state()
414 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]); in i915_restore_state()
417 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]); in i915_restore_state()