74 	tmp = I915_READ(crt->adpa_reg);  in intel_crt_get_hw_state()
96 	temp = I915_READ(crt->adpa_reg);  in intel_crt_set_dpms()
267 		save_adpa = adpa = I915_READ(crt->adpa_reg);  in intel_ironlake_crt_detect_hotplug()
276 		if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,  in intel_ironlake_crt_detect_hotplug()
287 	adpa = I915_READ(crt->adpa_reg);  in intel_ironlake_crt_detect_hotplug()
306 	save_adpa = adpa = I915_READ(crt->adpa_reg);  in valleyview_crt_detect_hotplug()
313 	if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,  in valleyview_crt_detect_hotplug()
320 	adpa = I915_READ(crt->adpa_reg);  in valleyview_crt_detect_hotplug()
365 	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);  in intel_crt_detect_hotplug()
372 		if (wait_for((I915_READ(PORT_HOTPLUG_EN) &  in intel_crt_detect_hotplug()
378 	stat = I915_READ(PORT_HOTPLUG_STAT);  in intel_crt_detect_hotplug()
490 	save_bclrpat = I915_READ(bclrpat_reg);  in intel_crt_load_detect()
491 	save_vtotal = I915_READ(vtotal_reg);  in intel_crt_load_detect()
492 	vblank = I915_READ(vblank_reg);  in intel_crt_load_detect()
504 		uint32_t pipeconf = I915_READ(pipeconf_reg);  in intel_crt_load_detect()
525 			uint32_t vsync = I915_READ(vsync_reg);  in intel_crt_load_detect()
543 		while (I915_READ(pipe_dsl_reg) >= vactive)  in intel_crt_load_detect()
545 		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)  in intel_crt_load_detect()
558 		} while ((I915_READ(pipe_dsl_reg) == dsl));  in intel_crt_load_detect()
666 		adpa = I915_READ(crt->adpa_reg);  in intel_crt_reset()
807 		dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;  in intel_crt_init()