488 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {  in intel_ironlake_limit()
514 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {  in intel_g4x_limit()
542 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))  in intel_limit()
554 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))  in intel_limit()
559 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))  in intel_limit()
648 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {  in intel_find_best_PLL()
714 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {  in intel_g4x_find_best_PLL()
3344 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {  in ironlake_crtc_enable()
3367 	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||  in ironlake_crtc_enable()
4137 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {  in vlv_get_refclk()
4157 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&  in i9xx_get_refclk()
4219 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&  in i9xx_update_pll_dividers()
4353 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))  in i9xx_update_pll()
4400 	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&  in i9xx_update_pll()
4460 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {  in i8xx_update_pll()
4471 	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&  in i8xx_update_pll()
4650 		case INTEL_OUTPUT_LVDS:  in i9xx_crtc_mode_set()
4791 		case INTEL_OUTPUT_LVDS:  in ironlake_init_pch_refclk()
5111 		case INTEL_OUTPUT_LVDS:  in ironlake_get_refclk()
5283 		case INTEL_OUTPUT_LVDS:  in ironlake_compute_clocks()
5508 		case INTEL_OUTPUT_LVDS:  in ironlake_compute_dpll()
5615 		case INTEL_OUTPUT_LVDS:  in ironlake_crtc_mode_set()