Lines Matching refs:I915_READ
61 fbc_ctl = I915_READ(FBC_CONTROL); in i8xx_disable_fbc()
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { in i8xx_disable_fbc()
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; in i8xx_fbc_enabled()
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); in g4x_enable_fbc()
160 dpfc_ctl = I915_READ(DPFC_CONTROL); in g4x_disable_fbc()
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; in g4x_fbc_enabled()
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); in sandybridge_blit_fbc_update()
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); in ironlake_enable_fbc()
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); in ironlake_disable_fbc()
253 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; in ironlake_fbc_enabled()
546 tmp = I915_READ(CLKCFG); in i915_pineview_get_mem_freq()
576 tmp = I915_READ(CSHRDDR3CTL); in i915_pineview_get_mem_freq()
715 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); in pineview_disable_cxsr()
737 uint32_t dsparb = I915_READ(DSPARB); in i9xx_get_fifo_size()
753 uint32_t dsparb = I915_READ(DSPARB); in i85x_get_fifo_size()
770 uint32_t dsparb = I915_READ(DSPARB); in i845_get_fifo_size()
786 uint32_t dsparb = I915_READ(DSPARB); in i830_get_fifo_size()
1040 reg = I915_READ(DSPFW1); in pineview_update_wm()
1050 reg = I915_READ(DSPFW3); in pineview_update_wm()
1059 reg = I915_READ(DSPFW3); in pineview_update_wm()
1068 reg = I915_READ(DSPFW3); in pineview_update_wm()
1076 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); in pineview_update_wm()
1330 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); in valleyview_update_wm()
1345 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | in valleyview_update_wm()
1348 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | in valleyview_update_wm()
1381 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); in g4x_update_wm()
1396 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | in g4x_update_wm()
1400 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | in g4x_update_wm()
1454 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) in i965_update_wm()
1529 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); in i9xx_update_wm()
1579 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); in i9xx_update_wm()
1600 fwater_lo = I915_READ(FW_BLC) & ~0xfff; in i830_update_wm()
1634 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); in ironlake_check_srwm()
1808 val = I915_READ(WM0_PIPEA_ILK); in sandybridge_update_wm()
1822 val = I915_READ(WM0_PIPEB_ILK); in sandybridge_update_wm()
1911 val = I915_READ(WM0_PIPEA_ILK); in ivybridge_update_wm()
1925 val = I915_READ(WM0_PIPEB_ILK); in ivybridge_update_wm()
1939 val = I915_READ(WM0_PIPEC_IVB); in ivybridge_update_wm()
2026 temp = I915_READ(PIPE_WM_LINETIME(pipe)); in haswell_update_linetime_wm()
2154 val = I915_READ(reg); in sandybridge_update_sprite_wm()
2331 u32 rgvmodectl = I915_READ(MEMMODECTL); in ironlake_enable_drps()
2337 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); in ironlake_enable_drps()
2338 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); in ironlake_enable_drps()
2356 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> in ironlake_enable_drps()
2381 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) in ironlake_enable_drps()
2387 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + in ironlake_enable_drps()
2388 I915_READ(0x112e0); in ironlake_enable_drps()
2390 dev_priv->ips.last_count2 = I915_READ(0x112f4); in ironlake_enable_drps()
2406 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); in ironlake_disable_drps()
2408 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); in ironlake_disable_drps()
2410 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); in ironlake_disable_drps()
2501 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); in gen6_disable_rps()
2551 if ((gtfifodbg = I915_READ(GTFIFODBG))) { in gen6_enable_rps()
2558 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); in gen6_enable_rps()
2559 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); in gen6_enable_rps()
2704 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK); in gen6_update_ring_freq()
2766 if (I915_READ(PWRCTXA)) { in ironlake_disable_rc6()
2768 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); in ironlake_disable_rc6()
2769 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), in ironlake_disable_rc6()
2775 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); in ironlake_disable_rc6()
2858 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); in ironlake_enable_rc6()
2909 count1 = I915_READ(DMIEC); in __i915_chipset_val()
2910 count2 = I915_READ(DDREC); in __i915_chipset_val()
2911 count3 = I915_READ(CSIEC); in __i915_chipset_val()
2965 tsfs = I915_READ(TSFS); in i915_mch_val()
3133 count = I915_READ(GFXEC); in __i915_update_gfx_val()
3170 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); in __i915_gfx_val()
3417 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); in intel_init_emon()
3459 lcfuse = I915_READ(LCFUSE02); in intel_init_emon()
3547 (I915_READ(ILK_DISPLAY_CHICKEN2) | in ironlake_init_clock_gating()
3551 (I915_READ(DISP_ARB_CTL) | in ironlake_init_clock_gating()
3566 I915_READ(ILK_DISPLAY_CHICKEN1) | in ironlake_init_clock_gating()
3569 I915_READ(ILK_DISPLAY_CHICKEN2) | in ironlake_init_clock_gating()
3576 I915_READ(ILK_DISPLAY_CHICKEN2) | in ironlake_init_clock_gating()
3601 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | in cpt_init_clock_gating()
3607 val = I915_READ(TRANS_CHICKEN2(pipe)); in cpt_init_clock_gating()
3629 tmp = I915_READ(MCH_SSKPD); in gen6_check_mch_setup()
3646 I915_READ(ILK_DISPLAY_CHICKEN2) | in gen6_init_clock_gating()
3666 I915_READ(GEN6_UCGCTL1) | in gen6_init_clock_gating()
3702 I915_READ(ILK_DISPLAY_CHICKEN1) | in gen6_init_clock_gating()
3705 I915_READ(ILK_DISPLAY_CHICKEN2) | in gen6_init_clock_gating()
3708 I915_READ(ILK_DSPCLK_GATE_D) | in gen6_init_clock_gating()
3713 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | in gen6_init_clock_gating()
3718 I915_READ(DSPCNTR(pipe)) | in gen6_init_clock_gating()
3735 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); in gen7_setup_fixed_func_scheduler()
3759 I915_READ(SOUTH_DSPCLK_GATE_D) | in lpt_init_clock_gating()
3789 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | in haswell_init_clock_gating()
3794 I915_READ(DSPCNTR(pipe)) | in haswell_init_clock_gating()
3806 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | in haswell_init_clock_gating()
3810 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in haswell_init_clock_gating()
3816 I915_READ(WM_DBG) | in haswell_init_clock_gating()
3871 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in ivybridge_init_clock_gating()
3893 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | in ivybridge_init_clock_gating()
3898 I915_READ(DSPCNTR(pipe)) | in ivybridge_init_clock_gating()
3904 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | in ivybridge_init_clock_gating()
3913 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); in ivybridge_init_clock_gating()
3954 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); in valleyview_init_clock_gating()
3958 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in valleyview_init_clock_gating()
3966 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in valleyview_init_clock_gating()
3971 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | in valleyview_init_clock_gating()
3975 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | in valleyview_init_clock_gating()
4006 I915_READ(DSPCNTR(pipe)) | in valleyview_init_clock_gating()
4079 u32 dstate = I915_READ(D_STATE); in gen3_init_clock_gating()
4123 return I915_READ(HSW_PWR_WELL_DRIVER) == in intel_using_power_well()
4141 tmp = I915_READ(HSW_PWR_WELL_DRIVER); in intel_set_power_well()
4151 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & in intel_set_power_well()
4181 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE) in intel_init_power_well()
4216 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) in intel_init_pm()
4528 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { in sandybridge_pcode_read()
4536 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, in sandybridge_pcode_read()
4542 *val = I915_READ(GEN6_PCODE_DATA); in sandybridge_pcode_read()
4552 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { in sandybridge_pcode_write()
4560 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, in sandybridge_pcode_write()
4587 if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) { in vlv_punit_rw()
4599 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, in vlv_punit_rw()
4608 *val = I915_READ(VLV_IOSF_DATA); in vlv_punit_rw()