50 	t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |  in nv40_mem_timing_calc()
52 		    (e->tWTR + 2 + (t->tCWL - 1)) << 8 |  in nv40_mem_timing_calc()
53 		    (e->tCL + 2 - (t->tCWL - 1));  in nv40_mem_timing_calc()
56 		    ((t->tCWL - 1) << 24 |  in nv40_mem_timing_calc()
87 		if (e->tCWL > 0)  in nv50_mem_timing_calc()
88 			t->tCWL = e->tCWL;  in nv50_mem_timing_calc()
96 	t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |  in nv50_mem_timing_calc()
98 				(e->tWTR + 2 + (t->tCWL - 1)) << 8;  in nv50_mem_timing_calc()
100 	t->reg[2] = ((t->tCWL - 1) << 24 |  in nv50_mem_timing_calc()
112 		t->reg[1] |= (e->tCL + 2 - (t->tCWL - 1));  in nv50_mem_timing_calc()
121 		t->reg[6] = (0x33 - t->tCWL) << 16 |  in nv50_mem_timing_calc()
122 			    t->tCWL << 8 |  in nv50_mem_timing_calc()
123 			    (0x2e + e->tCL - t->tCWL);  in nv50_mem_timing_calc()
130 			t->reg[6] |= (t->tCWL - 2) << 8;  in nv50_mem_timing_calc()
134 			t->reg[6] |= t->tCWL << 8;  in nv50_mem_timing_calc()
138 		t->reg[1] |= (5 + e->tCL - (t->tCWL));  in nv50_mem_timing_calc()
149 		t->reg[5] |= (t->tCWL + 6) << 8;  in nv50_mem_timing_calc()
152 			    (6 - e->tCL + t->tCWL) << 8 |  in nv50_mem_timing_calc()
153 			    (0x50 + e->tCL - t->tCWL);  in nv50_mem_timing_calc()
177 	if (e->tCWL > 0)  in nvc0_mem_timing_calc()
178 		t->tCWL = e->tCWL;  in nvc0_mem_timing_calc()
186 		    (t->tCWL << 7) |  in nvc0_mem_timing_calc()
280 	if (e->tCWL < 5) {  in nouveau_mem_ddr3_mr()
281 		NV_WARN(drm, "(%u) Invalid tCWL: %u", t->id, e->tCWL);  in nouveau_mem_ddr3_mr()
294 	t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3;  in nouveau_mem_ddr3_mr()
413 	t->tCWL = boot->tCWL;  in nouveau_mem_timing_calc()
510 	t->tCWL = 0;  in nouveau_mem_timing_read()
512 		t->tCWL = ((nv_rd32(device, 0x100228) & 0x0f000000) >> 24) + 1;  in nouveau_mem_timing_read()
514 		t->tCWL = ((nv_rd32(device, 0x10f294) & 0x00000f80) >> 7);  in nouveau_mem_timing_read()