1205 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1207 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1209 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1211 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1213 	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in dce4_crtc_do_set_base()
1214 	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in dce4_crtc_do_set_base()
1216 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1217 	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1218 	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1219 	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1220 	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);  in dce4_crtc_do_set_base()
1221 	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);  in dce4_crtc_do_set_base()
1224 	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);  in dce4_crtc_do_set_base()
1225 	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);  in dce4_crtc_do_set_base()
1227 	WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1231 	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1235 	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,  in dce4_crtc_do_set_base()
1240 	tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);  in dce4_crtc_do_set_base()
1242 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_crtc_do_set_base()
1245 	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1377 	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1380 	       radeon_crtc->crtc_offset, (u32) fb_location);  in avivo_crtc_do_set_base()
1381 	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);  in avivo_crtc_do_set_base()
1383 		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in avivo_crtc_do_set_base()
1385 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1386 	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1387 	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1388 	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1389 	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);  in avivo_crtc_do_set_base()
1390 	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);  in avivo_crtc_do_set_base()
1393 	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);  in avivo_crtc_do_set_base()
1394 	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);  in avivo_crtc_do_set_base()
1396 	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1400 	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1404 	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,  in avivo_crtc_do_set_base()
1409 	tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);  in avivo_crtc_do_set_base()
1411 	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);  in avivo_crtc_do_set_base()
1414 	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);  in avivo_crtc_do_set_base()
1899 			radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
1902 			radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
1905 			radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
1908 			radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
1911 			radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
1914 			radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;  in radeon_atombios_init_crtc()
1919 			radeon_crtc->crtc_offset =  in radeon_atombios_init_crtc()
1922 			radeon_crtc->crtc_offset = 0;  in radeon_atombios_init_crtc()