1204 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip()  local
1205 	u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);  in evergreen_page_flip()
1210 	WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in evergreen_page_flip()
1213 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1215 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1218 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1220 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1225 …if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDI…  in evergreen_page_flip()
1233 	WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in evergreen_page_flip()
1236 …return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PE…  in evergreen_page_flip()
1463 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_prepare()  local
1468 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_prepare()
1469 		if (radeon_crtc->enabled) {  in evergreen_pm_prepare()
1470 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_prepare()
1472 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_prepare()
1488 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_finish()  local
1493 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_finish()
1494 		if (radeon_crtc->enabled) {  in evergreen_pm_finish()
1495 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_finish()
1497 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_finish()
1717 					struct radeon_crtc *radeon_crtc,  in evergreen_line_buffer_adjust()  argument
1743 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
1752 	if (radeon_crtc->crtc_id % 2)  in evergreen_line_buffer_adjust()
1754 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);  in evergreen_line_buffer_adjust()
1756 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
2035 					 struct radeon_crtc *radeon_crtc,  in evergreen_program_watermarks()  argument
2038 	struct drm_display_mode *mode = &radeon_crtc->base.mode;  in evergreen_program_watermarks()
2046 	u32 pipe_offset = radeon_crtc->crtc_id * 16;  in evergreen_program_watermarks()
2050 	if (radeon_crtc->base.enabled && num_heads && mode) {  in evergreen_program_watermarks()
2065 		wm.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2067 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2096 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2108 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2137 	WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);  in evergreen_program_watermarks()
2138 	WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);  in evergreen_program_watermarks()