2654 	tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);  in r600_uvd_rbc_start()
2658 	tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);  in r600_uvd_rbc_start()
2662 	tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);  in r600_uvd_rbc_start()
2667 	radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));  in r600_uvd_rbc_start()
2670 	radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));  in r600_uvd_rbc_start()
2913 	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));  in r600_uvd_ring_test()
2980 		radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));  in r600_fence_ring_emit()
2991 	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));  in r600_uvd_fence_emit()
2993 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in r600_uvd_fence_emit()
2995 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in r600_uvd_fence_emit()
2997 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in r600_uvd_fence_emit()
3000 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in r600_uvd_fence_emit()
3002 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in r600_uvd_fence_emit()
3004 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in r600_uvd_fence_emit()
3085 	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));  in r600_uvd_semaphore_emit()
3088 	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));  in r600_uvd_semaphore_emit()
3091 	radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));  in r600_uvd_semaphore_emit()
3504 	radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));  in r600_uvd_ib_execute()
3506 	radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));  in r600_uvd_ib_execute()