Lines Matching refs:lobj
1029 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1070 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1072 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset; in r600_cs_check_reg()
1091 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1128 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1131 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1200 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1231 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1267 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1270 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; in r600_cs_check_reg()
1281 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1283 track->db_bo_mc = reloc->lobj.gpu_offset; in r600_cs_check_reg()
1294 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1363 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1372 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1658 offset = reloc->lobj.gpu_offset + in r600_packet3_check()
1699 offset = reloc->lobj.gpu_offset + in r600_packet3_check()
1751 offset = reloc->lobj.gpu_offset + in r600_packet3_check()
1791 offset = reloc->lobj.gpu_offset + tmp; in r600_packet3_check()
1821 offset = reloc->lobj.gpu_offset + tmp; in r600_packet3_check()
1847 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1863 offset = reloc->lobj.gpu_offset + in r600_packet3_check()
1885 offset = reloc->lobj.gpu_offset + in r600_packet3_check()
1950 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1952 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1954 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1964 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1970 reloc->lobj.tiling_flags); in r600_packet3_check()
1994 offset64 = reloc->lobj.gpu_offset + offset; in r600_packet3_check()
2104 ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2137 offset += reloc->lobj.gpu_offset; in r600_packet3_check()
2156 offset += reloc->lobj.gpu_offset; in r600_packet3_check()
2185 offset += reloc->lobj.gpu_offset; in r600_packet3_check()
2210 offset += reloc->lobj.gpu_offset; in r600_packet3_check()
2234 offset += reloc->lobj.gpu_offset; in r600_packet3_check()
2497 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); in r600_dma_cs_parse()
2503 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2504 ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; in r600_dma_cs_parse()
2531 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); in r600_dma_cs_parse()
2535 ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2536 ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; in r600_dma_cs_parse()
2541 ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2542 ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in r600_dma_cs_parse()
2546 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); in r600_dma_cs_parse()
2556 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2557 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2558 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; in r600_dma_cs_parse()
2559 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in r600_dma_cs_parse()
2567 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2568 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2569 ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; in r600_dma_cs_parse()
2570 ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16; in r600_dma_cs_parse()
2602 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2603 ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000; in r600_dma_cs_parse()