Lines Matching refs:tegra_dc_writel
83 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_plane_disable()
87 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_plane_disable()
89 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL); in tegra_plane_disable()
90 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL); in tegra_plane_disable()
146 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_set_base()
151 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); in tegra_dc_set_base()
152 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); in tegra_dc_set_base()
155 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_dc_set_base()
158 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_dc_set_base()
171 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
184 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
202 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
204 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_finish_page_flip()
332 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
335 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
339 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
343 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
347 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
350 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
437 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_setup_window()
439 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
440 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
443 tegra_dc_writel(dc, value, DC_WIN_POSITION); in tegra_dc_setup_window()
446 tegra_dc_writel(dc, value, DC_WIN_SIZE); in tegra_dc_setup_window()
454 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); in tegra_dc_setup_window()
467 tegra_dc_writel(dc, value, DC_WIN_DDA_INC); in tegra_dc_setup_window()
472 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); in tegra_dc_setup_window()
473 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); in tegra_dc_setup_window()
475 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); in tegra_dc_setup_window()
476 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); in tegra_dc_setup_window()
478 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); in tegra_dc_setup_window()
481 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); in tegra_dc_setup_window()
482 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); in tegra_dc_setup_window()
484 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
486 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
489 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); in tegra_dc_setup_window()
490 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); in tegra_dc_setup_window()
496 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); in tegra_dc_setup_window()
497 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); in tegra_dc_setup_window()
498 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); in tegra_dc_setup_window()
499 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); in tegra_dc_setup_window()
500 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); in tegra_dc_setup_window()
501 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); in tegra_dc_setup_window()
502 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); in tegra_dc_setup_window()
503 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); in tegra_dc_setup_window()
510 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); in tegra_dc_setup_window()
516 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); in tegra_dc_setup_window()
517 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); in tegra_dc_setup_window()
521 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
522 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
523 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
527 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
528 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
529 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
533 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); in tegra_dc_setup_window()
534 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); in tegra_dc_setup_window()
535 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); in tegra_dc_setup_window()
539 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL); in tegra_dc_setup_window()
540 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL); in tegra_dc_setup_window()
597 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_crtc_mode_set()
602 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_crtc_mode_set()
606 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL); in tegra_crtc_mode_set()
608 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS); in tegra_crtc_mode_set()
611 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_crtc_mode_set()
659 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_crtc_prepare()
660 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_crtc_prepare()
663 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_prepare()
667 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_prepare()
671 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_prepare()
675 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_prepare()
680 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_crtc_prepare()
684 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_crtc_prepare()
687 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_prepare()
690 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_prepare()
699 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_commit()
702 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_commit()
727 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()