220 	reg = in_be32((void __iomem *)cckctrl_port);  in scc_set_pio_mode()
227 	out_be32((void __iomem *)piosht_port, reg);  in scc_set_pio_mode()
229 	out_be32((void __iomem *)pioct_port, reg);  in scc_set_pio_mode()
258 	reg = in_be32((void __iomem *)cckctrl_port);  in scc_set_dma_mode()
269 		out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);  in scc_set_dma_mode()
270 		out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);  in scc_set_dma_mode()
272 …out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | …  in scc_set_dma_mode()
274 		out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);  in scc_set_dma_mode()
275 		out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);  in scc_set_dma_mode()
276 …out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) |…  in scc_set_dma_mode()
279 	out_be32((void __iomem *)udenvt_port, reg);  in scc_set_dma_mode()
319 	out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);  in scc_dma_setup()
322 	out_be32((void __iomem *)hwif->dma_base, rw);  in scc_dma_setup()
328 	out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6);  in scc_dma_setup()
370 	void __iomem *dma_base = (void __iomem *)hwif->dma_base;  in scc_dma_end()
378 	if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)  in scc_dma_end()
381 		reg = in_be32((void __iomem *)intsts_port);  in scc_dma_end()
404 		reg = in_be32((void __iomem *)intsts_port);  in scc_dma_end()
408 			out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);  in scc_dma_end()
418 			maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));  in scc_dma_end()
419 			maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));  in scc_dma_end()
423 			out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);  in scc_dma_end()
431 			out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);  in scc_dma_end()
441 			out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);  in scc_dma_end()
447 			out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);  in scc_dma_end()
454 			out_be32((void __iomem *)intsts_port, INTSTS_BMHE);  in scc_dma_end()
459 			out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);  in scc_dma_end()
464 			out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);  in scc_dma_end()
480 	u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);  in scc_dma_test_irq()
483 	if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)  in scc_dma_test_irq()
519 	void __iomem *ctl_addr;  in setup_mmio_scc()
520 	void __iomem *dma_addr;  in setup_mmio_scc()
772 	out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);  in init_hwif_scc()
774 	if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)  in init_hwif_scc()