Lines Matching refs:dd
157 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ argument
159 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \ argument
681 static inline void qib_write_kreg(const struct qib_devdata *dd,
700 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, in qib_read_ureg32() argument
703 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg32()
706 (dd->ureg_align * ctxt) + (dd->userbase ? in qib_read_ureg32()
707 (char __iomem *)dd->userbase : in qib_read_ureg32()
708 (char __iomem *)dd->kregbase + dd->uregbase))); in qib_read_ureg32()
721 static inline u64 qib_read_ureg(const struct qib_devdata *dd, in qib_read_ureg() argument
725 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg()
728 (dd->ureg_align * ctxt) + (dd->userbase ? in qib_read_ureg()
729 (char __iomem *)dd->userbase : in qib_read_ureg()
730 (char __iomem *)dd->kregbase + dd->uregbase))); in qib_read_ureg()
742 static inline void qib_write_ureg(const struct qib_devdata *dd, in qib_write_ureg() argument
746 if (dd->userbase) in qib_write_ureg()
748 ((char __iomem *) dd->userbase + in qib_write_ureg()
749 dd->ureg_align * ctxt); in qib_write_ureg()
752 (dd->uregbase + in qib_write_ureg()
753 (char __iomem *) dd->kregbase + in qib_write_ureg()
754 dd->ureg_align * ctxt); in qib_write_ureg()
756 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_ureg()
760 static inline u32 qib_read_kreg32(const struct qib_devdata *dd, in qib_read_kreg32() argument
763 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg32()
765 return readl((u32 __iomem *) &dd->kregbase[regno]); in qib_read_kreg32()
768 static inline u64 qib_read_kreg64(const struct qib_devdata *dd, in qib_read_kreg64() argument
771 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg64()
773 return readq(&dd->kregbase[regno]); in qib_read_kreg64()
776 static inline void qib_write_kreg(const struct qib_devdata *dd, in qib_write_kreg() argument
779 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_kreg()
780 writeq(value, &dd->kregbase[regno]); in qib_write_kreg()
790 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT)) in qib_read_kreg_port()
798 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase && in qib_write_kreg_port()
799 (ppd->dd->flags & QIB_PRESENT)) in qib_write_kreg_port()
810 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, in qib_write_kreg_ctxt() argument
814 qib_write_kreg(dd, regno + ctxt, value); in qib_write_kreg_ctxt()
817 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno) in read_7322_creg() argument
819 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg()
821 return readq(&dd->cspec->cregbase[regno]); in read_7322_creg()
826 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno) in read_7322_creg32() argument
828 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg32()
830 return readl(&dd->cspec->cregbase[regno]); in read_7322_creg32()
839 (ppd->dd->flags & QIB_PRESENT)) in write_7322_creg_port()
847 !(ppd->dd->flags & QIB_PRESENT)) in read_7322_creg_port()
856 !(ppd->dd->flags & QIB_PRESENT)) in read_7322_creg32_port()
1273 struct qib_devdata *dd = ppd->dd; in qib_disarm_7322_senderrbufs() local
1276 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; in qib_disarm_7322_senderrbufs()
1286 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i); in qib_disarm_7322_senderrbufs()
1289 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]); in qib_disarm_7322_senderrbufs()
1294 qib_disarm_piobufs_set(dd, sbuf, piobcnt); in qib_disarm_7322_senderrbufs()
1351 struct qib_devdata *dd = ppd->dd; in flush_fifo() local
1382 if (dd->flags & QIB_PIO_FLUSH_WC) { in flush_fifo()
1390 qib_sendbuf_done(dd, bufn); in flush_fifo()
1398 struct qib_devdata *dd = ppd->dd; in qib_7322_sdma_sendctrl() local
1426 spin_lock(&dd->sendctrl_lock); in qib_7322_sdma_sendctrl()
1432 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_sdma_sendctrl()
1444 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_sdma_sendctrl()
1449 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_sdma_sendctrl()
1452 spin_unlock(&dd->sendctrl_lock); in qib_7322_sdma_sendctrl()
1454 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) in qib_7322_sdma_sendctrl()
1522 struct qib_devdata *dd = ppd->dd; in sdma_7322_p_errors() local
1527 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit, in sdma_7322_p_errors()
1572 static noinline void handle_7322_errors(struct qib_devdata *dd) in handle_7322_errors() argument
1581 errs = qib_read_kreg64(dd, kr_errstatus); in handle_7322_errors()
1583 qib_devinfo(dd->pcidev, in handle_7322_errors()
1589 errs &= dd->cspec->errormask; in handle_7322_errors()
1590 msg = dd->cspec->emsgbuf; in handle_7322_errors()
1595 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf); in handle_7322_errors()
1598 if (errs & dd->eep_st_masks[log_idx].errs_to_log) in handle_7322_errors()
1599 qib_inc_eeprom_err(dd, log_idx, 1); in handle_7322_errors()
1602 qib_disarm_7322_senderrbufs(dd->pport); in handle_7322_errors()
1608 qib_disarm_7322_senderrbufs(dd->pport); in handle_7322_errors()
1610 qib_write_kreg(dd, kr_errclear, errs); in handle_7322_errors()
1620 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask, in handle_7322_errors()
1630 qib_dev_err(dd, in handle_7322_errors()
1632 dd->flags &= ~QIB_INITTED; /* needs re-init */ in handle_7322_errors()
1634 *dd->devstatusp |= QIB_STATUS_HWERROR; in handle_7322_errors()
1635 for (pidx = 0; pidx < dd->num_pports; ++pidx) in handle_7322_errors()
1636 if (dd->pport[pidx].link_speed_supported) in handle_7322_errors()
1637 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF; in handle_7322_errors()
1641 qib_dev_err(dd, "%s error\n", msg); in handle_7322_errors()
1651 qib_handle_urcv(dd, ~0U); in handle_7322_errors()
1664 struct qib_devdata *dd = (struct qib_devdata *)data; in qib_error_tasklet() local
1666 handle_7322_errors(dd); in qib_error_tasklet()
1667 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_error_tasklet()
1729 if (!ppd->dd->cspec->r1) in handle_serdes_issues()
1738 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) && in handle_serdes_issues()
1750 if (!ppd->dd->cspec->r1 && in handle_serdes_issues()
1765 ppd->dd->cspec->r1 ? in handle_serdes_issues()
1770 ppd->dd->unit, ppd->port, ibclt); in handle_serdes_issues()
1786 struct qib_devdata *dd = ppd->dd; in handle_7322_p_errors() local
1789 fmask = qib_read_kreg64(dd, kr_act_fmask); in handle_7322_p_errors()
1795 qib_devinfo(dd->pcidev, in handle_7322_p_errors()
1812 qib_dev_porterr(dd, ppd->port, in handle_7322_p_errors()
1929 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); in handle_7322_p_errors()
1938 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable) in qib_7322_set_intr_state() argument
1941 if (dd->flags & QIB_BADINTR) in qib_7322_set_intr_state()
1943 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); in qib_7322_set_intr_state()
1945 qib_write_kreg(dd, kr_intclear, 0ULL); in qib_7322_set_intr_state()
1946 if (dd->cspec->num_msix_entries) { in qib_7322_set_intr_state()
1948 u64 val = qib_read_kreg64(dd, kr_intgranted); in qib_7322_set_intr_state()
1950 qib_write_kreg(dd, kr_intgranted, val); in qib_7322_set_intr_state()
1953 qib_write_kreg(dd, kr_intmask, 0ULL); in qib_7322_set_intr_state()
1971 static void qib_7322_clear_freeze(struct qib_devdata *dd) in qib_7322_clear_freeze() argument
1976 qib_write_kreg(dd, kr_errmask, 0ULL); in qib_7322_clear_freeze()
1978 for (pidx = 0; pidx < dd->num_pports; ++pidx) in qib_7322_clear_freeze()
1979 if (dd->pport[pidx].link_speed_supported) in qib_7322_clear_freeze()
1980 qib_write_kreg_port(dd->pport + pidx, krp_errmask, in qib_7322_clear_freeze()
1984 qib_7322_set_intr_state(dd, 0); in qib_7322_clear_freeze()
1987 qib_write_kreg(dd, kr_control, dd->control); in qib_7322_clear_freeze()
1988 qib_read_kreg32(dd, kr_scratch); in qib_7322_clear_freeze()
1996 qib_write_kreg(dd, kr_hwerrclear, 0ULL); in qib_7322_clear_freeze()
1997 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE); in qib_7322_clear_freeze()
1998 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_7322_clear_freeze()
2000 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in qib_7322_clear_freeze()
2001 if (!dd->pport[pidx].link_speed_supported) in qib_7322_clear_freeze()
2003 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull); in qib_7322_clear_freeze()
2004 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull); in qib_7322_clear_freeze()
2006 qib_7322_set_intr_state(dd, 1); in qib_7322_clear_freeze()
2021 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg, in qib_7322_handle_hwerrors() argument
2028 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); in qib_7322_handle_hwerrors()
2032 qib_dev_err(dd, in qib_7322_handle_hwerrors()
2039 qib_write_kreg(dd, kr_hwerrclear, hwerrs & in qib_7322_handle_hwerrors()
2042 hwerrs &= dd->cspec->hwerrmask; in qib_7322_handle_hwerrors()
2047 qib_devinfo(dd->pcidev, in qib_7322_handle_hwerrors()
2051 ctrl = qib_read_kreg32(dd, kr_control); in qib_7322_handle_hwerrors()
2052 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) { in qib_7322_handle_hwerrors()
2057 dd->cspec->stay_in_freeze) { in qib_7322_handle_hwerrors()
2065 if (dd->flags & QIB_INITTED) in qib_7322_handle_hwerrors()
2068 qib_7322_clear_freeze(dd); in qib_7322_handle_hwerrors()
2077 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); in qib_7322_handle_hwerrors()
2078 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_handle_hwerrors()
2085 qib_dev_err(dd, "%s hardware error\n", msg); in qib_7322_handle_hwerrors()
2087 if (isfatal && !dd->diag_client) { in qib_7322_handle_hwerrors()
2088 qib_dev_err(dd, in qib_7322_handle_hwerrors()
2090 dd->serial); in qib_7322_handle_hwerrors()
2095 if (dd->freezemsg) in qib_7322_handle_hwerrors()
2096 snprintf(dd->freezemsg, dd->freezelen, in qib_7322_handle_hwerrors()
2098 qib_disable_after_error(dd); in qib_7322_handle_hwerrors()
2113 static void qib_7322_init_hwerrors(struct qib_devdata *dd) in qib_7322_init_hwerrors() argument
2118 extsval = qib_read_kreg64(dd, kr_extstatus); in qib_7322_init_hwerrors()
2121 qib_dev_err(dd, "MemBIST did not complete!\n"); in qib_7322_init_hwerrors()
2124 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed)); in qib_7322_init_hwerrors()
2125 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_init_hwerrors()
2128 qib_write_kreg(dd, kr_errclear, ~0ULL); in qib_7322_init_hwerrors()
2130 qib_write_kreg(dd, kr_errmask, ~0ULL); in qib_7322_init_hwerrors()
2131 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); in qib_7322_init_hwerrors()
2132 for (pidx = 0; pidx < dd->num_pports; ++pidx) in qib_7322_init_hwerrors()
2133 if (dd->pport[pidx].link_speed_supported) in qib_7322_init_hwerrors()
2134 qib_write_kreg_port(dd->pport + pidx, krp_errmask, in qib_7322_init_hwerrors()
2144 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable) in qib_set_7322_armlaunch() argument
2147 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH); in qib_set_7322_armlaunch()
2148 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2150 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2151 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_set_7322_armlaunch()
2163 struct qib_devdata *dd = ppd->dd; in qib_set_ib_7322_lstate() local
2201 qib_write_kreg(dd, kr_scratch, 0); in qib_set_ib_7322_lstate()
2214 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports)) argument
2219 struct qib_devdata *dd = ppd->dd; in set_vls() local
2231 totcred = NUM_RCV_BUF_UNITS(dd); in set_vls()
2247 qib_write_kreg(dd, kr_scratch, 0ULL); in set_vls()
2260 qib_write_kreg(dd, kr_scratch, 0ULL); in set_vls()
2275 struct qib_devdata *dd = ppd->dd; in qib_7322_bringup_serdes() local
2288 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_bringup_serdes()
2375 if (dd->base_guid) in qib_7322_bringup_serdes()
2376 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1; in qib_7322_bringup_serdes()
2382 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_bringup_serdes()
2392 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_bringup_serdes()
2397 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2400 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2428 if (ppd->dd->cspec->r1) in qib_7322_mini_quiet_serdes()
2451 struct qib_devdata *dd = ppd->dd; in qib_7322_mini_quiet_serdes() local
2455 diagc = qib_read_kreg64(dd, kr_hwdiagctrl); in qib_7322_mini_quiet_serdes()
2456 qib_write_kreg(dd, kr_hwdiagctrl, in qib_7322_mini_quiet_serdes()
2484 qib_write_kreg(dd, kr_hwdiagctrl, diagc); in qib_7322_mini_quiet_serdes()
2512 struct qib_devdata *dd = ppd->dd; in qib_setup_7322_setextled() local
2521 if (dd->diag_client) in qib_setup_7322_setextled()
2538 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2539 extctl = dd->cspec->extctrl & (ppd->port == 1 ? in qib_setup_7322_setextled()
2553 dd->cspec->extctrl = extctl; in qib_setup_7322_setextled()
2554 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_setup_7322_setextled()
2555 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2566 static void qib_7322_nomsix(struct qib_devdata *dd) in qib_7322_nomsix() argument
2571 dd->cspec->main_int_mask = ~0ULL; in qib_7322_nomsix()
2572 n = dd->cspec->num_msix_entries; in qib_7322_nomsix()
2576 dd->cspec->num_msix_entries = 0; in qib_7322_nomsix()
2579 dd->cspec->msix_entries[i].msix.vector, NULL); in qib_7322_nomsix()
2580 free_cpumask_var(dd->cspec->msix_entries[i].mask); in qib_7322_nomsix()
2581 free_irq(dd->cspec->msix_entries[i].msix.vector, in qib_7322_nomsix()
2582 dd->cspec->msix_entries[i].arg); in qib_7322_nomsix()
2584 qib_nomsix(dd); in qib_7322_nomsix()
2587 intgranted = qib_read_kreg64(dd, kr_intgranted); in qib_7322_nomsix()
2589 qib_write_kreg(dd, kr_intgranted, intgranted); in qib_7322_nomsix()
2592 static void qib_7322_free_irq(struct qib_devdata *dd) in qib_7322_free_irq() argument
2594 if (dd->cspec->irq) { in qib_7322_free_irq()
2595 free_irq(dd->cspec->irq, dd); in qib_7322_free_irq()
2596 dd->cspec->irq = 0; in qib_7322_free_irq()
2598 qib_7322_nomsix(dd); in qib_7322_free_irq()
2601 static void qib_setup_7322_cleanup(struct qib_devdata *dd) in qib_setup_7322_cleanup() argument
2605 qib_7322_free_irq(dd); in qib_setup_7322_cleanup()
2606 kfree(dd->cspec->cntrs); in qib_setup_7322_cleanup()
2607 kfree(dd->cspec->sendchkenable); in qib_setup_7322_cleanup()
2608 kfree(dd->cspec->sendgrhchk); in qib_setup_7322_cleanup()
2609 kfree(dd->cspec->sendibchk); in qib_setup_7322_cleanup()
2610 kfree(dd->cspec->msix_entries); in qib_setup_7322_cleanup()
2611 for (i = 0; i < dd->num_pports; i++) { in qib_setup_7322_cleanup()
2616 kfree(dd->pport[i].cpspec->portcntrs); in qib_setup_7322_cleanup()
2617 if (dd->flags & QIB_HAS_QSFP) { in qib_setup_7322_cleanup()
2618 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2619 dd->cspec->gpio_mask &= ~mask; in qib_setup_7322_cleanup()
2620 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_setup_7322_cleanup()
2621 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2622 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data); in qib_setup_7322_cleanup()
2624 if (dd->pport[i].ibport_data.smi_ah) in qib_setup_7322_cleanup()
2625 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah); in qib_setup_7322_cleanup()
2630 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat) in sdma_7322_intr() argument
2632 struct qib_pportdata *ppd0 = &dd->pport[0]; in sdma_7322_intr()
2633 struct qib_pportdata *ppd1 = &dd->pport[1]; in sdma_7322_intr()
2653 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint) in qib_wantpiobuf_7322_intr() argument
2657 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_wantpiobuf_7322_intr()
2659 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
2661 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
2662 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in qib_wantpiobuf_7322_intr()
2663 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_wantpiobuf_7322_intr()
2664 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_wantpiobuf_7322_intr()
2672 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat) in unknown_7322_ibits() argument
2678 qib_dev_err(dd, in unknown_7322_ibits()
2681 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); in unknown_7322_ibits()
2685 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd) in unknown_7322_gpio_intr() argument
2698 gpiostatus = qib_read_kreg32(dd, kr_gpio_status); in unknown_7322_gpio_intr()
2706 qib_write_kreg(dd, kr_gpio_clear, gpiostatus); in unknown_7322_gpio_intr()
2711 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP); in unknown_7322_gpio_intr()
2716 if (!dd->pport[pidx].link_speed_supported) in unknown_7322_gpio_intr()
2719 ppd = dd->pport + pidx; in unknown_7322_gpio_intr()
2721 if (gpiostatus & dd->cspec->gpio_mask & mask) { in unknown_7322_gpio_intr()
2725 pins = qib_read_kreg64(dd, kr_extstatus); in unknown_7322_gpio_intr()
2736 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); in unknown_7322_gpio_intr()
2742 dd->cspec->gpio_mask &= ~gpio_irq; in unknown_7322_gpio_intr()
2743 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in unknown_7322_gpio_intr()
2751 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat) in unlikely_7322_intr() argument
2754 unknown_7322_ibits(dd, istat); in unlikely_7322_intr()
2756 unknown_7322_gpio_intr(dd); in unlikely_7322_intr()
2758 qib_write_kreg(dd, kr_errmask, 0ULL); in unlikely_7322_intr()
2759 tasklet_schedule(&dd->error_tasklet); in unlikely_7322_intr()
2761 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0]) in unlikely_7322_intr()
2762 handle_7322_p_errors(dd->rcd[0]->ppd); in unlikely_7322_intr()
2763 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1]) in unlikely_7322_intr()
2764 handle_7322_p_errors(dd->rcd[1]->ppd); in unlikely_7322_intr()
2773 struct qib_devdata *dd = rcd->dd; in adjust_rcv_timeout() local
2774 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; in adjust_rcv_timeout()
2787 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; in adjust_rcv_timeout()
2788 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout); in adjust_rcv_timeout()
2801 struct qib_devdata *dd = data; in qib_7322intr() local
2809 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { in qib_7322intr()
2820 istat = qib_read_kreg64(dd, kr_intstatus); in qib_7322intr()
2823 qib_bad_intrstatus(dd); in qib_7322intr()
2824 qib_dev_err(dd, "Interrupt status all f's, skipping\n"); in qib_7322intr()
2830 istat &= dd->cspec->main_int_mask; in qib_7322intr()
2838 if (dd->int_counter != (u32) -1) in qib_7322intr()
2839 dd->int_counter++; in qib_7322intr()
2845 unlikely_7322_intr(dd, istat); in qib_7322intr()
2853 qib_write_kreg(dd, kr_intclear, istat); in qib_7322intr()
2864 for (i = 0; i < dd->first_user_ctxt; i++) { in qib_7322intr()
2867 if (dd->rcd[i]) in qib_7322intr()
2868 qib_kreceive(dd->rcd[i], NULL, &npkts); in qib_7322intr()
2875 qib_handle_urcv(dd, ctxtrbits); in qib_7322intr()
2880 sdma_7322_intr(dd, istat); in qib_7322intr()
2882 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) in qib_7322intr()
2883 qib_ib_piobufavail(dd); in qib_7322intr()
2896 struct qib_devdata *dd = rcd->dd; in qib_7322pintr() local
2899 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in qib_7322pintr()
2909 if (dd->int_counter != (u32) -1) in qib_7322pintr()
2910 dd->int_counter++; in qib_7322pintr()
2913 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) | in qib_7322pintr()
2926 struct qib_devdata *dd = data; in qib_7322bufavail() local
2928 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in qib_7322bufavail()
2938 if (dd->int_counter != (u32) -1) in qib_7322bufavail()
2939 dd->int_counter++; in qib_7322bufavail()
2942 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL); in qib_7322bufavail()
2945 if (dd->flags & QIB_INITTED) in qib_7322bufavail()
2946 qib_ib_piobufavail(dd); in qib_7322bufavail()
2948 qib_wantpiobuf_7322_intr(dd, 0); in qib_7322bufavail()
2959 struct qib_devdata *dd = ppd->dd; in sdma_intr() local
2961 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_intr()
2971 if (dd->int_counter != (u32) -1) in sdma_intr()
2972 dd->int_counter++; in sdma_intr()
2975 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_intr()
2988 struct qib_devdata *dd = ppd->dd; in sdma_idle_intr() local
2990 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_idle_intr()
3000 if (dd->int_counter != (u32) -1) in sdma_idle_intr()
3001 dd->int_counter++; in sdma_idle_intr()
3004 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_idle_intr()
3017 struct qib_devdata *dd = ppd->dd; in sdma_progress_intr() local
3019 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_progress_intr()
3029 if (dd->int_counter != (u32) -1) in sdma_progress_intr()
3030 dd->int_counter++; in sdma_progress_intr()
3033 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_progress_intr()
3047 struct qib_devdata *dd = ppd->dd; in sdma_cleanup_intr() local
3049 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_cleanup_intr()
3059 if (dd->int_counter != (u32) -1) in sdma_cleanup_intr()
3060 dd->int_counter++; in sdma_cleanup_intr()
3063 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_cleanup_intr()
3079 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend) in qib_setup_7322_interrupt() argument
3087 if (!dd->num_pports) in qib_setup_7322_interrupt()
3096 qib_7322_set_intr_state(dd, 0); in qib_setup_7322_interrupt()
3099 qib_7322_init_hwerrors(dd); in qib_setup_7322_interrupt()
3102 qib_write_kreg(dd, kr_intclear, ~0ULL); in qib_setup_7322_interrupt()
3105 qib_write_kreg(dd, kr_intgranted, ~0ULL); in qib_setup_7322_interrupt()
3106 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL); in qib_setup_7322_interrupt()
3109 if (!dd->cspec->num_msix_entries) { in qib_setup_7322_interrupt()
3112 if (!dd->pcidev->irq) { in qib_setup_7322_interrupt()
3113 qib_dev_err(dd, in qib_setup_7322_interrupt()
3117 ret = request_irq(dd->pcidev->irq, qib_7322intr, in qib_setup_7322_interrupt()
3118 IRQF_SHARED, QIB_DRV_NAME, dd); in qib_setup_7322_interrupt()
3120 qib_dev_err(dd, in qib_setup_7322_interrupt()
3122 dd->pcidev->irq, ret); in qib_setup_7322_interrupt()
3125 dd->cspec->irq = dd->pcidev->irq; in qib_setup_7322_interrupt()
3126 dd->cspec->main_int_mask = ~0ULL; in qib_setup_7322_interrupt()
3134 local_mask = cpumask_of_pcibus(dd->pcidev->bus); in qib_setup_7322_interrupt()
3147 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { in qib_setup_7322_interrupt()
3153 dd->cspec->msix_entries[msixnum]. in qib_setup_7322_interrupt()
3154 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1] in qib_setup_7322_interrupt()
3159 if (irq_table[i].port > dd->num_pports) in qib_setup_7322_interrupt()
3161 arg = dd->pport + irq_table[i].port - 1; in qib_setup_7322_interrupt()
3163 arg = dd; in qib_setup_7322_interrupt()
3166 snprintf(dd->cspec->msix_entries[msixnum].name, in qib_setup_7322_interrupt()
3167 sizeof(dd->cspec->msix_entries[msixnum].name) in qib_setup_7322_interrupt()
3169 QIB_DRV_NAME "%d%s", dd->unit, in qib_setup_7322_interrupt()
3176 arg = dd->rcd[ctxt]; in qib_setup_7322_interrupt()
3183 snprintf(dd->cspec->msix_entries[msixnum].name, in qib_setup_7322_interrupt()
3184 sizeof(dd->cspec->msix_entries[msixnum].name) in qib_setup_7322_interrupt()
3186 QIB_DRV_NAME "%d (kctx)", dd->unit); in qib_setup_7322_interrupt()
3189 dd->cspec->msix_entries[msixnum].msix.vector, in qib_setup_7322_interrupt()
3190 handler, 0, dd->cspec->msix_entries[msixnum].name, in qib_setup_7322_interrupt()
3197 qib_dev_err(dd, in qib_setup_7322_interrupt()
3200 dd->cspec->msix_entries[msixnum].msix.vector, in qib_setup_7322_interrupt()
3202 qib_7322_nomsix(dd); in qib_setup_7322_interrupt()
3205 dd->cspec->msix_entries[msixnum].arg = arg; in qib_setup_7322_interrupt()
3213 val = qib_read_kreg64(dd, 2 * msixnum + 1 + in qib_setup_7322_interrupt()
3217 &dd->cspec->msix_entries[msixnum].mask, in qib_setup_7322_interrupt()
3221 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3228 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3231 dd->cspec->msix_entries[msixnum].msix.vector, in qib_setup_7322_interrupt()
3232 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3238 qib_write_kreg(dd, kr_intredirect + i, redirect[i]); in qib_setup_7322_interrupt()
3239 dd->cspec->main_int_mask = mask; in qib_setup_7322_interrupt()
3240 tasklet_init(&dd->error_tasklet, qib_error_tasklet, in qib_setup_7322_interrupt()
3241 (unsigned long)dd); in qib_setup_7322_interrupt()
3251 static unsigned qib_7322_boardname(struct qib_devdata *dd) in qib_7322_boardname() argument
3258 boardid = SYM_FIELD(dd->revision, Revision, BoardID); in qib_7322_boardname()
3266 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3271 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3278 qib_dev_err(dd, "Unsupported version of QMH7342\n"); in qib_7322_boardname()
3290 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3294 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3298 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid); in qib_7322_boardname()
3301 dd->board_atten = 1; /* index into txdds_Xdr */ in qib_7322_boardname()
3304 dd->boardname = kmalloc(namelen, GFP_KERNEL); in qib_7322_boardname()
3305 if (!dd->boardname) in qib_7322_boardname()
3306 qib_dev_err(dd, "Failed allocation for board name: %s\n", n); in qib_7322_boardname()
3308 snprintf(dd->boardname, namelen, "%s", n); in qib_7322_boardname()
3310 snprintf(dd->boardversion, sizeof(dd->boardversion), in qib_7322_boardname()
3312 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, in qib_7322_boardname()
3313 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch), in qib_7322_boardname()
3314 dd->majrev, dd->minrev, in qib_7322_boardname()
3315 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW)); in qib_7322_boardname()
3318 qib_devinfo(dd->pcidev, in qib_7322_boardname()
3320 dd->unit); in qib_7322_boardname()
3331 static int qib_do_7322_reset(struct qib_devdata *dd) in qib_do_7322_reset() argument
3341 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); in qib_do_7322_reset()
3343 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz); in qib_do_7322_reset()
3345 msix_entries = dd->cspec->num_msix_entries; in qib_do_7322_reset()
3348 qib_7322_set_intr_state(dd, 0); in qib_do_7322_reset()
3351 qib_7322_nomsix(dd); in qib_do_7322_reset()
3353 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries * in qib_do_7322_reset()
3356 qib_dev_err(dd, "No mem to save MSIx data\n"); in qib_do_7322_reset()
3369 vecaddr = qib_read_kreg64(dd, 2 * i + in qib_do_7322_reset()
3371 vecdata = qib_read_kreg64(dd, 1 + 2 * i + in qib_do_7322_reset()
3380 dd->pport->cpspec->ibdeltainprog = 0; in qib_do_7322_reset()
3381 dd->pport->cpspec->ibsymdelta = 0; in qib_do_7322_reset()
3382 dd->pport->cpspec->iblnkerrdelta = 0; in qib_do_7322_reset()
3383 dd->pport->cpspec->ibmalfdelta = 0; in qib_do_7322_reset()
3384 dd->int_counter = 0; /* so we check interrupts work again */ in qib_do_7322_reset()
3391 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR); in qib_do_7322_reset()
3392 dd->flags |= QIB_DOING_RESET; in qib_do_7322_reset()
3393 val = dd->control | QLOGIC_IB_C_RESET; in qib_do_7322_reset()
3394 writeq(val, &dd->kregbase[kr_control]); in qib_do_7322_reset()
3404 qib_pcie_reenable(dd, cmdval, int_line, clinesz); in qib_do_7322_reset()
3410 val = readq(&dd->kregbase[kr_revision]); in qib_do_7322_reset()
3411 if (val == dd->revision) in qib_do_7322_reset()
3414 qib_dev_err(dd, in qib_do_7322_reset()
3421 dd->flags |= QIB_PRESENT; /* it's back */ in qib_do_7322_reset()
3426 dd->cspec->msix_entries[i].msix.entry = i; in qib_do_7322_reset()
3429 qib_write_kreg(dd, 2 * i + in qib_do_7322_reset()
3432 qib_write_kreg(dd, 1 + 2 * i + in qib_do_7322_reset()
3439 for (i = 0; i < dd->num_pports; ++i) in qib_do_7322_reset()
3440 write_7322_init_portregs(&dd->pport[i]); in qib_do_7322_reset()
3441 write_7322_initregs(dd); in qib_do_7322_reset()
3443 if (qib_pcie_params(dd, dd->lbus_width, in qib_do_7322_reset()
3444 &dd->cspec->num_msix_entries, in qib_do_7322_reset()
3445 dd->cspec->msix_entries)) in qib_do_7322_reset()
3446 qib_dev_err(dd, in qib_do_7322_reset()
3449 qib_setup_7322_interrupt(dd, 1); in qib_do_7322_reset()
3451 for (i = 0; i < dd->num_pports; ++i) { in qib_do_7322_reset()
3452 struct qib_pportdata *ppd = &dd->pport[i]; in qib_do_7322_reset()
3461 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */ in qib_do_7322_reset()
3473 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, in qib_7322_put_tid() argument
3476 if (!(dd->flags & QIB_PRESENT)) in qib_7322_put_tid()
3478 if (pa != dd->tidinvalid) { in qib_7322_put_tid()
3483 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", in qib_7322_put_tid()
3488 qib_dev_err(dd, in qib_7322_put_tid()
3495 chippa |= dd->tidtemplate; in qib_7322_put_tid()
3512 static void qib_7322_clear_tids(struct qib_devdata *dd, in qib_7322_clear_tids() argument
3520 if (!dd->kregbase || !rcd) in qib_7322_clear_tids()
3525 tidinv = dd->tidinvalid; in qib_7322_clear_tids()
3527 ((char __iomem *) dd->kregbase + in qib_7322_clear_tids()
3528 dd->rcvtidbase + in qib_7322_clear_tids()
3529 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); in qib_7322_clear_tids()
3531 for (i = 0; i < dd->rcvtidcnt; i++) in qib_7322_clear_tids()
3532 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, in qib_7322_clear_tids()
3536 ((char __iomem *) dd->kregbase + in qib_7322_clear_tids()
3537 dd->rcvegrbase + in qib_7322_clear_tids()
3541 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, in qib_7322_clear_tids()
3551 static void qib_7322_tidtemplate(struct qib_devdata *dd) in qib_7322_tidtemplate() argument
3562 if (dd->rcvegrbufsize == 2048) in qib_7322_tidtemplate()
3563 dd->tidtemplate = IBA7322_TID_SZ_2K; in qib_7322_tidtemplate()
3564 else if (dd->rcvegrbufsize == 4096) in qib_7322_tidtemplate()
3565 dd->tidtemplate = IBA7322_TID_SZ_4K; in qib_7322_tidtemplate()
3566 dd->tidinvalid = 0; in qib_7322_tidtemplate()
3584 if (rcd->dd->cspec->r1) in qib_7322_get_base_info()
3586 if (rcd->dd->flags & QIB_USE_SPCL_TRIG) in qib_7322_get_base_info()
3593 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) in qib_7322_get_msgheader() argument
3598 (rhf_addr - dd->rhf_offset + offset); in qib_7322_get_msgheader()
3604 static void qib_7322_config_ctxts(struct qib_devdata *dd) in qib_7322_config_ctxts() argument
3609 nchipctxts = qib_read_kreg32(dd, kr_contextcnt); in qib_7322_config_ctxts()
3610 dd->cspec->numctxts = nchipctxts; in qib_7322_config_ctxts()
3611 if (qib_n_krcv_queues > 1 && dd->num_pports) { in qib_7322_config_ctxts()
3612 dd->first_user_ctxt = NUM_IB_PORTS + in qib_7322_config_ctxts()
3613 (qib_n_krcv_queues - 1) * dd->num_pports; in qib_7322_config_ctxts()
3614 if (dd->first_user_ctxt > nchipctxts) in qib_7322_config_ctxts()
3615 dd->first_user_ctxt = nchipctxts; in qib_7322_config_ctxts()
3616 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports; in qib_7322_config_ctxts()
3618 dd->first_user_ctxt = NUM_IB_PORTS; in qib_7322_config_ctxts()
3619 dd->n_krcv_queues = 1; in qib_7322_config_ctxts()
3623 int nctxts = dd->first_user_ctxt + num_online_cpus(); in qib_7322_config_ctxts()
3626 dd->ctxtcnt = 6; in qib_7322_config_ctxts()
3628 dd->ctxtcnt = 10; in qib_7322_config_ctxts()
3630 dd->ctxtcnt = nchipctxts; in qib_7322_config_ctxts()
3631 } else if (qib_cfgctxts < dd->num_pports) in qib_7322_config_ctxts()
3632 dd->ctxtcnt = dd->num_pports; in qib_7322_config_ctxts()
3634 dd->ctxtcnt = qib_cfgctxts; in qib_7322_config_ctxts()
3635 if (!dd->ctxtcnt) /* none of the above, set to max */ in qib_7322_config_ctxts()
3636 dd->ctxtcnt = nchipctxts; in qib_7322_config_ctxts()
3643 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
3644 if (dd->ctxtcnt > 10) in qib_7322_config_ctxts()
3645 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3646 else if (dd->ctxtcnt > 6) in qib_7322_config_ctxts()
3647 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3651 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode); in qib_7322_config_ctxts()
3657 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); in qib_7322_config_ctxts()
3658 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
3661 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); in qib_7322_config_ctxts()
3663 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); in qib_7322_config_ctxts()
3665 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt, in qib_7322_config_ctxts()
3666 dd->num_pports > 1 ? 1024U : 2048U); in qib_7322_config_ctxts()
3774 struct qib_devdata *dd = ppd->dd; in qib_7322_set_ib_cfg() local
3859 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_set_ib_cfg()
3873 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_set_ib_cfg()
3893 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_set_ib_cfg()
3910 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_set_ib_cfg()
3949 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); in qib_7322_set_ib_cfg()
3980 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n", in qib_7322_set_ib_cfg()
4009 if (ppd->dd->cspec->r1) { in qib_7322_set_ib_cfg()
4022 qib_write_kreg(dd, kr_scratch, 0); in qib_7322_set_ib_cfg()
4037 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", in qib_7322_set_loopback()
4038 ppd->dd->unit, ppd->port); in qib_7322_set_loopback()
4044 qib_devinfo(ppd->dd->pcidev, in qib_7322_set_loopback()
4046 ppd->dd->unit, ppd->port); in qib_7322_set_loopback()
4057 qib_write_kreg(ppd->dd, kr_scratch, 0); in qib_7322_set_loopback()
4092 struct qib_devdata *dd = ppd->dd; in set_vl_weights() local
4095 spin_lock_irqsave(&dd->sendctrl_lock, flags); in set_vl_weights()
4098 qib_write_kreg(dd, kr_scratch, 0); in set_vl_weights()
4099 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in set_vl_weights()
4147 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); in qib_update_7322_usrhead()
4149 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_7322_usrhead()
4150 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_7322_usrhead()
4158 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); in qib_7322_hdrqempty()
4162 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); in qib_7322_hdrqempty()
4192 struct qib_devdata *dd = ppd->dd; in rcvctrl_7322_mod() local
4197 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4200 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4202 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4204 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4206 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4212 mask = (1ULL << dd->ctxtcnt) - 1; in rcvctrl_7322_mod()
4216 rcd = dd->rcd[ctxt]; in rcvctrl_7322_mod()
4221 if (!(dd->flags & QIB_NODMA_RTAIL)) { in rcvctrl_7322_mod()
4223 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4226 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, in rcvctrl_7322_mod()
4228 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, in rcvctrl_7322_mod()
4236 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); in rcvctrl_7322_mod()
4238 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); in rcvctrl_7322_mod()
4240 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4242 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4249 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); in rcvctrl_7322_mod()
4252 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) { in rcvctrl_7322_mod()
4259 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); in rcvctrl_7322_mod()
4260 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); in rcvctrl_7322_mod()
4263 (void) qib_read_kreg32(dd, kr_scratch); in rcvctrl_7322_mod()
4264 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); in rcvctrl_7322_mod()
4265 dd->rcd[ctxt]->head = val; in rcvctrl_7322_mod()
4267 if (ctxt < dd->first_user_ctxt) in rcvctrl_7322_mod()
4268 val |= dd->rhdrhead_intr_off; in rcvctrl_7322_mod()
4269 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); in rcvctrl_7322_mod()
4271 dd->rcd[ctxt] && dd->rhdrhead_intr_off) { in rcvctrl_7322_mod()
4273 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off; in rcvctrl_7322_mod()
4274 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); in rcvctrl_7322_mod()
4281 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0); in rcvctrl_7322_mod()
4282 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0); in rcvctrl_7322_mod()
4284 qib_write_ureg(dd, ur_rcvflowtable + f, in rcvctrl_7322_mod()
4289 for (i = 0; i < dd->cfgctxts; i++) { in rcvctrl_7322_mod()
4290 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, in rcvctrl_7322_mod()
4292 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0); in rcvctrl_7322_mod()
4294 qib_write_ureg(dd, ur_rcvflowtable + f, in rcvctrl_7322_mod()
4299 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4331 struct qib_devdata *dd = ppd->dd; in sendctrl_7322_mod() local
4335 spin_lock_irqsave(&dd->sendctrl_lock, flags); in sendctrl_7322_mod()
4339 dd->sendctrl = 0; in sendctrl_7322_mod()
4341 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4343 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4344 if (dd->flags & QIB_USE_SPCL_TRIG) in sendctrl_7322_mod()
4345 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn); in sendctrl_7322_mod()
4357 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_7322_mod()
4358 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; in sendctrl_7322_mod()
4365 qib_write_kreg(dd, kr_sendctrl, in sendctrl_7322_mod()
4368 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4384 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4387 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_7322_mod()
4394 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd))) in sendctrl_7322_mod()
4398 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl); in sendctrl_7322_mod()
4399 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4404 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4408 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in sendctrl_7322_mod()
4409 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_7322_mod()
4412 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in sendctrl_7322_mod()
4422 v = qib_read_kreg32(dd, kr_scratch); in sendctrl_7322_mod()
4423 qib_write_kreg(dd, kr_scratch, v); in sendctrl_7322_mod()
4424 v = qib_read_kreg32(dd, kr_scratch); in sendctrl_7322_mod()
4425 qib_write_kreg(dd, kr_scratch, v); in sendctrl_7322_mod()
4426 qib_read_kreg32(dd, kr_scratch); in sendctrl_7322_mod()
4441 struct qib_devdata *dd = ppd->dd; in qib_portcntr_7322() local
4489 qib_devinfo(ppd->dd->pcidev, in qib_portcntr_7322()
4500 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) { in qib_portcntr_7322()
4501 struct qib_ctxtdata *rcd = dd->rcd[i]; in qib_portcntr_7322()
4505 ret += read_7322_creg32(dd, cr_base_egrovfl + i); in qib_portcntr_7322()
4697 static void init_7322_cntrnames(struct qib_devdata *dd) in init_7322_cntrnames() argument
4702 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts; in init_7322_cntrnames()
4711 dd->cspec->ncntrs = i; in init_7322_cntrnames()
4714 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; in init_7322_cntrnames()
4716 dd->cspec->cntrnamelen = 1 + s - cntr7322names; in init_7322_cntrnames()
4717 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs in init_7322_cntrnames()
4719 if (!dd->cspec->cntrs) in init_7322_cntrnames()
4720 qib_dev_err(dd, "Failed allocation for counters\n"); in init_7322_cntrnames()
4724 dd->cspec->nportcntrs = i - 1; in init_7322_cntrnames()
4725 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; in init_7322_cntrnames()
4726 for (i = 0; i < dd->num_pports; ++i) { in init_7322_cntrnames()
4727 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs in init_7322_cntrnames()
4729 if (!dd->pport[i].cpspec->portcntrs) in init_7322_cntrnames()
4730 qib_dev_err(dd, in init_7322_cntrnames()
4735 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep, in qib_read_7322cntrs() argument
4741 ret = dd->cspec->cntrnamelen; in qib_read_7322cntrs()
4747 u64 *cntr = dd->cspec->cntrs; in qib_read_7322cntrs()
4750 ret = dd->cspec->ncntrs * sizeof(u64); in qib_read_7322cntrs()
4757 for (i = 0; i < dd->cspec->ncntrs; i++) in qib_read_7322cntrs()
4759 *cntr++ = read_7322_creg(dd, in qib_read_7322cntrs()
4763 *cntr++ = read_7322_creg32(dd, in qib_read_7322cntrs()
4770 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, in qib_read_7322portcntrs() argument
4776 ret = dd->cspec->portcntrnamelen; in qib_read_7322portcntrs()
4782 struct qib_pportdata *ppd = &dd->pport[port]; in qib_read_7322portcntrs()
4786 ret = dd->cspec->nportcntrs * sizeof(u64); in qib_read_7322portcntrs()
4793 for (i = 0; i < dd->cspec->nportcntrs; i++) { in qib_read_7322portcntrs()
4824 struct qib_devdata *dd = (struct qib_devdata *) opaque; in qib_get_7322_faststats() local
4830 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in qib_get_7322_faststats()
4831 ppd = dd->pport + pidx; in qib_get_7322_faststats()
4838 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED) in qib_get_7322_faststats()
4839 || dd->diag_client) in qib_get_7322_faststats()
4849 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags); in qib_get_7322_faststats()
4850 traffic_wds -= ppd->dd->traffic_wds; in qib_get_7322_faststats()
4851 ppd->dd->traffic_wds += traffic_wds; in qib_get_7322_faststats()
4853 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time); in qib_get_7322_faststats()
4854 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags); in qib_get_7322_faststats()
4864 ppd->dd->cspec->r1 ? in qib_get_7322_faststats()
4870 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); in qib_get_7322_faststats()
4876 static int qib_7322_intr_fallback(struct qib_devdata *dd) in qib_7322_intr_fallback() argument
4878 if (!dd->cspec->num_msix_entries) in qib_7322_intr_fallback()
4881 qib_devinfo(dd->pcidev, in qib_7322_intr_fallback()
4883 qib_7322_nomsix(dd); in qib_7322_intr_fallback()
4884 qib_enable_intx(dd->pcidev); in qib_7322_intr_fallback()
4885 qib_setup_7322_interrupt(dd, 0); in qib_7322_intr_fallback()
4901 struct qib_devdata *dd = ppd->dd; in qib_7322_mini_pcs_reset() local
4907 qib_write_kreg(dd, kr_hwerrmask, in qib_7322_mini_pcs_reset()
4908 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); in qib_7322_mini_pcs_reset()
4914 qib_read_kreg32(dd, kr_scratch); in qib_7322_mini_pcs_reset()
4917 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_7322_mini_pcs_reset()
4918 qib_write_kreg(dd, kr_hwerrclear, in qib_7322_mini_pcs_reset()
4920 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_mini_pcs_reset()
4938 struct qib_devdata *dd = ppd->dd; in autoneg_7322_sendpkt() local
4950 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL); in autoneg_7322_sendpkt()
4955 if (dd->flags & QIB_USE_SPCL_TRIG) { in autoneg_7322_sendpkt()
4956 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023; in autoneg_7322_sendpkt()
4962 qib_sendbuf_done(dd, pnum); in autoneg_7322_sendpkt()
4964 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL); in autoneg_7322_sendpkt()
4972 struct qib_devdata *dd = ppd->dd; in qib_autoneg_7322_send() local
5007 qib_read_kreg64(dd, kr_scratch); in qib_autoneg_7322_send()
5010 qib_read_kreg64(dd, kr_scratch); in qib_autoneg_7322_send()
5050 qib_write_kreg(ppd->dd, kr_scratch, 0); in set_7322_ibspeed_fast()
5081 struct qib_devdata *dd; in autoneg_7322_work() local
5088 dd = ppd->dd; in autoneg_7322_work()
5301 if (ppd->dd->flags & QIB_HAS_QSFP) { in qib_7322_ib_updown()
5369 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) in qib_7322_ib_updown()
5412 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) in gpio_7322_mod() argument
5421 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5422 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5423 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5424 new_out = (dd->cspec->gpio_out & ~mask) | out; in gpio_7322_mod()
5426 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in gpio_7322_mod()
5427 qib_write_kreg(dd, kr_gpio_out, new_out); in gpio_7322_mod()
5428 dd->cspec->gpio_out = new_out; in gpio_7322_mod()
5429 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5439 read_val = qib_read_kreg64(dd, kr_extstatus); in gpio_7322_mod()
5444 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen) in qib_7322_eeprom_wen() argument
5450 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM; in qib_7322_eeprom_wen()
5451 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask); in qib_7322_eeprom_wen()
5461 static void get_7322_chip_params(struct qib_devdata *dd) in get_7322_chip_params() argument
5467 dd->palign = qib_read_kreg32(dd, kr_pagealign); in get_7322_chip_params()
5469 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); in get_7322_chip_params()
5471 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); in get_7322_chip_params()
5472 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); in get_7322_chip_params()
5473 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); in get_7322_chip_params()
5474 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); in get_7322_chip_params()
5475 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; in get_7322_chip_params()
5477 val = qib_read_kreg64(dd, kr_sendpiobufcnt); in get_7322_chip_params()
5478 dd->piobcnt2k = val & ~0U; in get_7322_chip_params()
5479 dd->piobcnt4k = val >> 32; in get_7322_chip_params()
5480 val = qib_read_kreg64(dd, kr_sendpiosize); in get_7322_chip_params()
5481 dd->piosize2k = val & ~0U; in get_7322_chip_params()
5482 dd->piosize4k = val >> 32; in get_7322_chip_params()
5487 dd->pport[0].ibmtu = (u32)mtu; in get_7322_chip_params()
5488 dd->pport[1].ibmtu = (u32)mtu; in get_7322_chip_params()
5491 dd->pio2kbase = (u32 __iomem *) in get_7322_chip_params()
5492 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase); in get_7322_chip_params()
5493 dd->pio4kbase = (u32 __iomem *) in get_7322_chip_params()
5494 ((char __iomem *) dd->kregbase + in get_7322_chip_params()
5495 (dd->piobufbase >> 32)); in get_7322_chip_params()
5501 dd->align4k = ALIGN(dd->piosize4k, dd->palign); in get_7322_chip_params()
5503 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS; in get_7322_chip_params()
5505 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / in get_7322_chip_params()
5514 static void qib_7322_set_baseaddrs(struct qib_devdata *dd) in qib_7322_set_baseaddrs() argument
5517 cregbase = qib_read_kreg32(dd, kr_counterregbase); in qib_7322_set_baseaddrs()
5519 dd->cspec->cregbase = (u64 __iomem *)(cregbase + in qib_7322_set_baseaddrs()
5520 (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5522 dd->egrtidbase = (u64 __iomem *) in qib_7322_set_baseaddrs()
5523 ((char __iomem *) dd->kregbase + dd->rcvegrbase); in qib_7322_set_baseaddrs()
5526 dd->pport[0].cpspec->kpregbase = in qib_7322_set_baseaddrs()
5527 (u64 __iomem *)((char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5528 dd->pport[1].cpspec->kpregbase = in qib_7322_set_baseaddrs()
5529 (u64 __iomem *)(dd->palign + in qib_7322_set_baseaddrs()
5530 (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5531 dd->pport[0].cpspec->cpregbase = in qib_7322_set_baseaddrs()
5532 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0], in qib_7322_set_baseaddrs()
5533 kr_counterregbase) + (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5534 dd->pport[1].cpspec->cpregbase = in qib_7322_set_baseaddrs()
5535 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1], in qib_7322_set_baseaddrs()
5536 kr_counterregbase) + (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5552 static int sendctrl_hook(struct qib_devdata *dd, in sendctrl_hook() argument
5568 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in sendctrl_hook()
5572 ppd = dd->pport + pidx; in sendctrl_hook()
5577 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr); in sendctrl_hook()
5583 if (pidx >= dd->num_pports) in sendctrl_hook()
5593 spin_lock_irqsave(&dd->sendctrl_lock, flags); in sendctrl_hook()
5603 local_data = (u64)qib_read_kreg32(dd, idx); in sendctrl_hook()
5605 local_data = qib_read_kreg64(dd, idx); in sendctrl_hook()
5626 qib_write_kreg(dd, idx, tval); in sendctrl_hook()
5627 qib_write_kreg(dd, kr_scratch, 0Ull); in sendctrl_hook()
5629 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in sendctrl_hook()
5695 if (!ret && !ppd->dd->cspec->r1) { in qsfp_7322_event()
5737 struct qib_devdata *dd = ppd->dd; in qib_init_7322_qsfp() local
5743 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
5744 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); in qib_init_7322_qsfp()
5745 dd->cspec->gpio_mask |= mod_prs_bit; in qib_init_7322_qsfp()
5746 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_init_7322_qsfp()
5747 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_init_7322_qsfp()
5748 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
5764 static void set_no_qsfp_atten(struct qib_devdata *dd, int change) in set_no_qsfp_atten() argument
5776 for (pidx = 0; pidx < dd->num_pports; ++pidx) in set_no_qsfp_atten()
5777 dd->pport[pidx].cpspec->no_eep = deflt; in set_no_qsfp_atten()
5780 if (IS_QME(dd) || IS_QMH(dd)) in set_no_qsfp_atten()
5818 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports; in set_no_qsfp_atten()
5820 struct qib_pportdata *ppd = &dd->pport[pidx]; in set_no_qsfp_atten()
5832 if (IS_QMH(dd) || IS_QME(dd)) in set_no_qsfp_atten()
5845 for (pidx = 0; pidx < dd->num_pports; ++pidx) in set_no_qsfp_atten()
5846 if (dd->pport[pidx].link_speed_supported) in set_no_qsfp_atten()
5847 init_txdds_table(&dd->pport[pidx], 0); in set_no_qsfp_atten()
5854 struct qib_devdata *dd; in setup_txselect() local
5871 list_for_each_entry(dd, &qib_dev_list, list) in setup_txselect()
5872 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322) in setup_txselect()
5873 set_no_qsfp_atten(dd, 1); in setup_txselect()
5882 static int qib_late_7322_initreg(struct qib_devdata *dd) in qib_late_7322_initreg() argument
5887 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); in qib_late_7322_initreg()
5888 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); in qib_late_7322_initreg()
5889 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); in qib_late_7322_initreg()
5890 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); in qib_late_7322_initreg()
5891 val = qib_read_kreg64(dd, kr_sendpioavailaddr); in qib_late_7322_initreg()
5892 if (val != dd->pioavailregs_phys) { in qib_late_7322_initreg()
5893 qib_dev_err(dd, in qib_late_7322_initreg()
5895 (unsigned long) dd->pioavailregs_phys, in qib_late_7322_initreg()
5900 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; in qib_late_7322_initreg()
5901 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL); in qib_late_7322_initreg()
5903 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL); in qib_late_7322_initreg()
5905 qib_register_observer(dd, &sendctrl_0_observer); in qib_late_7322_initreg()
5906 qib_register_observer(dd, &sendctrl_1_observer); in qib_late_7322_initreg()
5908 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN; in qib_late_7322_initreg()
5909 qib_write_kreg(dd, kr_control, dd->control); in qib_late_7322_initreg()
5916 set_no_qsfp_atten(dd, 0); in qib_late_7322_initreg()
5917 for (n = 0; n < dd->num_pports; ++n) { in qib_late_7322_initreg()
5918 struct qib_pportdata *ppd = dd->pport + n; in qib_late_7322_initreg()
5923 if (dd->flags & QIB_HAS_QSFP) in qib_late_7322_initreg()
5926 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN; in qib_late_7322_initreg()
5927 qib_write_kreg(dd, kr_control, dd->control); in qib_late_7322_initreg()
5956 qib_write_kreg(ppd->dd, kr_scratch, 0); in write_7322_init_portregs()
5987 if (ppd->dd->cspec->r1) in write_7322_init_portregs()
5998 static void write_7322_initregs(struct qib_devdata *dd) in write_7322_initregs() argument
6005 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1); in write_7322_initregs()
6007 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in write_7322_initregs()
6011 if (dd->n_krcv_queues < 2 || in write_7322_initregs()
6012 !dd->pport[pidx].link_speed_supported) in write_7322_initregs()
6015 ppd = &dd->pport[pidx]; in write_7322_initregs()
6018 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6020 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6025 if (dd->num_pports > 1) in write_7322_initregs()
6026 n = dd->first_user_ctxt / dd->num_pports; in write_7322_initregs()
6028 n = dd->first_user_ctxt - 1; in write_7322_initregs()
6032 if (dd->num_pports > 1) in write_7322_initregs()
6033 ctxt = (i % n) * dd->num_pports + pidx; in write_7322_initregs()
6055 for (i = 0; i < dd->first_user_ctxt; i++) { in write_7322_initregs()
6056 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; in write_7322_initregs()
6057 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout); in write_7322_initregs()
6066 for (i = 0; i < dd->cfgctxts; i++) { in write_7322_initregs()
6069 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i); in write_7322_initregs()
6077 if (dd->num_pports) in write_7322_initregs()
6078 setup_7322_link_recovery(dd->pport, dd->num_pports > 1); in write_7322_initregs()
6081 static int qib_init_7322_variables(struct qib_devdata *dd) in qib_init_7322_variables() argument
6089 ppd = (struct qib_pportdata *)(dd + 1); in qib_init_7322_variables()
6090 dd->pport = ppd; in qib_init_7322_variables()
6091 ppd[0].dd = dd; in qib_init_7322_variables()
6092 ppd[1].dd = dd; in qib_init_7322_variables()
6094 dd->cspec = (struct qib_chip_specific *)(ppd + 2); in qib_init_7322_variables()
6096 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); in qib_init_7322_variables()
6101 spin_lock_init(&dd->cspec->rcvmod_lock); in qib_init_7322_variables()
6102 spin_lock_init(&dd->cspec->gpio_lock); in qib_init_7322_variables()
6105 dd->revision = readq(&dd->kregbase[kr_revision]); in qib_init_7322_variables()
6107 if ((dd->revision & 0xffffffffU) == 0xffffffffU) { in qib_init_7322_variables()
6108 qib_dev_err(dd, in qib_init_7322_variables()
6113 dd->flags |= QIB_PRESENT; /* now register routines work */ in qib_init_7322_variables()
6115 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor); in qib_init_7322_variables()
6116 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor); in qib_init_7322_variables()
6117 dd->cspec->r1 = dd->minrev == 1; in qib_init_7322_variables()
6119 get_7322_chip_params(dd); in qib_init_7322_variables()
6120 features = qib_7322_boardname(dd); in qib_init_7322_variables()
6123 sbufcnt = dd->piobcnt2k + dd->piobcnt4k + in qib_init_7322_variables()
6126 dd->cspec->sendchkenable = kmalloc(sbufcnt * in qib_init_7322_variables()
6127 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL); in qib_init_7322_variables()
6128 dd->cspec->sendgrhchk = kmalloc(sbufcnt * in qib_init_7322_variables()
6129 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL); in qib_init_7322_variables()
6130 dd->cspec->sendibchk = kmalloc(sbufcnt * in qib_init_7322_variables()
6131 sizeof(*dd->cspec->sendibchk), GFP_KERNEL); in qib_init_7322_variables()
6132 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || in qib_init_7322_variables()
6133 !dd->cspec->sendibchk) { in qib_init_7322_variables()
6134 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n"); in qib_init_7322_variables()
6139 ppd = dd->pport; in qib_init_7322_variables()
6145 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; in qib_init_7322_variables()
6146 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; in qib_init_7322_variables()
6147 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV; in qib_init_7322_variables()
6149 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY | in qib_init_7322_variables()
6153 dd->flags |= qib_special_trigger ? in qib_init_7322_variables()
6160 qib_7322_set_baseaddrs(dd); in qib_init_7322_variables()
6166 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; in qib_init_7322_variables()
6168 dd->cspec->hwerrmask = ~0ULL; in qib_init_7322_variables()
6171 dd->cspec->hwerrmask &= in qib_init_7322_variables()
6182 dd->skip_kctxt_mask |= 1 << pidx; in qib_init_7322_variables()
6188 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6192 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6203 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6207 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6218 dd->num_pports++; in qib_init_7322_variables()
6219 qib_init_pportdata(ppd, dd, pidx, dd->num_pports); in qib_init_7322_variables()
6239 qib_devinfo(dd->pcidev, in qib_init_7322_variables()
6251 qib_devinfo(dd->pcidev, in qib_init_7322_variables()
6265 if (ppd->dd->cspec->r1) in qib_init_7322_variables()
6273 if (!(dd->flags & QIB_HAS_QSFP)) { in qib_init_7322_variables()
6274 if (!IS_QMH(dd) && !IS_QME(dd)) in qib_init_7322_variables()
6275 qib_devinfo(dd->pcidev, in qib_init_7322_variables()
6277 dd->unit, ppd->port); in qib_init_7322_variables()
6278 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME; in qib_init_7322_variables()
6283 ppd->cpspec->no_eep = IS_QMH(dd) ? in qib_init_7322_variables()
6299 dd->rcvhdrentsize = qib_rcvhdrentsize ? in qib_init_7322_variables()
6301 dd->rcvhdrsize = qib_rcvhdrsize ? in qib_init_7322_variables()
6303 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32); in qib_init_7322_variables()
6306 dd->rcvegrbufsize = max(mtu, 2048); in qib_init_7322_variables()
6307 BUG_ON(!is_power_of_2(dd->rcvegrbufsize)); in qib_init_7322_variables()
6308 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); in qib_init_7322_variables()
6310 qib_7322_tidtemplate(dd); in qib_init_7322_variables()
6316 dd->rhdrhead_intr_off = in qib_init_7322_variables()
6320 init_timer(&dd->stats_timer); in qib_init_7322_variables()
6321 dd->stats_timer.function = qib_get_7322_faststats; in qib_init_7322_variables()
6322 dd->stats_timer.data = (unsigned long) dd; in qib_init_7322_variables()
6324 dd->ureg_align = 0x10000; /* 64KB alignment */ in qib_init_7322_variables()
6326 dd->piosize2kmax_dwords = dd->piosize2k >> 2; in qib_init_7322_variables()
6328 qib_7322_config_ctxts(dd); in qib_init_7322_variables()
6329 qib_set_ctxtcnt(dd); in qib_init_7322_variables()
6340 ret = init_chip_wc_pat(dd, 0); in qib_init_7322_variables()
6345 vl15off = dd->physaddr + (dd->piobufbase >> 32) + in qib_init_7322_variables()
6346 dd->piobcnt4k * dd->align4k; in qib_init_7322_variables()
6347 dd->piovl15base = ioremap_nocache(vl15off, in qib_init_7322_variables()
6348 NUM_VL15_BUFS * dd->align4k); in qib_init_7322_variables()
6349 if (!dd->piovl15base) { in qib_init_7322_variables()
6354 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */ in qib_init_7322_variables()
6359 if (!dd->num_pports) { in qib_init_7322_variables()
6360 qib_dev_err(dd, "No ports enabled, giving up initialization\n"); in qib_init_7322_variables()
6364 write_7322_initregs(dd); in qib_init_7322_variables()
6365 ret = qib_create_ctxts(dd); in qib_init_7322_variables()
6366 init_7322_cntrnames(dd); in qib_init_7322_variables()
6380 if (dd->flags & QIB_HAS_SEND_DMA) { in qib_init_7322_variables()
6381 dd->cspec->sdmabufcnt = dd->piobcnt4k; in qib_init_7322_variables()
6384 dd->cspec->sdmabufcnt = 0; in qib_init_7322_variables()
6385 sbufs = dd->piobcnt4k; in qib_init_7322_variables()
6387 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - in qib_init_7322_variables()
6388 dd->cspec->sdmabufcnt; in qib_init_7322_variables()
6389 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; in qib_init_7322_variables()
6390 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ in qib_init_7322_variables()
6391 dd->last_pio = dd->cspec->lastbuf_for_pio; in qib_init_7322_variables()
6392 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ? in qib_init_7322_variables()
6393 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0; in qib_init_7322_variables()
6401 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh) in qib_init_7322_variables()
6402 updthresh = dd->pbufsctxt - 2; in qib_init_7322_variables()
6403 dd->cspec->updthresh_dflt = updthresh; in qib_init_7322_variables()
6404 dd->cspec->updthresh = updthresh; in qib_init_7322_variables()
6407 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld)) in qib_init_7322_variables()
6411 dd->psxmitwait_supported = 1; in qib_init_7322_variables()
6412 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE; in qib_init_7322_variables()
6414 if (!dd->ctxtcnt) in qib_init_7322_variables()
6415 dd->ctxtcnt = 1; /* for other initialization code */ in qib_init_7322_variables()
6424 struct qib_devdata *dd = ppd->dd; in qib_7322_getsendbuf() local
6428 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx; in qib_7322_getsendbuf()
6431 if ((plen + 1) > dd->piosize2kmax_dwords) in qib_7322_getsendbuf()
6432 first = dd->piobcnt2k; in qib_7322_getsendbuf()
6435 last = dd->cspec->lastbuf_for_pio; in qib_7322_getsendbuf()
6437 return qib_getsendbuf_range(dd, pbufnum, first, last); in qib_7322_getsendbuf()
6509 struct qib_devdata *dd = ppd->dd; in init_sdma_7322_regs() local
6521 if (dd->num_pports) in init_sdma_7322_regs()
6522 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ in init_sdma_7322_regs()
6524 n = dd->cspec->sdmabufcnt; /* failsafe for init */ in init_sdma_7322_regs()
6525 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) - in init_sdma_7322_regs()
6526 ((dd->num_pports == 1 || ppd->port == 2) ? n : in init_sdma_7322_regs()
6527 dd->cspec->sdmabufcnt); in init_sdma_7322_regs()
6548 struct qib_devdata *dd = ppd->dd; in qib_sdma_7322_gethead() local
6557 (dd->flags & QIB_HAS_SDMA_TIMEOUT); in qib_sdma_7322_gethead()
6633 static void qib_7322_initvl15_bufs(struct qib_devdata *dd) in qib_7322_initvl15_bufs() argument
6637 vl15bufs = dd->piobcnt2k + dd->piobcnt4k; in qib_7322_initvl15_bufs()
6638 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS, in qib_7322_initvl15_bufs()
6645 if (rcd->dd->num_pports > 1) { in qib_7322_init_ctxt()
6653 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; in qib_7322_init_ctxt()
6660 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start, in qib_7322_txchk_change() argument
6687 le64_to_cpu(dd->pioavailregs_dma[i]); in qib_7322_txchk_change()
6702 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in qib_7322_txchk_change()
6714 clear_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
6724 qib_read_kreg32(dd, kr_scratch); in qib_7322_txchk_change()
6726 set_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
6732 set_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
6733 clear_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
6735 spin_lock_irqsave(&dd->uctxt_lock, flags); in qib_7322_txchk_change()
6737 for (i = dd->first_user_ctxt; in qib_7322_txchk_change()
6738 dd->cspec->updthresh != dd->cspec->updthresh_dflt in qib_7322_txchk_change()
6739 && i < dd->cfgctxts; i++) in qib_7322_txchk_change()
6740 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt && in qib_7322_txchk_change()
6741 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1) in qib_7322_txchk_change()
6742 < dd->cspec->updthresh_dflt) in qib_7322_txchk_change()
6744 spin_unlock_irqrestore(&dd->uctxt_lock, flags); in qib_7322_txchk_change()
6745 if (i == dd->cfgctxts) { in qib_7322_txchk_change()
6746 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
6747 dd->cspec->updthresh = dd->cspec->updthresh_dflt; in qib_7322_txchk_change()
6748 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
6749 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
6752 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
6753 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in qib_7322_txchk_change()
6760 clear_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
6761 set_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
6763 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
6765 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { in qib_7322_txchk_change()
6766 dd->cspec->updthresh = (rcd->piocnt / in qib_7322_txchk_change()
6768 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
6769 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
6772 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
6773 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in qib_7322_txchk_change()
6775 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
6783 qib_write_kreg(dd, kr_sendcheckmask + i, in qib_7322_txchk_change()
6784 dd->cspec->sendchkenable[i]); in qib_7322_txchk_change()
6787 qib_write_kreg(dd, kr_sendgrhcheckmask + i, in qib_7322_txchk_change()
6788 dd->cspec->sendgrhchk[i]); in qib_7322_txchk_change()
6789 qib_write_kreg(dd, kr_sendibpktmask + i, in qib_7322_txchk_change()
6790 dd->cspec->sendibchk[i]); in qib_7322_txchk_change()
6797 qib_read_kreg32(dd, kr_scratch); in qib_7322_txchk_change()
6802 static void writescratch(struct qib_devdata *dd, u32 val) in writescratch() argument
6804 qib_write_kreg(dd, kr_scratch, val); in writescratch()
6808 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum) in qib_7322_tempsense_rd() argument
6827 struct qib_devdata *dd; in qib_init_iba7322_funcs() local
6831 dd = qib_alloc_devdata(pdev, in qib_init_iba7322_funcs()
6835 if (IS_ERR(dd)) in qib_init_iba7322_funcs()
6838 dd->f_bringup_serdes = qib_7322_bringup_serdes; in qib_init_iba7322_funcs()
6839 dd->f_cleanup = qib_setup_7322_cleanup; in qib_init_iba7322_funcs()
6840 dd->f_clear_tids = qib_7322_clear_tids; in qib_init_iba7322_funcs()
6841 dd->f_free_irq = qib_7322_free_irq; in qib_init_iba7322_funcs()
6842 dd->f_get_base_info = qib_7322_get_base_info; in qib_init_iba7322_funcs()
6843 dd->f_get_msgheader = qib_7322_get_msgheader; in qib_init_iba7322_funcs()
6844 dd->f_getsendbuf = qib_7322_getsendbuf; in qib_init_iba7322_funcs()
6845 dd->f_gpio_mod = gpio_7322_mod; in qib_init_iba7322_funcs()
6846 dd->f_eeprom_wen = qib_7322_eeprom_wen; in qib_init_iba7322_funcs()
6847 dd->f_hdrqempty = qib_7322_hdrqempty; in qib_init_iba7322_funcs()
6848 dd->f_ib_updown = qib_7322_ib_updown; in qib_init_iba7322_funcs()
6849 dd->f_init_ctxt = qib_7322_init_ctxt; in qib_init_iba7322_funcs()
6850 dd->f_initvl15_bufs = qib_7322_initvl15_bufs; in qib_init_iba7322_funcs()
6851 dd->f_intr_fallback = qib_7322_intr_fallback; in qib_init_iba7322_funcs()
6852 dd->f_late_initreg = qib_late_7322_initreg; in qib_init_iba7322_funcs()
6853 dd->f_setpbc_control = qib_7322_setpbc_control; in qib_init_iba7322_funcs()
6854 dd->f_portcntr = qib_portcntr_7322; in qib_init_iba7322_funcs()
6855 dd->f_put_tid = qib_7322_put_tid; in qib_init_iba7322_funcs()
6856 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes; in qib_init_iba7322_funcs()
6857 dd->f_rcvctrl = rcvctrl_7322_mod; in qib_init_iba7322_funcs()
6858 dd->f_read_cntrs = qib_read_7322cntrs; in qib_init_iba7322_funcs()
6859 dd->f_read_portcntrs = qib_read_7322portcntrs; in qib_init_iba7322_funcs()
6860 dd->f_reset = qib_do_7322_reset; in qib_init_iba7322_funcs()
6861 dd->f_init_sdma_regs = init_sdma_7322_regs; in qib_init_iba7322_funcs()
6862 dd->f_sdma_busy = qib_sdma_7322_busy; in qib_init_iba7322_funcs()
6863 dd->f_sdma_gethead = qib_sdma_7322_gethead; in qib_init_iba7322_funcs()
6864 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl; in qib_init_iba7322_funcs()
6865 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt; in qib_init_iba7322_funcs()
6866 dd->f_sdma_update_tail = qib_sdma_update_7322_tail; in qib_init_iba7322_funcs()
6867 dd->f_sendctrl = sendctrl_7322_mod; in qib_init_iba7322_funcs()
6868 dd->f_set_armlaunch = qib_set_7322_armlaunch; in qib_init_iba7322_funcs()
6869 dd->f_set_cntr_sample = qib_set_cntr_7322_sample; in qib_init_iba7322_funcs()
6870 dd->f_iblink_state = qib_7322_iblink_state; in qib_init_iba7322_funcs()
6871 dd->f_ibphys_portstate = qib_7322_phys_portstate; in qib_init_iba7322_funcs()
6872 dd->f_get_ib_cfg = qib_7322_get_ib_cfg; in qib_init_iba7322_funcs()
6873 dd->f_set_ib_cfg = qib_7322_set_ib_cfg; in qib_init_iba7322_funcs()
6874 dd->f_set_ib_loopback = qib_7322_set_loopback; in qib_init_iba7322_funcs()
6875 dd->f_get_ib_table = qib_7322_get_ib_table; in qib_init_iba7322_funcs()
6876 dd->f_set_ib_table = qib_7322_set_ib_table; in qib_init_iba7322_funcs()
6877 dd->f_set_intr_state = qib_7322_set_intr_state; in qib_init_iba7322_funcs()
6878 dd->f_setextled = qib_setup_7322_setextled; in qib_init_iba7322_funcs()
6879 dd->f_txchk_change = qib_7322_txchk_change; in qib_init_iba7322_funcs()
6880 dd->f_update_usrhead = qib_update_7322_usrhead; in qib_init_iba7322_funcs()
6881 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr; in qib_init_iba7322_funcs()
6882 dd->f_xgxs_reset = qib_7322_mini_pcs_reset; in qib_init_iba7322_funcs()
6883 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up; in qib_init_iba7322_funcs()
6884 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up; in qib_init_iba7322_funcs()
6885 dd->f_sdma_init_early = qib_7322_sdma_init_early; in qib_init_iba7322_funcs()
6886 dd->f_writescratch = writescratch; in qib_init_iba7322_funcs()
6887 dd->f_tempsense_rd = qib_7322_tempsense_rd; in qib_init_iba7322_funcs()
6894 ret = qib_pcie_ddinit(dd, pdev, ent); in qib_init_iba7322_funcs()
6899 ret = qib_init_7322_variables(dd); in qib_init_iba7322_funcs()
6903 if (qib_mini_init || !dd->num_pports) in qib_init_iba7322_funcs()
6912 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table); in qib_init_iba7322_funcs()
6915 irq_table[i].port <= dd->num_pports) || in qib_init_iba7322_funcs()
6917 dd->rcd[i - ARRAY_SIZE(irq_table)])) in qib_init_iba7322_funcs()
6921 actual_cnt -= dd->num_pports; in qib_init_iba7322_funcs()
6924 dd->cspec->msix_entries = kmalloc(tabsize * in qib_init_iba7322_funcs()
6926 if (!dd->cspec->msix_entries) { in qib_init_iba7322_funcs()
6927 qib_dev_err(dd, "No memory for MSIx table\n"); in qib_init_iba7322_funcs()
6931 dd->cspec->msix_entries[i].msix.entry = i; in qib_init_iba7322_funcs()
6933 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries)) in qib_init_iba7322_funcs()
6934 qib_dev_err(dd, in qib_init_iba7322_funcs()
6937 dd->cspec->num_msix_entries = tabsize; in qib_init_iba7322_funcs()
6940 qib_setup_7322_interrupt(dd, 1); in qib_init_iba7322_funcs()
6943 qib_write_kreg(dd, kr_hwdiagctrl, 0); in qib_init_iba7322_funcs()
6948 qib_pcie_ddcleanup(dd); in qib_init_iba7322_funcs()
6950 qib_free_devdata(dd); in qib_init_iba7322_funcs()
6951 dd = ERR_PTR(ret); in qib_init_iba7322_funcs()
6953 return dd; in qib_init_iba7322_funcs()
6977 struct qib_devdata *dd = ppd->dd; in set_txdds() local
6989 regidx += (dd->palign / sizeof(u64)); in set_txdds()
6995 qib_write_kreg(dd, regidx, pack_ent); in set_txdds()
6997 qib_write_kreg(ppd->dd, kr_scratch, 0); in set_txdds()
7255 *sdr_dds = txdds_sdr + ppd->dd->board_atten; in find_best_ent()
7256 *ddr_dds = txdds_ddr + ppd->dd->board_atten; in find_best_ent()
7257 *qdr_dds = txdds_qdr + ppd->dd->board_atten; in find_best_ent()
7284 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) && in find_best_ent()
7289 ppd->dd->unit, ppd->port, idx); in find_best_ent()
7311 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override) in init_txdds_table()
7350 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr, in ahb_mod() argument
7358 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC); in ahb_mod()
7361 qib_write_kreg(dd, KR_AHB_ACC, acc); in ahb_mod()
7364 trans = qib_read_kreg64(dd, KR_AHB_TRANS); in ahb_mod()
7369 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES); in ahb_mod()
7380 qib_write_kreg(dd, KR_AHB_TRANS, trans); in ahb_mod()
7383 trans = qib_read_kreg64(dd, KR_AHB_TRANS); in ahb_mod()
7388 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n", in ahb_mod()
7393 trans = qib_read_kreg64(dd, KR_AHB_TRANS); in ahb_mod()
7403 qib_write_kreg(dd, KR_AHB_TRANS, trans); in ahb_mod()
7406 trans = qib_read_kreg64(dd, KR_AHB_TRANS); in ahb_mod()
7411 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n", in ahb_mod()
7418 qib_write_kreg(dd, KR_AHB_ACC, prev_acc); in ahb_mod()
7425 struct qib_devdata *dd = ppd->dd; in ibsd_wr_allchans() local
7430 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, in ibsd_wr_allchans()
7432 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in ibsd_wr_allchans()
7444 ppd->dd->unit, ppd->port); in serdes_7322_los_enable()
7448 ppd->dd->unit, ppd->port); in serdes_7322_los_enable()
7457 if (ppd->dd->cspec->r1) in serdes_7322_init()
7489 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; in serdes_7322_init_old()
7493 le_val = IS_QME(ppd->dd) ? 0 : 1; in serdes_7322_init_old()
7497 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); in serdes_7322_init_old()
7504 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); in serdes_7322_init_old()
7505 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); in serdes_7322_init_old()
7506 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); in serdes_7322_init_old()
7507 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); in serdes_7322_init_old()
7510 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); in serdes_7322_init_old()
7511 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); in serdes_7322_init_old()
7512 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); in serdes_7322_init_old()
7513 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); in serdes_7322_init_old()
7516 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); in serdes_7322_init_old()
7532 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_old()
7542 ppd->dd->cspec->r1 ? in serdes_7322_init_old()
7552 if (!ppd->dd->cspec->r1) { in serdes_7322_init_old()
7570 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); in serdes_7322_init_new()
7612 if (!ppd->dd->cspec->r1) { in serdes_7322_init_new()
7638 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); in serdes_7322_init_new()
7639 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); in serdes_7322_init_new()
7640 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); in serdes_7322_init_new()
7641 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); in serdes_7322_init_new()
7644 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); in serdes_7322_init_new()
7645 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); in serdes_7322_init_new()
7646 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); in serdes_7322_init_new()
7647 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); in serdes_7322_init_new()
7650 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); in serdes_7322_init_new()
7674 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), in serdes_7322_init_new()
7687 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), in serdes_7322_init_new()
7702 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; in serdes_7322_init_new()
7712 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_new()
7733 ppd->dd->cspec->r1 ? in serdes_7322_init_new()
7763 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in set_man_code()
7771 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in set_man_mode_h1()
7774 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in set_man_mode_h1()
7781 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
7783 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
7785 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
7787 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
7848 if (!ppd->dd->cspec->r1) in force_h1()
7870 static int qib_r_grab(struct qib_devdata *dd) in qib_r_grab() argument
7874 qib_write_kreg(dd, kr_r_access, val); in qib_r_grab()
7875 qib_read_kreg32(dd, kr_scratch); in qib_r_grab()
7882 static int qib_r_wait_for_rdy(struct qib_devdata *dd) in qib_r_wait_for_rdy() argument
7887 val = qib_read_kreg32(dd, kr_r_access); in qib_r_wait_for_rdy()
7894 static int qib_r_shift(struct qib_devdata *dd, int bisten, in qib_r_shift() argument
7902 ret = qib_r_wait_for_rdy(dd); in qib_r_shift()
7915 qib_write_kreg(dd, kr_r_access, val); in qib_r_shift()
7916 qib_read_kreg32(dd, kr_scratch); in qib_r_shift()
7917 ret = qib_r_wait_for_rdy(dd); in qib_r_shift()
7923 qib_write_kreg(dd, kr_r_access, val); in qib_r_shift()
7924 qib_read_kreg32(dd, kr_scratch); in qib_r_shift()
7925 ret = qib_r_wait_for_rdy(dd); in qib_r_shift()
7933 static int qib_r_update(struct qib_devdata *dd, int bisten) in qib_r_update() argument
7939 ret = qib_r_wait_for_rdy(dd); in qib_r_update()
7941 qib_write_kreg(dd, kr_r_access, val); in qib_r_update()
7942 qib_read_kreg32(dd, kr_scratch); in qib_r_update()
8045 struct qib_devdata *dd = ppd->dd; in setup_7322_link_recovery() local
8047 if (!ppd->dd->cspec->r1) in setup_7322_link_recovery()
8050 dd->cspec->recovery_ports_initted++; in setup_7322_link_recovery()
8053 if (!both && dd->cspec->recovery_ports_initted == 1) { in setup_7322_link_recovery()
8061 if (qib_r_grab(dd) < 0 || in setup_7322_link_recovery()
8062 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 || in setup_7322_link_recovery()
8063 qib_r_update(dd, BISTEN_ETM) < 0 || in setup_7322_link_recovery()
8064 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 || in setup_7322_link_recovery()
8065 qib_r_update(dd, BISTEN_AT) < 0 || in setup_7322_link_recovery()
8066 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL, in setup_7322_link_recovery()
8068 qib_r_update(dd, BISTEN_PORT_SEL) < 0 || in setup_7322_link_recovery()
8069 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 || in setup_7322_link_recovery()
8070 qib_r_update(dd, BISTEN_AT) < 0 || in setup_7322_link_recovery()
8071 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 || in setup_7322_link_recovery()
8072 qib_r_update(dd, BISTEN_ETM) < 0) in setup_7322_link_recovery()
8073 qib_dev_err(dd, "Failed IB link recovery setup\n"); in setup_7322_link_recovery()
8078 struct qib_devdata *dd = ppd->dd; in check_7322_rxe_status() local
8081 if (dd->cspec->recovery_ports_initted != 1) in check_7322_rxe_status()
8083 qib_write_kreg(dd, kr_control, dd->control | in check_7322_rxe_status()
8085 (void)qib_read_kreg64(dd, kr_scratch); in check_7322_rxe_status()
8087 fmask = qib_read_kreg64(dd, kr_act_fmask); in check_7322_rxe_status()
8094 ppd->dd->cspec->stay_in_freeze = 1; in check_7322_rxe_status()
8095 qib_7322_set_intr_state(ppd->dd, 0); in check_7322_rxe_status()
8096 qib_write_kreg(dd, kr_fmask, 0ULL); in check_7322_rxe_status()
8097 qib_dev_err(dd, "HCA unusable until powercycled\n"); in check_7322_rxe_status()
8101 qib_write_kreg(ppd->dd, kr_hwerrclear, in check_7322_rxe_status()
8105 qib_write_kreg(dd, kr_control, dd->control); in check_7322_rxe_status()
8106 qib_read_kreg32(dd, kr_scratch); in check_7322_rxe_status()
8113 qib_read_kreg32(dd, kr_scratch); in check_7322_rxe_status()