Lines Matching refs:iommu
245 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
249 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
250 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
254 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
256 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
257 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
258 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
261 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
265 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
266 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
270 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
272 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
273 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
289 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
291 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
292 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; in iommu_set_exclusion_range()
295 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
299 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
303 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
308 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
312 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
316 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
321 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
325 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
327 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
330 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
334 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
336 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
339 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
343 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
346 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
350 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
352 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
355 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
358 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
361 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
362 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
365 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
384 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
386 if (iommu->mmio_base) in iommu_unmap_mmio_space()
387 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
388 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); in iommu_unmap_mmio_space()
514 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
522 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED; in alloc_command_buffer()
531 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
533 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
535 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
536 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
538 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
545 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
549 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
551 entry = (u64)virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
554 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
557 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
558 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED); in iommu_enable_command_buffer()
561 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
563 free_pages((unsigned long)iommu->cmd_buf, in free_command_buffer()
564 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED))); in free_command_buffer()
568 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
570 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_event_buffer()
573 if (iommu->evt_buf == NULL) in alloc_event_buffer()
576 iommu->evt_buf_size = EVT_BUFFER_SIZE; in alloc_event_buffer()
578 return iommu->evt_buf; in alloc_event_buffer()
581 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
585 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
587 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
589 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
593 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
594 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
596 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
599 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
601 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
605 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu) in alloc_ppr_log() argument
607 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_ppr_log()
610 if (iommu->ppr_log == NULL) in alloc_ppr_log()
613 return iommu->ppr_log; in alloc_ppr_log()
616 static void iommu_enable_ppr_log(struct amd_iommu *iommu) in iommu_enable_ppr_log() argument
620 if (iommu->ppr_log == NULL) in iommu_enable_ppr_log()
623 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in iommu_enable_ppr_log()
625 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, in iommu_enable_ppr_log()
629 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_enable_ppr_log()
630 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_enable_ppr_log()
632 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN); in iommu_enable_ppr_log()
633 iommu_feature_enable(iommu, CONTROL_PPR_EN); in iommu_enable_ppr_log()
636 static void __init free_ppr_log(struct amd_iommu *iommu) in free_ppr_log() argument
638 if (iommu->ppr_log == NULL) in free_ppr_log()
641 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); in free_ppr_log()
644 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
646 if (!iommu_feature(iommu, FEATURE_GT)) in iommu_enable_gt()
649 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
682 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) in set_iommu_for_device() argument
684 amd_iommu_rlookup_table[devid] = iommu; in set_iommu_for_device()
691 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
711 set_iommu_for_device(iommu, devid); in set_dev_entry_from_acpi()
780 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; in set_device_exclusion_range() local
785 if (iommu) { in set_device_exclusion_range()
792 iommu->exclusion_start = m->range_start; in set_device_exclusion_range()
793 iommu->exclusion_length = m->range_length; in set_device_exclusion_range()
801 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
820 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
836 PCI_BUS_NUM(iommu->first_device), in init_iommu_from_acpi()
837 PCI_SLOT(iommu->first_device), in init_iommu_from_acpi()
838 PCI_FUNC(iommu->first_device), in init_iommu_from_acpi()
839 PCI_BUS_NUM(iommu->last_device), in init_iommu_from_acpi()
840 PCI_SLOT(iommu->last_device), in init_iommu_from_acpi()
841 PCI_FUNC(iommu->last_device), in init_iommu_from_acpi()
844 for (dev_i = iommu->first_device; in init_iommu_from_acpi()
845 dev_i <= iommu->last_device; ++dev_i) in init_iommu_from_acpi()
846 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
859 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
889 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
890 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
922 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
950 set_dev_entry_from_acpi(iommu, in init_iommu_from_acpi()
953 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
980 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
997 static int __init init_iommu_devices(struct amd_iommu *iommu) in init_iommu_devices() argument
1001 for (i = iommu->first_device; i <= iommu->last_device; ++i) in init_iommu_devices()
1002 set_iommu_for_device(iommu, i); in init_iommu_devices()
1007 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
1009 free_command_buffer(iommu); in free_iommu_one()
1010 free_event_buffer(iommu); in free_iommu_one()
1011 free_ppr_log(iommu); in free_iommu_one()
1012 iommu_unmap_mmio_space(iommu); in free_iommu_one()
1017 struct amd_iommu *iommu, *next; in free_iommu_all() local
1019 for_each_iommu_safe(iommu, next) { in free_iommu_all()
1020 list_del(&iommu->list); in free_iommu_all()
1021 free_iommu_one(iommu); in free_iommu_all()
1022 kfree(iommu); in free_iommu_all()
1032 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1041 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1042 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1048 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1050 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1052 dev_name(&iommu->dev->dev)); in amd_iommu_erratum_746_workaround()
1055 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1063 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) in init_iommu_one() argument
1067 spin_lock_init(&iommu->lock); in init_iommu_one()
1070 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1071 iommu->index = amd_iommus_present++; in init_iommu_one()
1073 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1079 amd_iommus[iommu->index] = iommu; in init_iommu_one()
1084 iommu->devid = h->devid; in init_iommu_one()
1085 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1086 iommu->pci_seg = h->pci_seg; in init_iommu_one()
1087 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1088 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); in init_iommu_one()
1089 if (!iommu->mmio_base) in init_iommu_one()
1092 iommu->cmd_buf = alloc_command_buffer(iommu); in init_iommu_one()
1093 if (!iommu->cmd_buf) in init_iommu_one()
1096 iommu->evt_buf = alloc_event_buffer(iommu); in init_iommu_one()
1097 if (!iommu->evt_buf) in init_iommu_one()
1100 iommu->int_enabled = false; in init_iommu_one()
1102 ret = init_iommu_from_acpi(iommu, h); in init_iommu_one()
1110 amd_iommu_rlookup_table[iommu->devid] = NULL; in init_iommu_one()
1112 init_iommu_devices(iommu); in init_iommu_one()
1125 struct amd_iommu *iommu; in init_iommu_all() local
1144 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1145 if (iommu == NULL) in init_iommu_all()
1148 ret = init_iommu_one(iommu, h); in init_iommu_all()
1163 static int iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
1165 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
1168 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
1169 iommu->devid & 0xff); in iommu_init_pci()
1170 if (!iommu->dev) in iommu_init_pci()
1173 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
1174 &iommu->cap); in iommu_init_pci()
1175 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, in iommu_init_pci()
1177 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, in iommu_init_pci()
1180 iommu->first_device = PCI_DEVID(MMIO_GET_BUS(range), in iommu_init_pci()
1182 iommu->last_device = PCI_DEVID(MMIO_GET_BUS(range), in iommu_init_pci()
1185 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
1189 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES); in iommu_init_pci()
1190 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4); in iommu_init_pci()
1192 iommu->features = ((u64)high << 32) | low; in iommu_init_pci()
1194 if (iommu_feature(iommu, FEATURE_GT)) { in iommu_init_pci()
1199 shift = iommu->features & FEATURE_PASID_MASK; in iommu_init_pci()
1205 glxval = iommu->features & FEATURE_GLXVAL_MASK; in iommu_init_pci()
1214 if (iommu_feature(iommu, FEATURE_GT) && in iommu_init_pci()
1215 iommu_feature(iommu, FEATURE_PPR)) { in iommu_init_pci()
1216 iommu->is_iommu_v2 = true; in iommu_init_pci()
1220 if (iommu_feature(iommu, FEATURE_PPR)) { in iommu_init_pci()
1221 iommu->ppr_log = alloc_ppr_log(iommu); in iommu_init_pci()
1222 if (!iommu->ppr_log) in iommu_init_pci()
1226 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) in iommu_init_pci()
1229 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
1232 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number, in iommu_init_pci()
1240 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
1241 &iommu->stored_addr_lo); in iommu_init_pci()
1242 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
1243 &iommu->stored_addr_hi); in iommu_init_pci()
1246 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
1250 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
1253 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
1256 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
1258 return pci_enable_device(iommu->dev); in iommu_init_pci()
1267 struct amd_iommu *iommu; in print_iommu_info() local
1269 for_each_iommu(iommu) { in print_iommu_info()
1273 dev_name(&iommu->dev->dev), iommu->cap_ptr); in print_iommu_info()
1275 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { in print_iommu_info()
1278 if (iommu_feature(iommu, (1ULL << i))) in print_iommu_info()
1290 struct amd_iommu *iommu; in amd_iommu_init_pci() local
1293 for_each_iommu(iommu) { in amd_iommu_init_pci()
1294 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
1315 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
1319 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
1323 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
1327 iommu); in iommu_setup_msi()
1330 pci_disable_msi(iommu->dev); in iommu_setup_msi()
1334 iommu->int_enabled = true; in iommu_setup_msi()
1339 static int iommu_init_msi(struct amd_iommu *iommu) in iommu_init_msi() argument
1343 if (iommu->int_enabled) in iommu_init_msi()
1346 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) in iommu_init_msi()
1347 ret = iommu_setup_msi(iommu); in iommu_init_msi()
1355 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_msi()
1357 if (iommu->ppr_log != NULL) in iommu_init_msi()
1358 iommu_feature_enable(iommu, CONTROL_PPFINT_EN); in iommu_init_msi()
1507 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
1509 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
1510 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
1511 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
1513 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
1514 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
1515 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
1517 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
1518 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
1519 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
1521 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
1522 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
1523 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
1528 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
1531 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
1534 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
1538 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
1541 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
1558 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
1559 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
1560 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
1561 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
1566 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
1570 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
1573 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
1574 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
1583 struct amd_iommu *iommu; in early_enable_iommus() local
1585 for_each_iommu(iommu) { in early_enable_iommus()
1586 iommu_disable(iommu); in early_enable_iommus()
1587 iommu_init_flags(iommu); in early_enable_iommus()
1588 iommu_set_device_table(iommu); in early_enable_iommus()
1589 iommu_enable_command_buffer(iommu); in early_enable_iommus()
1590 iommu_enable_event_buffer(iommu); in early_enable_iommus()
1591 iommu_set_exclusion_range(iommu); in early_enable_iommus()
1592 iommu_enable(iommu); in early_enable_iommus()
1593 iommu_flush_all_caches(iommu); in early_enable_iommus()
1599 struct amd_iommu *iommu; in enable_iommus_v2() local
1601 for_each_iommu(iommu) { in enable_iommus_v2()
1602 iommu_enable_ppr_log(iommu); in enable_iommus_v2()
1603 iommu_enable_gt(iommu); in enable_iommus_v2()
1616 struct amd_iommu *iommu; in disable_iommus() local
1618 for_each_iommu(iommu) in disable_iommus()
1619 iommu_disable(iommu); in disable_iommus()
1629 struct amd_iommu *iommu; in amd_iommu_resume() local
1631 for_each_iommu(iommu) in amd_iommu_resume()
1632 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
1895 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
1898 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
1899 ret = iommu_init_msi(iommu); in amd_iommu_enable_interrupts()
1936 struct amd_iommu *iommu; in amd_iommu_init_dma() local
1949 for_each_iommu(iommu) in amd_iommu_init_dma()
1950 iommu_flush_all_caches(iommu); in amd_iommu_init_dma()
2093 struct amd_iommu *iommu; in amd_iommu_init() local
2096 for_each_iommu(iommu) in amd_iommu_init()
2097 iommu_flush_all_caches(iommu); in amd_iommu_init()
2127 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()