160 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)  in dib8000_read_word()  argument
164 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {  in dib8000_read_word()
169 	state->i2c_write_buffer[0] = reg >> 8;  in dib8000_read_word()
170 	state->i2c_write_buffer[1] = reg & 0xff;  in dib8000_read_word()
172 	memset(state->msg, 0, 2 * sizeof(struct i2c_msg));  in dib8000_read_word()
173 	state->msg[0].addr = state->i2c.addr >> 1;  in dib8000_read_word()
174 	state->msg[0].flags = 0;  in dib8000_read_word()
175 	state->msg[0].buf = state->i2c_write_buffer;  in dib8000_read_word()
176 	state->msg[0].len = 2;  in dib8000_read_word()
177 	state->msg[1].addr = state->i2c.addr >> 1;  in dib8000_read_word()
178 	state->msg[1].flags = I2C_M_RD;  in dib8000_read_word()
179 	state->msg[1].buf = state->i2c_read_buffer;  in dib8000_read_word()
180 	state->msg[1].len = 2;  in dib8000_read_word()
182 	if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)  in dib8000_read_word()
185 	ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];  in dib8000_read_word()
186 	mutex_unlock(&state->i2c_buffer_lock);  in dib8000_read_word()
191 static u32 dib8000_read32(struct dib8000_state *state, u16 reg)  in dib8000_read32()  argument
195 	rw[0] = dib8000_read_word(state, reg + 0);  in dib8000_read32()
196 	rw[1] = dib8000_read_word(state, reg + 1);  in dib8000_read32()
223 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)  in dib8000_write_word()  argument
227 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {  in dib8000_write_word()
232 	state->i2c_write_buffer[0] = (reg >> 8) & 0xff;  in dib8000_write_word()
233 	state->i2c_write_buffer[1] = reg & 0xff;  in dib8000_write_word()
234 	state->i2c_write_buffer[2] = (val >> 8) & 0xff;  in dib8000_write_word()
235 	state->i2c_write_buffer[3] = val & 0xff;  in dib8000_write_word()
237 	memset(&state->msg[0], 0, sizeof(struct i2c_msg));  in dib8000_write_word()
238 	state->msg[0].addr = state->i2c.addr >> 1;  in dib8000_write_word()
239 	state->msg[0].flags = 0;  in dib8000_write_word()
240 	state->msg[0].buf = state->i2c_write_buffer;  in dib8000_write_word()
241 	state->msg[0].len = 4;  in dib8000_write_word()
243 	ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?  in dib8000_write_word()
245 	mutex_unlock(&state->i2c_buffer_lock);  in dib8000_write_word()
351 static u16 fft_to_mode(struct dib8000_state *state)  in fft_to_mode()  argument
354 	switch (state->fe[0]->dtv_property_cache.transmission_mode) {  in fft_to_mode()
370 static void dib8000_set_acquisition_mode(struct dib8000_state *state)  in dib8000_set_acquisition_mode()  argument
372 	u16 nud = dib8000_read_word(state, 298);  in dib8000_set_acquisition_mode()
375 	dib8000_write_word(state, 298, nud);  in dib8000_set_acquisition_mode()
379 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_output_mode()  local
382 	state->output_mode = mode;  in dib8000_set_output_mode()
385 	smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);  in dib8000_set_output_mode()
388 			&state->fe[0], mode);  in dib8000_set_output_mode()
401 		if (state->cfg.hostbus_diversity) {  in dib8000_set_output_mode()
418 		dib8000_set_acquisition_mode(state);  in dib8000_set_output_mode()
423 				&state->fe[0]);  in dib8000_set_output_mode()
427 	if (state->cfg.output_mpeg2_in_188_bytes)  in dib8000_set_output_mode()
430 	dib8000_write_word(state, 299, smo_mode);  in dib8000_set_output_mode()
431 	dib8000_write_word(state, 300, fifo_threshold);	/* synchronous fread */  in dib8000_set_output_mode()
432 	dib8000_write_word(state, 1286, outreg);  in dib8000_set_output_mode()
433 	dib8000_write_word(state, 1291, sram);  in dib8000_set_output_mode()
440 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_diversity_in()  local
441 	u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0;  in dib8000_set_diversity_in()
444 	if (!state->differential_constellation) {  in dib8000_set_diversity_in()
445 		dib8000_write_word(state, 272, 1 << 9);	//dvsy_off_lmod4 = 1  in dib8000_set_diversity_in()
446 		dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2);	// sync_enable = 1; comb_mode = 2  in dib8000_set_diversity_in()
448 		dib8000_write_word(state, 272, 0);	//dvsy_off_lmod4 = 0  in dib8000_set_diversity_in()
449 		dib8000_write_word(state, 273, sync_wait);	// sync_enable = 0; comb_mode = 0  in dib8000_set_diversity_in()
451 	state->diversity_onoff = onoff;  in dib8000_set_diversity_in()
455 		dib8000_write_word(state, 270, 1);  in dib8000_set_diversity_in()
456 		dib8000_write_word(state, 271, 0);  in dib8000_set_diversity_in()
459 		dib8000_write_word(state, 270, 6);  in dib8000_set_diversity_in()
460 		dib8000_write_word(state, 271, 6);  in dib8000_set_diversity_in()
463 		dib8000_write_word(state, 270, 0);  in dib8000_set_diversity_in()
464 		dib8000_write_word(state, 271, 1);  in dib8000_set_diversity_in()
468 	if (state->revision == 0x8002) {  in dib8000_set_diversity_in()
469 		tmp = dib8000_read_word(state, 903);  in dib8000_set_diversity_in()
470 		dib8000_write_word(state, 903, tmp & ~(1 << 3));  in dib8000_set_diversity_in()
472 		dib8000_write_word(state, 903, tmp | (1 << 3));  in dib8000_set_diversity_in()
477 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)  in dib8000_set_power_mode()  argument
481 		reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,  in dib8000_set_power_mode()
484 	if (state->revision != 0x8090)  in dib8000_set_power_mode()
485 		reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;  in dib8000_set_power_mode()
487 		reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;  in dib8000_set_power_mode()
497 		if (state->revision != 0x8090)  in dib8000_set_power_mode()
503 		if (state->revision != 0x8090)  in dib8000_set_power_mode()
511 	dib8000_write_word(state, 774, reg_774);  in dib8000_set_power_mode()
512 	dib8000_write_word(state, 775, reg_775);  in dib8000_set_power_mode()
513 	dib8000_write_word(state, 776, reg_776);  in dib8000_set_power_mode()
514 	dib8000_write_word(state, 900, reg_900);  in dib8000_set_power_mode()
515 	dib8000_write_word(state, 1280, reg_1280);  in dib8000_set_power_mode()
518 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)  in dib8000_set_adc_state()  argument
521 	u16 reg, reg_907 = dib8000_read_word(state, 907);  in dib8000_set_adc_state()
522 	u16 reg_908 = dib8000_read_word(state, 908);  in dib8000_set_adc_state()
526 		if (state->revision != 0x8090) {  in dib8000_set_adc_state()
528 			ret |= dib8000_write_word(state, 908, reg_908);  in dib8000_set_adc_state()
531 			reg = dib8000_read_word(state, 1925);  in dib8000_set_adc_state()
533 			dib8000_write_word(state, 1925, reg |  in dib8000_set_adc_state()
537 			reg = dib8000_read_word(state, 1925);  in dib8000_set_adc_state()
540 			dib8000_write_word(state, 1925, reg & ~(1<<4));  in dib8000_set_adc_state()
542 			reg = dib8000_read_word(state, 921) & ~((0x3 << 14)  in dib8000_set_adc_state()
546 			dib8000_write_word(state, 921, reg | (1 << 14)  in dib8000_set_adc_state()
552 		if (state->revision == 0x8090) {  in dib8000_set_adc_state()
553 			reg = dib8000_read_word(state, 1925);  in dib8000_set_adc_state()
555 			dib8000_write_word(state, 1925,  in dib8000_set_adc_state()
583 	ret |= dib8000_write_word(state, 907, reg_907);  in dib8000_set_adc_state()
584 	ret |= dib8000_write_word(state, 908, reg_908);  in dib8000_set_adc_state()
591 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_bandwidth()  local
597 	if (state->timf == 0) {  in dib8000_set_bandwidth()
599 		timf = state->timf_default;  in dib8000_set_bandwidth()
602 		timf = state->timf;  in dib8000_set_bandwidth()
605 	dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));  in dib8000_set_bandwidth()
606 	dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));  in dib8000_set_bandwidth()
611 static int dib8000_sad_calib(struct dib8000_state *state)  in dib8000_sad_calib()  argument
615 	if (state->revision == 0x8090) {  in dib8000_sad_calib()
616 		dib8000_write_word(state, 922, (sad_sel << 2));  in dib8000_sad_calib()
617 		dib8000_write_word(state, 923, 2048);  in dib8000_sad_calib()
619 		dib8000_write_word(state, 922, (sad_sel << 2) | 0x1);  in dib8000_sad_calib()
620 		dib8000_write_word(state, 922, (sad_sel << 2));  in dib8000_sad_calib()
623 		dib8000_write_word(state, 923, (0 << 1) | (0 << 0));  in dib8000_sad_calib()
624 		dib8000_write_word(state, 924, 776);  in dib8000_sad_calib()
627 		dib8000_write_word(state, 923, (1 << 0));  in dib8000_sad_calib()
628 		dib8000_write_word(state, 923, (0 << 0));  in dib8000_sad_calib()
637 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_wbd_ref()  local
640 	state->wbd_ref = value;  in dib8000_set_wbd_ref()
641 	return dib8000_write_word(state, 106, value);  in dib8000_set_wbd_ref()
645 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_co…  in dib8000_reset_pll_common()  argument
648 	if (state->revision != 0x8090) {  in dib8000_reset_pll_common()
649 		dib8000_write_word(state, 23,  in dib8000_reset_pll_common()
651 		dib8000_write_word(state, 24,  in dib8000_reset_pll_common()
654 		dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));  in dib8000_reset_pll_common()
655 		dib8000_write_word(state, 24,  in dib8000_reset_pll_common()
658 	dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));  in dib8000_reset_pll_common()
659 	dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));  in dib8000_reset_pll_common()
660 	dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));  in dib8000_reset_pll_common()
662 	if (state->revision != 0x8090)  in dib8000_reset_pll_common()
663 		dib8000_write_word(state, 922, bw->sad_cfg);  in dib8000_reset_pll_common()
666 static void dib8000_reset_pll(struct dib8000_state *state)  in dib8000_reset_pll()  argument
668 	const struct dibx000_bandwidth_config *pll = state->cfg.pll;  in dib8000_reset_pll()
671 	if (state->revision != 0x8090) {  in dib8000_reset_pll()
672 		dib8000_write_word(state, 901,  in dib8000_reset_pll()
680 		dib8000_write_word(state, 902, clk_cfg1);  in dib8000_reset_pll()
682 		dib8000_write_word(state, 902, clk_cfg1);  in dib8000_reset_pll()
687 		if (state->cfg.pll->ADClkSrc == 0)  in dib8000_reset_pll()
688 			dib8000_write_word(state, 904,  in dib8000_reset_pll()
692 		else if (state->cfg.refclksel != 0)  in dib8000_reset_pll()
693 			dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |  in dib8000_reset_pll()
694 					((state->cfg.refclksel & 0x3) << 10) |  in dib8000_reset_pll()
698 			dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |  in dib8000_reset_pll()
702 		dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |  in dib8000_reset_pll()
706 		reg = dib8000_read_word(state, 1857);  in dib8000_reset_pll()
707 		dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));  in dib8000_reset_pll()
709 		reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */  in dib8000_reset_pll()
710 		dib8000_write_word(state, 1858, reg | 1);  in dib8000_reset_pll()
712 		dib8000_write_word(state, 904, (pll->modulo << 8));  in dib8000_reset_pll()
715 	dib8000_reset_pll_common(state, pll);  in dib8000_reset_pll()
721 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_update_pll()  local
722 	u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);  in dib8000_update_pll()
723 	u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;  in dib8000_update_pll()
735 	if (state->revision == 0x8090) {  in dib8000_update_pll()
737 		reg_1857 = dib8000_read_word(state, 1857);  in dib8000_update_pll()
739 		dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));  in dib8000_update_pll()
741 		dib8000_write_word(state, 1856, reg_1856 |  in dib8000_update_pll()
746 		internal = dib8000_read32(state, 23) / 1000;  in dib8000_update_pll()
753 		dib8000_write_word(state, 23,  in dib8000_update_pll()
755 		dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));  in dib8000_update_pll()
757 		dib8000_write_word(state, 1857, reg_1857 | (1 << 15));  in dib8000_update_pll()
759 		while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)  in dib8000_update_pll()
763 		reg_1856 = dib8000_read_word(state, 1856);  in dib8000_update_pll()
767 		if (bw != state->current_demod_bw) {  in dib8000_update_pll()
769 …dth Change %d MHz -> %d MHz (prediv: %d->%d)", state->current_demod_bw / 1000, bw / 1000, oldpredi…  in dib8000_update_pll()
771 			if (state->cfg.pll->pll_prediv != oldprediv) {  in dib8000_update_pll()
775 …ing for %d MHz Bandwidth (prediv: %d, ratio: %d)", bw/1000, state->cfg.pll->pll_prediv, state->cfg…  in dib8000_update_pll()
776 				dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */  in dib8000_update_pll()
777 				dib8000_reset_pll(state);  in dib8000_update_pll()
778 				dib8000_write_word(state, 898, 0x0004); /* sad */  in dib8000_update_pll()
780 				ratio = state->cfg.pll->pll_ratio;  in dib8000_update_pll()
782 			state->current_demod_bw = bw;  in dib8000_update_pll()
787 			dprintk("PLL: Update ratio (prediv: %d, ratio: %d)", state->cfg.pll->pll_prediv, ratio);  in dib8000_update_pll()
788 …dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL …  in dib8000_update_pll()
830 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_gpio()  local
831 	return dib8000_cfg_gpio(state, num, dir, val);  in dib8000_set_gpio()
971 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_reset()  local
973 	if ((state->revision = dib8000_identify(&state->i2c)) == 0)  in dib8000_reset()
977 	if (state->revision != 0x8090)  in dib8000_reset()
978 		dib8000_write_word(state, 1287, 0x0003);  in dib8000_reset()
980 	if (state->revision == 0x8000)  in dib8000_reset()
983 	dibx000_reset_i2c_master(&state->i2c_master);  in dib8000_reset()
985 	dib8000_set_power_mode(state, DIB8000_POWER_ALL);  in dib8000_reset()
988 	dib8000_set_adc_state(state, DIBX000_ADC_OFF);  in dib8000_reset()
991 	dib8000_write_word(state, 770, 0xffff);  in dib8000_reset()
992 	dib8000_write_word(state, 771, 0xffff);  in dib8000_reset()
993 	dib8000_write_word(state, 772, 0xfffc);  in dib8000_reset()
994 	if (state->revision == 0x8090)  in dib8000_reset()
995 		dib8000_write_word(state, 1280, 0x0045);  in dib8000_reset()
997 		dib8000_write_word(state, 1280, 0x004d);  in dib8000_reset()
998 	dib8000_write_word(state, 1281, 0x000c);  in dib8000_reset()
1000 	dib8000_write_word(state, 770, 0x0000);  in dib8000_reset()
1001 	dib8000_write_word(state, 771, 0x0000);  in dib8000_reset()
1002 	dib8000_write_word(state, 772, 0x0000);  in dib8000_reset()
1003 	dib8000_write_word(state, 898, 0x0004);	// sad  in dib8000_reset()
1004 	dib8000_write_word(state, 1280, 0x0000);  in dib8000_reset()
1005 	dib8000_write_word(state, 1281, 0x0000);  in dib8000_reset()
1008 	if (state->revision != 0x8090) {  in dib8000_reset()
1009 		if (state->cfg.drives)  in dib8000_reset()
1010 			dib8000_write_word(state, 906, state->cfg.drives);  in dib8000_reset()
1014 			dib8000_write_word(state, 906, 0x2d98);  in dib8000_reset()
1018 	dib8000_reset_pll(state);  in dib8000_reset()
1019 	if (state->revision != 0x8090)  in dib8000_reset()
1020 		dib8000_write_word(state, 898, 0x0004);  in dib8000_reset()
1022 	if (dib8000_reset_gpio(state) != 0)  in dib8000_reset()
1025 	if ((state->revision != 0x8090) &&  in dib8000_reset()
1029 	state->current_agc = NULL;  in dib8000_reset()
1033 	if (state->cfg.pll->ifreq == 0)  in dib8000_reset()
1034 		dib8000_write_word(state, 40, 0x0755);	/* P_iqc_corr_inh = 0 enable IQcorr block */  in dib8000_reset()
1036 		dib8000_write_word(state, 40, 0x1f55);	/* P_iqc_corr_inh = 1 disable IQcorr block */  in dib8000_reset()
1046 				dib8000_write_word(state, r, *n++);  in dib8000_reset()
1053 	state->isdbt_cfg_loaded = 0;  in dib8000_reset()
1056 	if ((state->revision != 8090) && (state->cfg.div_cfg != 0))  in dib8000_reset()
1057 		dib8000_write_word(state, 903, state->cfg.div_cfg);  in dib8000_reset()
1060 	dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));  in dib8000_reset()
1064 	dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);  in dib8000_reset()
1065 	dib8000_sad_calib(state);  in dib8000_reset()
1066 	if (state->revision != 0x8090)  in dib8000_reset()
1067 		dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);  in dib8000_reset()
1070 	dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));  in dib8000_reset()
1072 	dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);  in dib8000_reset()
1077 static void dib8000_restart_agc(struct dib8000_state *state)  in dib8000_restart_agc()  argument
1080 	dib8000_write_word(state, 770, 0x0a00);  in dib8000_restart_agc()
1081 	dib8000_write_word(state, 770, 0x0000);  in dib8000_restart_agc()
1084 static int dib8000_update_lna(struct dib8000_state *state)  in dib8000_update_lna()  argument
1088 	if (state->cfg.update_lna) {  in dib8000_update_lna()
1090 		dyn_gain = dib8000_read_word(state, 390);  in dib8000_update_lna()
1092 		if (state->cfg.update_lna(state->fe[0], dyn_gain)) {  in dib8000_update_lna()
1093 			dib8000_restart_agc(state);  in dib8000_update_lna()
1100 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)  in dib8000_set_agc_config()  argument
1106 	if (state->current_band == band && state->current_agc != NULL)  in dib8000_set_agc_config()
1108 	state->current_band = band;  in dib8000_set_agc_config()
1110 	for (i = 0; i < state->cfg.agc_config_count; i++)  in dib8000_set_agc_config()
1111 		if (state->cfg.agc[i].band_caps & band) {  in dib8000_set_agc_config()
1112 			agc = &state->cfg.agc[i];  in dib8000_set_agc_config()
1121 	state->current_agc = agc;  in dib8000_set_agc_config()
1124 	dib8000_write_word(state, 76, agc->setup);  in dib8000_set_agc_config()
1125 	dib8000_write_word(state, 77, agc->inv_gain);  in dib8000_set_agc_config()
1126 	dib8000_write_word(state, 78, agc->time_stabiliz);  in dib8000_set_agc_config()
1127 	dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);  in dib8000_set_agc_config()
1130 	dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);  in dib8000_set_agc_config()
1131 	dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);  in dib8000_set_agc_config()
1134 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag…  in dib8000_set_agc_config()
1137 	if (state->wbd_ref != 0)  in dib8000_set_agc_config()
1138 		dib8000_write_word(state, 106, state->wbd_ref);  in dib8000_set_agc_config()
1140 		dib8000_write_word(state, 106, agc->wbd_ref);  in dib8000_set_agc_config()
1142 	if (state->revision == 0x8090) {  in dib8000_set_agc_config()
1143 		reg = dib8000_read_word(state, 922) & (0x3 << 2);  in dib8000_set_agc_config()
1144 		dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));  in dib8000_set_agc_config()
1147 	dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));  in dib8000_set_agc_config()
1148 	dib8000_write_word(state, 108, agc->agc1_max);  in dib8000_set_agc_config()
1149 	dib8000_write_word(state, 109, agc->agc1_min);  in dib8000_set_agc_config()
1150 	dib8000_write_word(state, 110, agc->agc2_max);  in dib8000_set_agc_config()
1151 	dib8000_write_word(state, 111, agc->agc2_min);  in dib8000_set_agc_config()
1152 	dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);  in dib8000_set_agc_config()
1153 	dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);  in dib8000_set_agc_config()
1154 	dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);  in dib8000_set_agc_config()
1155 	dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);  in dib8000_set_agc_config()
1157 	dib8000_write_word(state, 75, agc->agc1_pt3);  in dib8000_set_agc_config()
1158 	if (state->revision != 0x8090)  in dib8000_set_agc_config()
1159 		dib8000_write_word(state, 923,  in dib8000_set_agc_config()
1160 				(dib8000_read_word(state, 923) & 0xffe3) |  in dib8000_set_agc_config()
1168 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_pwm_agc_reset()  local
1169 	dib8000_set_adc_state(state, DIBX000_ADC_ON);  in dib8000_pwm_agc_reset()
1170 …dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency /…  in dib8000_pwm_agc_reset()
1174 static int dib8000_agc_soft_split(struct dib8000_state *state)  in dib8000_agc_soft_split()  argument
1178 …if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split…  in dib8000_agc_soft_split()
1182 	agc = dib8000_read_word(state, 390);  in dib8000_agc_soft_split()
1184 	if (agc > state->current_agc->split.min_thres)  in dib8000_agc_soft_split()
1185 		split_offset = state->current_agc->split.min;  in dib8000_agc_soft_split()
1186 	else if (agc < state->current_agc->split.max_thres)  in dib8000_agc_soft_split()
1187 		split_offset = state->current_agc->split.max;  in dib8000_agc_soft_split()
1189 		split_offset = state->current_agc->split.max *  in dib8000_agc_soft_split()
1190 			(agc - state->current_agc->split.min_thres) /  in dib8000_agc_soft_split()
1191 			(state->current_agc->split.max_thres - state->current_agc->split.min_thres);  in dib8000_agc_soft_split()
1196 	dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);  in dib8000_agc_soft_split()
1202 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_agc_startup()  local
1203 	enum frontend_tune_state *tune_state = &state->tune_state;  in dib8000_agc_startup()
1211 		if (state->revision != 0x8090)  in dib8000_agc_startup()
1212 			dib8000_set_adc_state(state, DIBX000_ADC_ON);  in dib8000_agc_startup()
1214 			dib8000_set_power_mode(state, DIB8000_POWER_ALL);  in dib8000_agc_startup()
1216 			reg = dib8000_read_word(state, 1947)&0xff00;  in dib8000_agc_startup()
1217 			dib8000_write_word(state, 1946,  in dib8000_agc_startup()
1220 			dib8000_write_word(state, 1947, reg | (1<<14) |  in dib8000_agc_startup()
1224 			reg = dib8000_read_word(state, 1920);  in dib8000_agc_startup()
1225 			dib8000_write_word(state, 1920, (reg | 0x3) &  in dib8000_agc_startup()
1229 …if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequen…  in dib8000_agc_startup()
1231 			state->status = FE_STATUS_TUNE_FAILED;  in dib8000_agc_startup()
1241 		if (state->cfg.agc_control)  in dib8000_agc_startup()
1242 			state->cfg.agc_control(fe, 1);  in dib8000_agc_startup()
1244 		dib8000_restart_agc(state);  in dib8000_agc_startup()
1255 		if (dib8000_update_lna(state))  in dib8000_agc_startup()
1263 		dib8000_agc_soft_split(state);  in dib8000_agc_startup()
1265 		if (state->cfg.agc_control)  in dib8000_agc_startup()
1266 			state->cfg.agc_control(fe, 0);  in dib8000_agc_startup()
1271 		ret = dib8000_agc_soft_split(state);  in dib8000_agc_startup()
1278 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)  in dib8096p_host_bus_drive()  argument
1285 	reg = dib8000_read_word(state, 1798) &  in dib8096p_host_bus_drive()
1288 	dib8000_write_word(state, 1798, reg);  in dib8096p_host_bus_drive()
1291 	reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));  in dib8096p_host_bus_drive()
1293 	dib8000_write_word(state, 1799, reg);  in dib8096p_host_bus_drive()
1296 	reg = dib8000_read_word(state, 1800) &  in dib8096p_host_bus_drive()
1299 	dib8000_write_word(state, 1800, reg);  in dib8096p_host_bus_drive()
1302 	reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));  in dib8096p_host_bus_drive()
1304 	dib8000_write_word(state, 1801, reg);  in dib8096p_host_bus_drive()
1307 	reg = dib8000_read_word(state, 1802) &  in dib8096p_host_bus_drive()
1310 	dib8000_write_word(state, 1802, reg);  in dib8096p_host_bus_drive()
1332 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,  in dib8096p_cfg_DibTx()  argument
1338 	dib8000_write_word(state, 1615, 1);  in dib8096p_cfg_DibTx()
1339 	dib8000_write_word(state, 1603, P_Kin);  in dib8096p_cfg_DibTx()
1340 	dib8000_write_word(state, 1605, P_Kout);  in dib8096p_cfg_DibTx()
1341 	dib8000_write_word(state, 1606, insertExtSynchro);  in dib8096p_cfg_DibTx()
1342 	dib8000_write_word(state, 1608, synchroMode);  in dib8096p_cfg_DibTx()
1343 	dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);  in dib8096p_cfg_DibTx()
1344 	dib8000_write_word(state, 1610, syncWord & 0xffff);  in dib8096p_cfg_DibTx()
1345 	dib8000_write_word(state, 1612, syncSize);  in dib8096p_cfg_DibTx()
1346 	dib8000_write_word(state, 1615, 0);  in dib8096p_cfg_DibTx()
1349 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,  in dib8096p_cfg_DibRx()  argument
1360 		dib8000_write_word(state, 1542, syncFreq);  in dib8096p_cfg_DibRx()
1363 	dib8000_write_word(state, 1554, 1);  in dib8096p_cfg_DibRx()
1364 	dib8000_write_word(state, 1536, P_Kin);  in dib8096p_cfg_DibRx()
1365 	dib8000_write_word(state, 1537, P_Kout);  in dib8096p_cfg_DibRx()
1366 	dib8000_write_word(state, 1539, synchroMode);  in dib8096p_cfg_DibRx()
1367 	dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);  in dib8096p_cfg_DibRx()
1368 	dib8000_write_word(state, 1541, syncWord & 0xffff);  in dib8096p_cfg_DibRx()
1369 	dib8000_write_word(state, 1543, syncSize);  in dib8096p_cfg_DibRx()
1370 	dib8000_write_word(state, 1544, dataOutRate);  in dib8096p_cfg_DibRx()
1371 	dib8000_write_word(state, 1554, 0);  in dib8096p_cfg_DibRx()
1374 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)  in dib8096p_enMpegMux()  argument
1378 	reg_1287 = dib8000_read_word(state, 1287);  in dib8096p_enMpegMux()
1389 	dib8000_write_word(state, 1287, reg_1287);  in dib8096p_enMpegMux()
1392 static void dib8096p_configMpegMux(struct dib8000_state *state,  in dib8096p_configMpegMux()  argument
1399 	dib8096p_enMpegMux(state, 0);  in dib8096p_configMpegMux()
1402 	if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))  in dib8096p_configMpegMux()
1407 	dib8000_write_word(state, 1287, reg_1287);  in dib8096p_configMpegMux()
1409 	dib8096p_enMpegMux(state, 1);  in dib8096p_configMpegMux()
1412 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)  in dib8096p_setDibTxMux()  argument
1414 	u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);  in dib8096p_setDibTxMux()
1419 			dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);  in dib8096p_setDibTxMux()
1423 			dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);  in dib8096p_setDibTxMux()
1427 			dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);  in dib8096p_setDibTxMux()
1432 	dib8000_write_word(state, 1288, reg_1288);  in dib8096p_setDibTxMux()
1435 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)  in dib8096p_setHostBusMux()  argument
1437 	u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);  in dib8096p_setHostBusMux()
1442 			dib8096p_enMpegMux(state, 0);  in dib8096p_setHostBusMux()
1447 			dib8096p_enMpegMux(state, 0);  in dib8096p_setHostBusMux()
1457 	dib8000_write_word(state, 1288, reg_1288);  in dib8096p_setHostBusMux()
1462 	struct dib8000_state *state = fe->demodulator_priv;  in dib8096p_set_diversity_in()  local
1470 			dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);  in dib8096p_set_diversity_in()
1474 			reg_1287 = dib8000_read_word(state, 1287);  in dib8096p_set_diversity_in()
1479 				dib8000_write_word(state, 1287, reg_1287);  in dib8096p_set_diversity_in()
1481 			state->input_mode_mpeg = 1;  in dib8096p_set_diversity_in()
1486 			dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);  in dib8096p_set_diversity_in()
1487 			state->input_mode_mpeg = 0;  in dib8096p_set_diversity_in()
1491 	dib8000_set_diversity_in(state->fe[0], onoff);  in dib8096p_set_diversity_in()
1497 	struct dib8000_state *state = fe->demodulator_priv;  in dib8096p_set_output_mode()  local
1502 	state->output_mode = mode;  in dib8096p_set_output_mode()
1503 	dib8096p_host_bus_drive(state, 1);  in dib8096p_set_output_mode()
1506 	smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);  in dib8096p_set_output_mode()
1507 	outreg   = dib8000_read_word(state, 1286) &  in dib8096p_set_output_mode()
1518 				dib8096p_configMpegMux(state, 3, 1, 1);  in dib8096p_set_output_mode()
1519 				dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);  in dib8096p_set_output_mode()
1522 				dib8096p_setHostBusMux(state,  in dib8096p_set_output_mode()
1531 				dib8096p_configMpegMux(state, 2, 0, 0);  in dib8096p_set_output_mode()
1532 				dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);  in dib8096p_set_output_mode()
1535 				dib8096p_setHostBusMux(state,  in dib8096p_set_output_mode()
1543 			dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);  in dib8096p_set_output_mode()
1551 			dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);  in dib8096p_set_output_mode()
1559 			dib8096p_setDibTxMux(state, DIV_ON_DIBTX);  in dib8096p_set_output_mode()
1560 			dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);  in dib8096p_set_output_mode()
1565 			dib8096p_setDibTxMux(state, ADC_ON_DIBTX);  in dib8096p_set_output_mode()
1566 			dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);  in dib8096p_set_output_mode()
1574 			state->cfg.output_mpeg2_in_188_bytes);  in dib8096p_set_output_mode()
1575 	if (state->cfg.output_mpeg2_in_188_bytes)  in dib8096p_set_output_mode()
1578 	ret |= dib8000_write_word(state, 299, smo_mode);  in dib8096p_set_output_mode()
1580 	ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);  in dib8096p_set_output_mode()
1581 	ret |= dib8000_write_word(state, 1286, outreg);  in dib8096p_set_output_mode()
1610 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);  in dib8096p_tuner_write_serpar()  local
1616 		n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;  in dib8096p_tuner_write_serpar()
1621 	dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));  in dib8096p_tuner_write_serpar()
1622 	dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);  in dib8096p_tuner_write_serpar()
1630 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);  in dib8096p_tuner_read_serpar()  local
1637 		n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;  in dib8096p_tuner_read_serpar()
1642 	dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));  in dib8096p_tuner_read_serpar()
1646 		n_empty = dib8000_read_word(state, 1984)&0x1;  in dib8096p_tuner_read_serpar()
1652 	read_word = dib8000_read_word(state, 1987);  in dib8096p_tuner_read_serpar()
1674 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);  in dib8096p_rw_on_apb()  local
1678 		dib8000_write_word(state, apb_address,  in dib8096p_rw_on_apb()
1681 		word = dib8000_read_word(state, apb_address);  in dib8096p_rw_on_apb()
1691 	struct dib8000_state *state = i2c_get_adapdata(i2c_adap);  in dib8096p_tuner_xfer()  local
1782 			i = ((dib8000_read_word(state, 921) >> 12)&0x3);  in dib8096p_tuner_xfer()
1783 			word = dib8000_read_word(state, 924+i);  in dib8096p_tuner_xfer()
1793 				word = (dib8000_read_word(state, 921) &  in dib8096p_tuner_xfer()
1796 				dib8000_write_word(state, 921, word);  in dib8096p_tuner_xfer()
1828 	struct dib8000_state *state = fe->demodulator_priv;  in dib8096p_tuner_sleep()  local
1833 	en_cur_state = dib8000_read_word(state, 1922);  in dib8096p_tuner_sleep()
1837 		state->tuner_enable = en_cur_state ;  in dib8096p_tuner_sleep()
1842 		if (state->tuner_enable != 0)  in dib8096p_tuner_sleep()
1843 			en_cur_state = state->tuner_enable;  in dib8096p_tuner_sleep()
1846 	dib8000_write_word(state, 1922, en_cur_state);  in dib8096p_tuner_sleep()
1859 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_adc_power()  local
1863 	val = dib8000_read32(state, 384);  in dib8000_get_adc_power()
1879 	struct dib8000_state *state = fe->demodulator_priv;  in dib8090p_get_dc_power()  local
1884 			val = dib8000_read_word(state, 403);  in dib8090p_get_dc_power()
1887 			val = dib8000_read_word(state, 404);  in dib8090p_get_dc_power()
1897 static void dib8000_update_timf(struct dib8000_state *state)  in dib8000_update_timf()  argument
1899 	u32 timf = state->timf = dib8000_read32(state, 435);  in dib8000_update_timf()
1901 	dib8000_write_word(state, 29, (u16) (timf >> 16));  in dib8000_update_timf()
1902 	dib8000_write_word(state, 30, (u16) (timf & 0xffff));  in dib8000_update_timf()
1903 	dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default);  in dib8000_update_timf()
1908 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_ctrl_timf()  local
1912 			state->timf = timf;  in dib8000_ctrl_timf()
1915 			dib8000_update_timf(state);  in dib8000_ctrl_timf()
1920 	dib8000_set_bandwidth(state->fe[0], 6000);  in dib8000_ctrl_timf()
1922 	return state->timf;  in dib8000_ctrl_timf()
1941 static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation)  in dib8000_set_layer()  argument
1944 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_layer()
1986 …dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment…  in dib8000_set_layer()
2007 static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation)  in dib8000_adp_fine_tune()  argument
2029 		dib8000_write_word(state, 215 + i, adp[i]);  in dib8000_adp_fine_tune()
2034 static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain)  in dib8000_update_ana_gain()  argument
2038 	dib8000_write_word(state, 116, ana_gain);  in dib8000_update_ana_gain()
2043 			dib8000_write_word(state, 80 + i, adc_target_16dB[i]);  in dib8000_update_ana_gain()
2046 			dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);  in dib8000_update_ana_gain()
2050 static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe)  in dib8000_load_ana_fe_coefs()  argument
2054 	if (state->isdbt_cfg_loaded == 0)  in dib8000_load_ana_fe_coefs()
2056 			dib8000_write_word(state, 117 + mode, ana_fe[mode]);  in dib8000_load_ana_fe_coefs()
2069 static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel)  in dib8000_get_init_prbs()  argument
2076 	switch (state->fe[0]->dtv_property_cache.transmission_mode) {  in dib8000_get_init_prbs()
2087 static void dib8000_set_13seg_channel(struct dib8000_state *state)  in dib8000_set_13seg_channel()  argument
2092 	state->seg_mask = 0x1fff; /* All 13 segments enabled */  in dib8000_set_13seg_channel()
2095 …if (state->isdbt_cfg_loaded == 0) {  /* if not Sound Broadcasting mode : put default values for 13…  in dib8000_set_13seg_channel()
2096 		dib8000_write_word(state, 180, (16 << 6) | 9);  in dib8000_set_13seg_channel()
2097 		dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);  in dib8000_set_13seg_channel()
2100 			dib8000_write_word(state, 181+i, coff_pow);  in dib8000_set_13seg_channel()
2104 		dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);  in dib8000_set_13seg_channel()
2107 		dib8000_write_word(state, 340, (8 << 6) | (6 << 0));  in dib8000_set_13seg_channel()
2109 		dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));  in dib8000_set_13seg_channel()
2111 		dib8000_write_word(state, 228, 0);  /* default value */  in dib8000_set_13seg_channel()
2112 		dib8000_write_word(state, 265, 31); /* default value */  in dib8000_set_13seg_channel()
2113 		dib8000_write_word(state, 205, 0x200f); /* init value */  in dib8000_set_13seg_channel()
2121 	if (state->cfg.pll->ifreq == 0)  in dib8000_set_13seg_channel()
2122 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_s…  in dib8000_set_13seg_channel()
2124 	dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg);  in dib8000_set_13seg_channel()
2127 static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs)  in dib8000_set_subchannel_prbs()  argument
2131 	reg_1 = dib8000_read_word(state, 1);  in dib8000_set_subchannel_prbs()
2132 	dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */  in dib8000_set_subchannel_prbs()
2135 static void dib8000_small_fine_tune(struct dib8000_state *state)  in dib8000_small_fine_tune()  argument
2139 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_small_fine_tune()
2141 	dib8000_write_word(state, 352, state->seg_diff_mask);  in dib8000_small_fine_tune()
2142 	dib8000_write_word(state, 353, state->seg_mask);  in dib8000_small_fine_tune()
2145 	dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5);  in dib8000_small_fine_tune()
2215 			dib8000_write_word(state, 343 + i, ncoeff[i]);  in dib8000_small_fine_tune()
2221 static void dib8000_set_sb_channel(struct dib8000_state *state)  in dib8000_set_sb_channel()  argument
2223 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_sb_channel()
2228 		dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */  in dib8000_set_sb_channel()
2229 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shi…  in dib8000_set_sb_channel()
2231 		dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */  in dib8000_set_sb_channel()
2232 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = …  in dib8000_set_sb_channel()
2236 		state->seg_mask = 0x00E0;  in dib8000_set_sb_channel()
2238 		state->seg_mask = 0x0040;  in dib8000_set_sb_channel()
2240 	dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);  in dib8000_set_sb_channel()
2244 …dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partia…  in dib8000_set_sb_channel()
2246 …dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_fr…  in dib8000_set_sb_channel()
2247 …dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres…  in dib8000_set_sb_channel()
2252 		if (state->mode == 3)  in dib8000_set_sb_channel()
2253 			dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14));  in dib8000_set_sb_channel()
2255 			dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14));  in dib8000_set_sb_channel()
2258 		dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);  in dib8000_set_sb_channel()
2261 		dib8000_write_word(state, 180, 0x1fcf | (1 << 14));  in dib8000_set_sb_channel()
2263 		dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);  in dib8000_set_sb_channel()
2267 	dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */  in dib8000_set_sb_channel()
2268 	dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */  in dib8000_set_sb_channel()
2271 		dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */  in dib8000_set_sb_channel()
2275 		dib8000_write_word(state, 181+i, coff[i]);  in dib8000_set_sb_channel()
2276 		dib8000_write_word(state, 184+i, coff[i]);  in dib8000_set_sb_channel()
2284 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh …  in dib8000_set_sb_channel()
2287 		dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */  in dib8000_set_sb_channel()
2289 		dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */  in dib8000_set_sb_channel()
2292 static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching)  in dib8000_set_isdbt_common_channel()  argument
2298 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_isdbt_common_channel()
2301 	dib8000_write_word(state, 10, (seq << 4));  in dib8000_set_isdbt_common_channel()
2304 	state->mode = fft_to_mode(state);  in dib8000_set_isdbt_common_channel()
2307 	tmp = dib8000_read_word(state, 1);  in dib8000_set_isdbt_common_channel()
2308 	dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3));  in dib8000_set_isdbt_common_channel()
2310 …dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_recep…  in dib8000_set_isdbt_common_channel()
2314 		state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0];  in dib8000_set_isdbt_common_channel()
2318 			state->seg_diff_mask |= 1 << permu_seg[i+1];  in dib8000_set_isdbt_common_channel()
2323 			state->seg_diff_mask |= 1 << permu_seg[i];  in dib8000_set_isdbt_common_channel()
2326 	if (state->seg_diff_mask)  in dib8000_set_isdbt_common_channel()
2327 		dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);  in dib8000_set_isdbt_common_channel()
2329 		dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */  in dib8000_set_isdbt_common_channel()
2332 		max_constellation = dib8000_set_layer(state, i, max_constellation);  in dib8000_set_isdbt_common_channel()
2334 		state->layer_b_nb_seg = c->layer[1].segment_count;  in dib8000_set_isdbt_common_channel()
2335 		state->layer_c_nb_seg = c->layer[2].segment_count;  in dib8000_set_isdbt_common_channel()
2339 	dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask);  in dib8000_set_isdbt_common_channel()
2341 	state->differential_constellation = (state->seg_diff_mask != 0);  in dib8000_set_isdbt_common_channel()
2344 	ana_gain = dib8000_adp_fine_tune(state, max_constellation);  in dib8000_set_isdbt_common_channel()
2347 	dib8000_update_ana_gain(state, ana_gain);  in dib8000_set_isdbt_common_channel()
2351 		dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg);  in dib8000_set_isdbt_common_channel()
2353 		dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */  in dib8000_set_isdbt_common_channel()
2357 		dib8000_set_sb_channel(state);  in dib8000_set_isdbt_common_channel()
2359 			init_prbs = dib8000_get_init_prbs(state, c->isdbt_sb_subchannel);  in dib8000_set_isdbt_common_channel()
2363 		dib8000_set_13seg_channel(state);  in dib8000_set_isdbt_common_channel()
2368 	dib8000_small_fine_tune(state);  in dib8000_set_isdbt_common_channel()
2370 	dib8000_set_subchannel_prbs(state, init_prbs);  in dib8000_set_isdbt_common_channel()
2374 		if ((((~state->seg_diff_mask) >> i) & 1) == 1) {  in dib8000_set_isdbt_common_channel()
2375 …p_cfr_left_edge  += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i -…  in dib8000_set_isdbt_common_channel()
2376 …p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i …  in dib8000_set_isdbt_common_channel()
2379 	dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */  in dib8000_set_isdbt_common_channel()
2380 	dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */  in dib8000_set_isdbt_common_channel()
2383 	dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */  in dib8000_set_isdbt_common_channel()
2384 	dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */  in dib8000_set_isdbt_common_channel()
2385 	dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */  in dib8000_set_isdbt_common_channel()
2388 …dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_…  in dib8000_set_isdbt_common_channel()
2390 …dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be a…  in dib8000_set_isdbt_common_channel()
2392 	dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */  in dib8000_set_isdbt_common_channel()
2393 	dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */  in dib8000_set_isdbt_common_channel()
2395 	dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */  in dib8000_set_isdbt_common_channel()
2404 	dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */  in dib8000_set_isdbt_common_channel()
2405 	dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */  in dib8000_set_isdbt_common_channel()
2406 	dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */  in dib8000_set_isdbt_common_channel()
2410 	if (state->isdbt_cfg_loaded == 0)  in dib8000_set_isdbt_common_channel()
2411 		dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */  in dib8000_set_isdbt_common_channel()
2413 	state->isdbt_cfg_loaded = 0;  in dib8000_set_isdbt_common_channel()
2416 static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal,  in dib8000_wait_lock()  argument
2424 			if (state->revision == 0x8090)  in dib8000_wait_lock()
2432 		dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff));  in dib8000_wait_lock()
2433 		dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff));  in dib8000_wait_lock()
2440 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_autosearch_start()  local
2441 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_autosearch_start()
2443 	u32 value, internal = state->cfg.pll->internal;  in dib8000_autosearch_start()
2445 	if (state->revision == 0x8090)  in dib8000_autosearch_start()
2446 		internal = dib8000_read32(state, 23) / 1000;  in dib8000_autosearch_start()
2448 	if (state->autosearch_state == AS_SEARCHING_FFT) {  in dib8000_autosearch_start()
2449 		dib8000_write_word(state,  37, 0x0065); /* P_ctrl_pha_off_max default values */  in dib8000_autosearch_start()
2450 		dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */  in dib8000_autosearch_start()
2452 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P…  in dib8000_autosearch_start()
2453 		dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */  in dib8000_autosearch_start()
2454 		dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */  in dib8000_autosearch_start()
2455 		dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */  in dib8000_autosearch_start()
2456 		dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */  in dib8000_autosearch_start()
2457 …dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P…  in dib8000_autosearch_start()
2459 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2460 …value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_se…  in dib8000_autosearch_start()
2462 …value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_se…  in dib8000_autosearch_start()
2464 		dib8000_write_word(state, 17, 0);  in dib8000_autosearch_start()
2465 		dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */  in dib8000_autosearch_start()
2466 		dib8000_write_word(state, 19, 0);  in dib8000_autosearch_start()
2467 		dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */  in dib8000_autosearch_start()
2468 		dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */  in dib8000_autosearch_start()
2469 		dib8000_write_word(state, 22, value & 0xffff);  in dib8000_autosearch_start()
2471 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2472 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha…  in dib8000_autosearch_start()
2474 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha…  in dib8000_autosearch_start()
2475 		dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */  in dib8000_autosearch_start()
2478 		dib8000_write_word(state, 356, 0);  in dib8000_autosearch_start()
2479 		dib8000_write_word(state, 357, 0x111);  in dib8000_autosearch_start()
2481 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart…  in dib8000_autosearch_start()
2482 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart…  in dib8000_autosearch_start()
2483 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_…  in dib8000_autosearch_start()
2484 	} else if (state->autosearch_state == AS_SEARCHING_GUARD) {  in dib8000_autosearch_start()
2494 		c->transmission_mode = state->found_nfft;  in dib8000_autosearch_start()
2496 		dib8000_set_isdbt_common_channel(state, slist, 1);  in dib8000_autosearch_start()
2499 		dib8000_write_word(state, 6, 0x4);  in dib8000_autosearch_start()
2500 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2501 …dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock…  in dib8000_autosearch_start()
2503 			dib8000_write_word(state, 7, 0x8);  in dib8000_autosearch_start()
2504 		dib8000_write_word(state, 8, 0x1000);  in dib8000_autosearch_start()
2507 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2508 …dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_…  in dib8000_autosearch_start()
2510 …dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_…  in dib8000_autosearch_start()
2512 		dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */  in dib8000_autosearch_start()
2515 		dib8000_write_word(state, 356, 0);  in dib8000_autosearch_start()
2516 		dib8000_write_word(state, 357, 0xf);  in dib8000_autosearch_start()
2518 		value = dib8000_read_word(state, 0);  in dib8000_autosearch_start()
2519 		dib8000_write_word(state, 0, (u16)((1 << 15) | value));  in dib8000_autosearch_start()
2520 		dib8000_read_word(state, 1284);  /* reset the INT. n_irq_pending */  in dib8000_autosearch_start()
2521 		dib8000_write_word(state, 0, (u16)value);  in dib8000_autosearch_start()
2534 			dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  in dib8000_autosearch_start()
2541 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  /* P_mode = 1 t…  in dib8000_autosearch_start()
2550 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));  /* P_mode = 1 */  in dib8000_autosearch_start()
2557 		dib8000_set_isdbt_common_channel(state, slist, 1);  in dib8000_autosearch_start()
2560 		dib8000_write_word(state, 6, 0x4);  in dib8000_autosearch_start()
2561 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2562 			dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10));  in dib8000_autosearch_start()
2564 			dib8000_write_word(state, 7, 0x8);  in dib8000_autosearch_start()
2565 		dib8000_write_word(state, 8, 0x1000);  in dib8000_autosearch_start()
2568 		if (state->revision == 0x8090)  in dib8000_autosearch_start()
2569 …dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_…  in dib8000_autosearch_start()
2571 …dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_…  in dib8000_autosearch_start()
2573 		value = dib8000_read_word(state, 0);  in dib8000_autosearch_start()
2574 		dib8000_write_word(state, 0, (u16)((1 << 15) | value));  in dib8000_autosearch_start()
2575 		dib8000_read_word(state, 1284);  /* reset the INT. n_irq_pending */  in dib8000_autosearch_start()
2576 		dib8000_write_word(state, 0, (u16)value);  in dib8000_autosearch_start()
2583 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_autosearch_irq()  local
2584 	u16 irq_pending = dib8000_read_word(state, 1284);  in dib8000_autosearch_irq()
2586 	if (state->autosearch_state == AS_SEARCHING_FFT) {  in dib8000_autosearch_irq()
2606 static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff)  in dib8000_viterbi_state()  argument
2610 	tmp = dib8000_read_word(state, 771);  in dib8000_viterbi_state()
2612 		dib8000_write_word(state, 771, tmp & 0xfffd);  in dib8000_viterbi_state()
2614 		dib8000_write_word(state, 771, tmp | (1<<1));  in dib8000_viterbi_state()
2617 static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz)  in dib8000_set_dds()  argument
2621 	u32 dds = state->cfg.pll->ifreq & 0x1ffffff;  in dib8000_set_dds()
2622 	u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));  in dib8000_set_dds()
2625 	if (state->revision == 0x8090) {  in dib8000_set_dds()
2627 		unit_khz_dds_val = (1<<26) / (dib8000_read32(state, 23) / 1000);  in dib8000_set_dds()
2637 		unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal);  in dib8000_set_dds()
2651 	if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {  in dib8000_set_dds()
2653 		dib8000_write_word(state, 26, invert);  in dib8000_set_dds()
2654 		dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff);  in dib8000_set_dds()
2655 		dib8000_write_word(state, 28, (u16)(dds & 0xffff));  in dib8000_set_dds()
2659 static void dib8000_set_frequency_offset(struct dib8000_state *state)  in dib8000_set_frequency_offset()  argument
2661 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_frequency_offset()
2666 	if (state->fe[0]->ops.tuner_ops.get_frequency)  in dib8000_set_frequency_offset()
2667 		state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], &current_rf);  in dib8000_set_frequency_offset()
2674 		state->subchannel = c->isdbt_sb_subchannel;  in dib8000_set_frequency_offset()
2676 		i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */  in dib8000_set_frequency_offset()
2677 		dib8000_write_word(state, 26, c->inversion ^ i);  in dib8000_set_frequency_offset()
2679 		if (state->cfg.pll->ifreq == 0) { /* low if tuner */  in dib8000_set_frequency_offset()
2681 				dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);  in dib8000_set_frequency_offset()
2691 	dib8000_set_dds(state, total_dds_offset_khz);  in dib8000_set_frequency_offset()
2696 static u32 dib8000_get_symbol_duration(struct dib8000_state *state)  in dib8000_get_symbol_duration()  argument
2698 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_get_symbol_duration()
2718 static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_st…  in dib8000_set_isdbt_loop_params()  argument
2720 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_isdbt_loop_params()
2727 …reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha…  in dib8000_set_isdbt_loop_params()
2728 …reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  …  in dib8000_set_isdbt_loop_params()
2730 …reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha…  in dib8000_set_isdbt_loop_params()
2731 …reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P…  in dib8000_set_isdbt_loop_params()
2734 …reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6,…  in dib8000_set_isdbt_loop_params()
2735 …reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3   P_ctrl_sfreq_inh =0  P…  in dib8000_set_isdbt_loop_params()
2741 …reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=…  in dib8000_set_isdbt_loop_params()
2742 					reg_37 = (12-state->mode) | ((5 + state->mode) << 5);  in dib8000_set_isdbt_loop_params()
2744 …reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=…  in dib8000_set_isdbt_loop_params()
2745 					reg_37 = (11-state->mode) | ((5 + state->mode) << 5);  in dib8000_set_isdbt_loop_params()
2748 …reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_…  in dib8000_set_isdbt_loop_params()
2749 				reg_37 = ((5+state->mode) << 5) | (10 - state->mode);  in dib8000_set_isdbt_loop_params()
2753 	dib8000_write_word(state, 32, reg_32);  in dib8000_set_isdbt_loop_params()
2754 	dib8000_write_word(state, 37, reg_37);  in dib8000_set_isdbt_loop_params()
2757 static void dib8000_demod_restart(struct dib8000_state *state)  in dib8000_demod_restart()  argument
2759 	dib8000_write_word(state, 770, 0x4000);  in dib8000_demod_restart()
2760 	dib8000_write_word(state, 770, 0x0000);  in dib8000_demod_restart()
2764 static void dib8000_set_sync_wait(struct dib8000_state *state)  in dib8000_set_sync_wait()  argument
2766 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_sync_wait()
2783 	if (state->cfg.diversity_delay == 0)  in dib8000_set_sync_wait()
2786 …sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add …  in dib8000_set_sync_wait()
2788 	dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4));  in dib8000_set_sync_wait()
2791 static u32 dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode mode)  in dib8000_get_timeout()  argument
2794 		return systime() + (delay * state->symbol_duration);  in dib8000_get_timeout()
2801 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_status()  local
2802 	return state->status;  in dib8000_get_status()
2807 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_tune_state()  local
2808 	return state->tune_state;  in dib8000_get_tune_state()
2814 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_tune_state()  local
2816 	state->tune_state = tune_state;  in dib8000_set_tune_state()
2823 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_tune_restart_from_demod()  local
2825 	state->status = FE_STATUS_TUNE_PENDING;  in dib8000_tune_restart_from_demod()
2826 	state->tune_state = CT_DEMOD_START;  in dib8000_tune_restart_from_demod()
2832 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_lock()  local
2834 	if (state->revision == 0x8090)  in dib8000_read_lock()
2835 		return dib8000_read_word(state, 570);  in dib8000_read_lock()
2836 	return dib8000_read_word(state, 568);  in dib8000_read_lock()
2839 static int dib8090p_init_sdram(struct dib8000_state *state)  in dib8090p_init_sdram()  argument
2844 	reg = dib8000_read_word(state, 274) & 0xfff0;  in dib8090p_init_sdram()
2845 	dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */  in dib8090p_init_sdram()
2847 	dib8000_write_word(state, 1803, (7 << 2));  in dib8090p_init_sdram()
2849 	reg = dib8000_read_word(state, 1280);  in dib8090p_init_sdram()
2850 	dib8000_write_word(state, 1280,  reg | (1 << 2)); /* force restart P_restart_sdram */  in dib8090p_init_sdram()
2851 	dib8000_write_word(state, 1280,  reg); /* release restart P_restart_sdram */  in dib8090p_init_sdram()
2858 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_tune()  local
2859 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_tune()
2860 	enum frontend_tune_state *tune_state = &state->tune_state;  in dib8000_tune()
2865 	u32 *timeout = &state->timeout;  in dib8000_tune()
2876 …, TUNE_STATE %d autosearch step = %u systime = %u", state->channel_parameters_set, *tune_state, st…  in dib8000_tune()
2881 			if (state->revision == 0x8090)  in dib8000_tune()
2882 				dib8090p_init_sdram(state);  in dib8000_tune()
2883 			state->status = FE_STATUS_TUNE_PENDING;  in dib8000_tune()
2908 				state->channel_parameters_set = 0; /* auto search */  in dib8000_tune()
2910 				state->channel_parameters_set = 1; /* channel parameters are known */  in dib8000_tune()
2912 			dib8000_viterbi_state(state, 0); /* force chan dec in restart */  in dib8000_tune()
2915 			dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);  in dib8000_tune()
2917 			dib8000_set_frequency_offset(state);  in dib8000_tune()
2920 			if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */  in dib8000_tune()
2922 				if (state->revision != 0x8090) {  in dib8000_tune()
2923 					state->agc1_max = dib8000_read_word(state, 108);  in dib8000_tune()
2924 					state->agc1_min = dib8000_read_word(state, 109);  in dib8000_tune()
2925 					state->agc2_max = dib8000_read_word(state, 110);  in dib8000_tune()
2926 					state->agc2_min = dib8000_read_word(state, 111);  in dib8000_tune()
2927 					agc1 = dib8000_read_word(state, 388);  in dib8000_tune()
2928 					agc2 = dib8000_read_word(state, 389);  in dib8000_tune()
2929 					dib8000_write_word(state, 108, agc1);  in dib8000_tune()
2930 					dib8000_write_word(state, 109, agc1);  in dib8000_tune()
2931 					dib8000_write_word(state, 110, agc2);  in dib8000_tune()
2932 					dib8000_write_word(state, 111, agc2);  in dib8000_tune()
2935 				state->autosearch_state = AS_SEARCHING_FFT;  in dib8000_tune()
2936 				state->found_nfft = TRANSMISSION_MODE_AUTO;  in dib8000_tune()
2937 				state->found_guard = GUARD_INTERVAL_AUTO;  in dib8000_tune()
2940 				state->autosearch_state = AS_DONE;  in dib8000_tune()
2943 			state->symbol_duration = dib8000_get_symbol_duration(state);  in dib8000_tune()
2948 			if (state->revision == 0x8090)  in dib8000_tune()
2958 					state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
2959 					state->autosearch_state = AS_DONE;  in dib8000_tune()
2963 …state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel foun…  in dib8000_tune()
2965 					if (state->autosearch_state == AS_SEARCHING_GUARD)  in dib8000_tune()
2968 						state->autosearch_state = AS_DONE;  in dib8000_tune()
2977 			switch (state->autosearch_state) {  in dib8000_tune()
2980 				if (state->revision == 0x8090) {  in dib8000_tune()
2981 					corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));  in dib8000_tune()
2982 					corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));  in dib8000_tune()
2983 					corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601));  in dib8000_tune()
2985 					corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595));  in dib8000_tune()
2986 					corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));  in dib8000_tune()
2987 					corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));  in dib8000_tune()
2999 							state->found_nfft = TRANSMISSION_MODE_2K;  in dib8000_tune()
3002 							state->found_nfft = TRANSMISSION_MODE_4K;  in dib8000_tune()
3006 							state->found_nfft = TRANSMISSION_MODE_8K;  in dib8000_tune()
3012 					state->autosearch_state = AS_SEARCHING_GUARD;  in dib8000_tune()
3013 					if (state->revision == 0x8090)  in dib8000_tune()
3020 					if (state->revision == 0x8090)  in dib8000_tune()
3021 						state->found_guard = dib8000_read_word(state, 572) & 0x3;  in dib8000_tune()
3023 						state->found_guard = dib8000_read_word(state, 570) & 0x3;  in dib8000_tune()
3030 					state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3031 					state->autosearch_state = AS_DONE;  in dib8000_tune()
3038 			state->symbol_duration = dib8000_get_symbol_duration(state);  in dib8000_tune()
3039 			dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1);  in dib8000_tune()
3040 			dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */  in dib8000_tune()
3045 			dib8000_demod_restart(state);  in dib8000_tune()
3047 			dib8000_set_sync_wait(state);  in dib8000_tune()
3048 			dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);  in dib8000_tune()
3050 			locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */  in dib8000_tune()
3052 			*timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON);  in dib8000_tune()
3059 				dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */  in dib8000_tune()
3060 				if (!state->differential_constellation) {  in dib8000_tune()
3062 …*timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEP…  in dib8000_tune()
3073 			if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) {  in dib8000_tune()
3075 …if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input…  in dib8000_tune()
3077 …else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input faill…  in dib8000_tune()
3079 					dib8000_viterbi_state(state, 1); /* start viterbi chandec */  in dib8000_tune()
3080 					dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);  in dib8000_tune()
3081 					state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3084 				dib8000_viterbi_state(state, 1); /* start viterbi chandec */  in dib8000_tune()
3085 				dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);  in dib8000_tune()
3087 				state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3101 			dib8000_viterbi_state(state, 1); /* start viterbi chandec */  in dib8000_tune()
3102 			dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);  in dib8000_tune()
3107 			    && !state->differential_constellation) {  in dib8000_tune()
3108 				state->subchannel = 0;  in dib8000_tune()
3112 				state->status = FE_STATUS_LOCKED;  in dib8000_tune()
3117 …if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable …  in dib8000_tune()
3124 							state->longest_intlv_layer = i;  in dib8000_tune()
3136 				if (state->diversity_onoff != 0) /* because of diversity sync */  in dib8000_tune()
3140 …: timeout mult factor = %d => will use timeout = %d", deeper_interleaver, state->longest_intlv_lay…  in dib8000_tune()
3149 			if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */  in dib8000_tune()
3153 				    && !state->differential_constellation)  in dib8000_tune()
3155 					state->status = FE_STATUS_DEMOD_SUCCESS;  in dib8000_tune()
3157 					state->status = FE_STATUS_DATA_LOCKED;  in dib8000_tune()
3162 				    && !state->differential_constellation) { /* continue to try init prbs autosearch */  in dib8000_tune()
3163 					state->subchannel += 3;  in dib8000_tune()
3168 						state->status = FE_STATUS_DATA_LOCKED;  in dib8000_tune()
3170 						state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3177 			if (state->subchannel <= 41) {  in dib8000_tune()
3178 				dib8000_set_subchannel_prbs(state, dib8000_get_init_prbs(state, state->subchannel));  in dib8000_tune()
3182 				state->status = FE_STATUS_TUNE_FAILED;  in dib8000_tune()
3194 			if ((state->revision != 0x8090) && (state->agc1_max != 0)) {  in dib8000_tune()
3195 				dib8000_write_word(state, 108, state->agc1_max);  in dib8000_tune()
3196 				dib8000_write_word(state, 109, state->agc1_min);  in dib8000_tune()
3197 				dib8000_write_word(state, 110, state->agc2_max);  in dib8000_tune()
3198 				dib8000_write_word(state, 111, state->agc2_min);  in dib8000_tune()
3199 				state->agc1_max = 0;  in dib8000_tune()
3200 				state->agc1_min = 0;  in dib8000_tune()
3201 				state->agc2_max = 0;  in dib8000_tune()
3202 				state->agc2_min = 0;  in dib8000_tune()
3212 		return ret * state->symbol_duration;  in dib8000_tune()
3213 	if ((ret > 0) && (ret < state->symbol_duration))  in dib8000_tune()
3214 		return state->symbol_duration; /* at least one symbol */  in dib8000_tune()
3220 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_wakeup()  local
3224 	dib8000_set_power_mode(state, DIB8000_POWER_ALL);  in dib8000_wakeup()
3225 	dib8000_set_adc_state(state, DIBX000_ADC_ON);  in dib8000_wakeup()
3226 	if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)  in dib8000_wakeup()
3229 	if (state->revision == 0x8090)  in dib8000_wakeup()
3230 		dib8000_sad_calib(state);  in dib8000_wakeup()
3232 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_wakeup()
3233 		ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);  in dib8000_wakeup()
3243 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_sleep()  local
3247 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_sleep()
3248 		ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);  in dib8000_sleep()
3253 	if (state->revision != 0x8090)  in dib8000_sleep()
3255 	dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);  in dib8000_sleep()
3256 …return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_A…  in dib8000_sleep()
3261 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_frontend()  local
3268 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_get_frontend()
3269 		state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);  in dib8000_get_frontend()
3273 			state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]);  in dib8000_get_frontend()
3274 …for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_inde…  in dib8000_get_frontend()
3276 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_p…  in dib8000_get_frontend()
3277 …state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_prope…  in dib8000_get_frontend()
3278 …state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->d…  in dib8000_get_frontend()
3279 …state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_…  in dib8000_get_frontend()
3280 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_fronte…  in dib8000_get_frontend()
3282 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_fronten…  in dib8000_get_frontend()
3283 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend…  in dib8000_get_frontend()
3284 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_pr…  in dib8000_get_frontend()
3285 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]-…  in dib8000_get_frontend()
3293 	fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;  in dib8000_get_frontend()
3295 	if (state->revision == 0x8090)  in dib8000_get_frontend()
3296 		val = dib8000_read_word(state, 572);  in dib8000_get_frontend()
3298 		val = dib8000_read_word(state, 570);  in dib8000_get_frontend()
3329 	val = dib8000_read_word(state, 505);  in dib8000_get_frontend()
3334 		val = dib8000_read_word(state, 493 + i);  in dib8000_get_frontend()
3338 		val = dib8000_read_word(state, 499 + i);  in dib8000_get_frontend()
3342 		val = dib8000_read_word(state, 481 + i);  in dib8000_get_frontend()
3366 		val = dib8000_read_word(state, 487 + i);  in dib8000_get_frontend()
3389 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_get_frontend()
3390 …state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode;  in dib8000_get_frontend()
3391 		state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;  in dib8000_get_frontend()
3392 …state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmiss…  in dib8000_get_frontend()
3393 …state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interv…  in dib8000_get_frontend()
3394 …state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isd…  in dib8000_get_frontend()
3396 …state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.laye…  in dib8000_get_frontend()
3397 …state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer…  in dib8000_get_frontend()
3398 			state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec;  in dib8000_get_frontend()
3399 …state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i…  in dib8000_get_frontend()
3407 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_frontend()  local
3408 	struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;  in dib8000_set_frontend()
3423 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3425 		state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;  in dib8000_set_frontend()
3426 …memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_…  in dib8000_set_frontend()
3429 		if (state->revision != 0x8090) {  in dib8000_set_frontend()
3430 			dib8000_set_diversity_in(state->fe[index_frontend], 1);  in dib8000_set_frontend()
3432 				dib8000_set_output_mode(state->fe[index_frontend],  in dib8000_set_frontend()
3435 				dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);  in dib8000_set_frontend()
3437 			dib8096p_set_diversity_in(state->fe[index_frontend], 1);  in dib8000_set_frontend()
3439 				dib8096p_set_output_mode(state->fe[index_frontend],  in dib8000_set_frontend()
3442 				dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);  in dib8000_set_frontend()
3446 		if (state->fe[index_frontend]->ops.tuner_ops.set_params)  in dib8000_set_frontend()
3447 			state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);  in dib8000_set_frontend()
3449 		dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);  in dib8000_set_frontend()
3453 	if (state->revision != 0x8090)  in dib8000_set_frontend()
3454 		dib8000_set_diversity_in(state->fe[index_frontend - 1], 0);  in dib8000_set_frontend()
3456 		dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0);  in dib8000_set_frontend()
3460 		time = dib8000_agc_startup(state->fe[0]);  in dib8000_set_frontend()
3461 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3462 			time_slave = dib8000_agc_startup(state->fe[index_frontend]);  in dib8000_set_frontend()
3473 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3474 			if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {  in dib8000_set_frontend()
3481 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3482 		dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);  in dib8000_set_frontend()
3487 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3488 			delay = dib8000_tune(state->fe[index_frontend]);  in dib8000_set_frontend()
3493 			if (state->channel_parameters_set == 0) { /* searching */  in dib8000_set_frontend()
3494 …if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_sta…  in dib8000_set_frontend()
3496 …dib8000_get_frontend(state->fe[index_frontend]); /* we read the channel parameters from the fronte…  in dib8000_set_frontend()
3497 					state->channel_parameters_set = 1;  in dib8000_set_frontend()
3499 					for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) {  in dib8000_set_frontend()
3501 							dib8000_tune_restart_from_demod(state->fe[l]);  in dib8000_set_frontend()
3503 …state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isd…  in dib8000_set_frontend()
3504 …state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversi…  in dib8000_set_frontend()
3505 …state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache…  in dib8000_set_frontend()
3506 …state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.gu…  in dib8000_set_frontend()
3507 …state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property…  in dib8000_set_frontend()
3509 …state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_…  in dib8000_set_frontend()
3510 …state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_c…  in dib8000_set_frontend()
3511 …state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.laye…  in dib8000_set_frontend()
3512 …state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cac…  in dib8000_set_frontend()
3523 		if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED ||  in dib8000_set_frontend()
3524 				dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED ||  in dib8000_set_frontend()
3525 				dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) {  in dib8000_set_frontend()
3528 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_set_frontend()
3529 				if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP)  in dib8000_set_frontend()
3533 				dprintk("tuning done with status %d", dib8000_get_status(state->fe[0]));  in dib8000_set_frontend()
3546 	if (state->revision != 0x8090)  in dib8000_set_frontend()
3547 		dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);  in dib8000_set_frontend()
3549 		dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);  in dib8000_set_frontend()
3550 		if (state->cfg.enMpegOutput == 0) {  in dib8000_set_frontend()
3551 			dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);  in dib8000_set_frontend()
3552 			dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);  in dib8000_set_frontend()
3561 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_status()  local
3566 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_read_status()
3567 		lock_slave |= dib8000_read_lock(state->fe[index_frontend]);  in dib8000_read_status()
3584 		lock = dib8000_read_word(state, 554); /* Viterbi Layer A */  in dib8000_read_status()
3588 		lock = dib8000_read_word(state, 555); /* Viterbi Layer B */  in dib8000_read_status()
3592 		lock = dib8000_read_word(state, 556); /* Viterbi Layer C */  in dib8000_read_status()
3602 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_ber()  local
3605 	if (state->revision == 0x8090)  in dib8000_read_ber()
3606 		*ber = (dib8000_read_word(state, 562) << 16) |  in dib8000_read_ber()
3607 			dib8000_read_word(state, 563);  in dib8000_read_ber()
3609 		*ber = (dib8000_read_word(state, 560) << 16) |  in dib8000_read_ber()
3610 			dib8000_read_word(state, 561);  in dib8000_read_ber()
3616 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_unc_blocks()  local
3619 	if (state->revision == 0x8090)  in dib8000_read_unc_blocks()
3620 		*unc = dib8000_read_word(state, 567);  in dib8000_read_unc_blocks()
3622 		*unc = dib8000_read_word(state, 565);  in dib8000_read_unc_blocks()
3628 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_signal_strength()  local
3633 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_read_signal_strength()
3634 		state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);  in dib8000_read_signal_strength()
3641 	val = 65535 - dib8000_read_word(state, 390);  in dib8000_read_signal_strength()
3651 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_snr()  local
3655 	if (state->revision != 0x8090)  in dib8000_get_snr()
3656 		val = dib8000_read_word(state, 542);  in dib8000_get_snr()
3658 		val = dib8000_read_word(state, 544);  in dib8000_get_snr()
3665 	if (state->revision != 0x8090)  in dib8000_get_snr()
3666 		val = dib8000_read_word(state, 543);  in dib8000_get_snr()
3668 		val = dib8000_read_word(state, 545);  in dib8000_get_snr()
3684 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_read_snr()  local
3689 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] …  in dib8000_read_snr()
3690 		snr_master += dib8000_get_snr(state->fe[index_frontend]);  in dib8000_read_snr()
3704 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_set_slave_frontend()  local
3707 	while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))  in dib8000_set_slave_frontend()
3711 		state->fe[index_frontend] = fe_slave;  in dib8000_set_slave_frontend()
3722 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_remove_slave_frontend()  local
3725 	while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))  in dib8000_remove_slave_frontend()
3728 		dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1);  in dib8000_remove_slave_frontend()
3729 		state->fe[index_frontend] = NULL;  in dib8000_remove_slave_frontend()
3740 	struct dib8000_state *state = fe->demodulator_priv;  in dib8000_get_slave_frontend()  local
3744 	return state->fe[slave_index];  in dib8000_get_slave_frontend()
3909 	struct dib8000_state *state;  in dib8000_attach()  local
3913 	state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);  in dib8000_attach()
3914 	if (state == NULL)  in dib8000_attach()
3920 	memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));  in dib8000_attach()
3921 	state->i2c.adap = i2c_adap;  in dib8000_attach()
3922 	state->i2c.addr = i2c_addr;  in dib8000_attach()
3923 	state->i2c.i2c_write_buffer = state->i2c_write_buffer;  in dib8000_attach()
3924 	state->i2c.i2c_read_buffer = state->i2c_read_buffer;  in dib8000_attach()
3925 	mutex_init(&state->i2c_buffer_lock);  in dib8000_attach()
3926 	state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;  in dib8000_attach()
3927 	state->gpio_val = cfg->gpio_val;  in dib8000_attach()
3928 	state->gpio_dir = cfg->gpio_dir;  in dib8000_attach()
3933 …if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_P…  in dib8000_attach()
3934 		state->cfg.output_mode = OUTMODE_MPEG2_FIFO;  in dib8000_attach()
3936 	state->fe[0] = fe;  in dib8000_attach()
3937 	fe->demodulator_priv = state;  in dib8000_attach()
3938 	memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));  in dib8000_attach()
3940 	state->timf_default = cfg->pll->timf;  in dib8000_attach()
3942 	if (dib8000_identify(&state->i2c) == 0)  in dib8000_attach()
3945 	dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);  in dib8000_attach()
3948 	strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",  in dib8000_attach()
3949 			sizeof(state->dib8096p_tuner_adap.name));  in dib8000_attach()
3950 	state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;  in dib8000_attach()
3951 	state->dib8096p_tuner_adap.algo_data = NULL;  in dib8000_attach()
3952 	state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;  in dib8000_attach()
3953 	i2c_set_adapdata(&state->dib8096p_tuner_adap, state);  in dib8000_attach()
3954 	i2c_add_adapter(&state->dib8096p_tuner_adap);  in dib8000_attach()
3958 …dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));	/* ber_rs_len …  in dib8000_attach()
3959 	state->current_demod_bw = 6000;  in dib8000_attach()
3964 	kfree(state);  in dib8000_attach()