Lines Matching refs:state
245 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) in Read16() argument
247 u8 adr = state->config.demod_address; in Read16()
252 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) in Read16()
259 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) in Read32() argument
261 u8 adr = state->config.demod_address; in Read32()
267 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) in Read32()
275 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) in Write16() argument
277 u8 adr = state->config.demod_address; in Write16()
283 if (i2c_write(state->i2c, adr, mm, 6) < 0) in Write16()
288 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) in Write32() argument
290 u8 adr = state->config.demod_address; in Write32()
297 if (i2c_write(state->i2c, adr, mm, 8) < 0) in Write32()
302 static int write_chunk(struct drxd_state *state, in write_chunk() argument
305 u8 adr = state->config.demod_address; in write_chunk()
313 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { in write_chunk()
320 static int WriteBlock(struct drxd_state *state, in WriteBlock() argument
326 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) in WriteBlock()
335 static int WriteTable(struct drxd_state *state, u8 * pTable) in WriteTable() argument
355 status = WriteBlock(state, Address, Length * 2, pTable, 0); in WriteTable()
365 static int ResetCEFR(struct drxd_state *state) in ResetCEFR() argument
367 return WriteTable(state, state->m_ResetCEFR); in ResetCEFR()
370 static int InitCP(struct drxd_state *state) in InitCP() argument
372 return WriteTable(state, state->m_InitCP); in InitCP()
375 static int InitCE(struct drxd_state *state) in InitCE() argument
378 enum app_env AppEnv = state->app_env_default; in InitCE()
381 status = WriteTable(state, state->m_InitCE); in InitCE()
385 if (state->operation_mode == OM_DVBT_Diversity_Front || in InitCE()
386 state->operation_mode == OM_DVBT_Diversity_End) { in InitCE()
387 AppEnv = state->app_env_diversity; in InitCE()
390 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); in InitCE()
394 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); in InitCE()
397 } else if (AppEnv == APPENV_MOBILE && state->type_A) { in InitCE()
398 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); in InitCE()
401 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { in InitCE()
402 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); in InitCE()
408 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); in InitCE()
415 static int StopOC(struct drxd_state *state) in StopOC() argument
419 u16 ocModeLop = state->m_EcOcRegOcModeLop; in StopOC()
425 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); in StopOC()
429 state->m_EcOcRegSncSncLvl = ocSyncLvl; in StopOC()
433 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); in StopOC()
436 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); in StopOC()
439 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); in StopOC()
442 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); in StopOC()
447 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
450 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StopOC()
456 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); in StopOC()
462 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); in StopOC()
468 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
471 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); in StopOC()
474 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StopOC()
482 static int StartOC(struct drxd_state *state) in StartOC() argument
488 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StartOC()
493 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
496 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
501 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); in StartOC()
506 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StartOC()
513 static int InitEQ(struct drxd_state *state) in InitEQ() argument
515 return WriteTable(state, state->m_InitEQ); in InitEQ()
518 static int InitEC(struct drxd_state *state) in InitEC() argument
520 return WriteTable(state, state->m_InitEC); in InitEC()
523 static int InitSC(struct drxd_state *state) in InitSC() argument
525 return WriteTable(state, state->m_InitSC); in InitSC()
528 static int InitAtomicRead(struct drxd_state *state) in InitAtomicRead() argument
530 return WriteTable(state, state->m_InitAtomicRead); in InitAtomicRead()
533 static int CorrectSysClockDeviation(struct drxd_state *state);
535 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) in DRX_GetLockStatus() argument
549 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); in DRX_GetLockStatus()
555 if (state->drxd_state != DRXD_STARTED) in DRX_GetLockStatus()
560 CorrectSysClockDeviation(state); in DRX_GetLockStatus()
573 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) in SetCfgIfAgc() argument
585 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
590 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
596 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); in SetCfgIfAgc()
614 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
620 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
628 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); in SetCfgIfAgc()
639 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); in SetCfgIfAgc()
642 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); in SetCfgIfAgc()
690 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); in SetCfgIfAgc()
693 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); in SetCfgIfAgc()
696 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); in SetCfgIfAgc()
699 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); in SetCfgIfAgc()
702 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); in SetCfgIfAgc()
716 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) in SetCfgRfAgc() argument
731 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); in SetCfgRfAgc()
738 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); in SetCfgRfAgc()
739 state->m_FeAgRegAgPwd |= in SetCfgRfAgc()
741 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
745 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
752 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
759 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
766 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
779 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
781 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
783 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
787 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
794 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
800 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); in SetCfgRfAgc()
811 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
818 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
830 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
832 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
834 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
838 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
845 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
852 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
859 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
868 static int ReadIFAgc(struct drxd_state *state, u32 * pValue) in ReadIFAgc() argument
873 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { in ReadIFAgc()
875 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); in ReadIFAgc()
888 u32 R1 = state->if_agc_cfg.R1; in ReadIFAgc()
889 u32 R2 = state->if_agc_cfg.R2; in ReadIFAgc()
890 u32 R3 = state->if_agc_cfg.R3; in ReadIFAgc()
908 static int load_firmware(struct drxd_state *state, const char *fw_name) in load_firmware() argument
912 if (request_firmware(&fw, fw_name, state->dev) < 0) { in load_firmware()
917 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); in load_firmware()
918 if (state->microcode == NULL) { in load_firmware()
924 state->microcode_length = fw->size; in load_firmware()
929 static int DownloadMicrocode(struct drxd_state *state, in DownloadMicrocode() argument
968 status = WriteBlock(state, Address, BlockSize, in DownloadMicrocode()
979 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) in HI_Command() argument
985 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); in HI_Command()
995 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); in HI_Command()
999 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); in HI_Command()
1003 static int HI_CfgCommand(struct drxd_state *state) in HI_CfgCommand() argument
1007 mutex_lock(&state->mutex); in HI_CfgCommand()
1008 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); in HI_CfgCommand()
1009 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); in HI_CfgCommand()
1010 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); in HI_CfgCommand()
1011 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); in HI_CfgCommand()
1012 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); in HI_CfgCommand()
1014 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); in HI_CfgCommand()
1016 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == in HI_CfgCommand()
1018 status = Write16(state, HI_RA_RAM_SRV_CMD__A, in HI_CfgCommand()
1021 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0); in HI_CfgCommand()
1022 mutex_unlock(&state->mutex); in HI_CfgCommand()
1026 static int InitHI(struct drxd_state *state) in InitHI() argument
1028 state->hi_cfg_wakeup_key = (state->chip_adr); in InitHI()
1030 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; in InitHI()
1031 return HI_CfgCommand(state); in InitHI()
1034 static int HI_ResetCommand(struct drxd_state *state) in HI_ResetCommand() argument
1038 mutex_lock(&state->mutex); in HI_ResetCommand()
1039 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, in HI_ResetCommand()
1042 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0); in HI_ResetCommand()
1043 mutex_unlock(&state->mutex); in HI_ResetCommand()
1048 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) in DRX_ConfigureI2CBridge() argument
1050 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); in DRX_ConfigureI2CBridge()
1052 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; in DRX_ConfigureI2CBridge()
1054 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; in DRX_ConfigureI2CBridge()
1056 return HI_CfgCommand(state); in DRX_ConfigureI2CBridge()
1065 static int AtomicReadBlock(struct drxd_state *state,
1075 mutex_lock(&state->mutex);
1080 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1083 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1086 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1089 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1092 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1096 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1106 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1114 mutex_unlock(&state->mutex);
1118 static int AtomicReadReg32(struct drxd_state *state,
1126 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1134 static int StopAllProcessors(struct drxd_state *state) in StopAllProcessors() argument
1136 return Write16(state, HI_COMM_EXEC__A, in StopAllProcessors()
1140 static int EnableAndResetMB(struct drxd_state *state) in EnableAndResetMB() argument
1142 if (state->type_A) { in EnableAndResetMB()
1144 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); in EnableAndResetMB()
1148 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); in EnableAndResetMB()
1149 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); in EnableAndResetMB()
1153 static int InitCC(struct drxd_state *state) in InitCC() argument
1155 if (state->osc_clock_freq == 0 || in InitCC()
1156 state->osc_clock_freq > 20000 || in InitCC()
1157 (state->osc_clock_freq % 4000) != 0) { in InitCC()
1158 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); in InitCC()
1162 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); in InitCC()
1163 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | in InitCC()
1165 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0); in InitCC()
1166 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); in InitCC()
1167 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); in InitCC()
1172 static int ResetECOD(struct drxd_state *state) in ResetECOD() argument
1176 if (state->type_A) in ResetECOD()
1177 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1179 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1182 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1184 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); in ResetECOD()
1190 static int SetCfgPga(struct drxd_state *state, int pgaSwitch) in SetCfgPga() argument
1199 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1204 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1209 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1214 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1220 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x000… in SetCfgPga()
1227 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1232 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1237 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1242 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1248 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x000… in SetCfgPga()
1256 static int InitFE(struct drxd_state *state) in InitFE() argument
1261 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1265 if (state->type_A) { in InitFE()
1266 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1270 if (state->PGA) in InitFE()
1271 status = SetCfgPga(state, 0); in InitFE()
1274 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1281 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1284 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1288 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1297 static int InitFT(struct drxd_state *state) in InitFT() argument
1303 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000); in InitFT()
1306 static int SC_WaitForReady(struct drxd_state *state) in SC_WaitForReady() argument
1312 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); in SC_WaitForReady()
1319 static int SC_SendCommand(struct drxd_state *state, u16 cmd) in SC_SendCommand() argument
1324 Write16(state, SC_RA_RAM_CMD__A, cmd, 0); in SC_SendCommand()
1325 SC_WaitForReady(state); in SC_SendCommand()
1327 Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); in SC_SendCommand()
1337 static int SC_ProcStartCommand(struct drxd_state *state, in SC_ProcStartCommand() argument
1343 mutex_lock(&state->mutex); in SC_ProcStartCommand()
1345 Read16(state, SC_COMM_EXEC__A, &scExec, 0); in SC_ProcStartCommand()
1350 SC_WaitForReady(state); in SC_ProcStartCommand()
1351 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_ProcStartCommand()
1352 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_ProcStartCommand()
1353 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_ProcStartCommand()
1355 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); in SC_ProcStartCommand()
1357 mutex_unlock(&state->mutex); in SC_ProcStartCommand()
1361 static int SC_SetPrefParamCommand(struct drxd_state *state, in SC_SetPrefParamCommand() argument
1366 mutex_lock(&state->mutex); in SC_SetPrefParamCommand()
1368 status = SC_WaitForReady(state); in SC_SetPrefParamCommand()
1371 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_SetPrefParamCommand()
1374 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_SetPrefParamCommand()
1377 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_SetPrefParamCommand()
1381 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); in SC_SetPrefParamCommand()
1385 mutex_unlock(&state->mutex); in SC_SetPrefParamCommand()
1390 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1394 mutex_lock(&state->mutex);
1396 status = SC_WaitForReady(state);
1399 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1402 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1406 mutex_unlock(&state->mutex);
1411 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) in ConfigureMPEGOutput() argument
1423 if (state->operation_mode == OM_DVBT_Diversity_Front) { in ConfigureMPEGOutput()
1432 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; in ConfigureMPEGOutput()
1440 if (state->insert_rs_byte) { in ConfigureMPEGOutput()
1457 if (state->enable_parallel) in ConfigureMPEGOutput()
1485 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); in ConfigureMPEGOutput()
1488 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); in ConfigureMPEGOutput()
1491 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); in ConfigureMPEGOutput()
1494 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); in ConfigureMPEGOutput()
1501 static int SetDeviceTypeId(struct drxd_state *state) in SetDeviceTypeId() argument
1507 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1511 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1516 state->type_A = 0; in SetDeviceTypeId()
1517 state->PGA = 0; in SetDeviceTypeId()
1518 state->diversity = 0; in SetDeviceTypeId()
1520 state->type_A = 1; in SetDeviceTypeId()
1527 state->diversity = 1; in SetDeviceTypeId()
1530 state->PGA = 1; in SetDeviceTypeId()
1533 state->diversity = 1; in SetDeviceTypeId()
1548 state->m_InitAtomicRead = DRXD_InitAtomicRead; in SetDeviceTypeId()
1549 state->m_InitSC = DRXD_InitSC; in SetDeviceTypeId()
1550 state->m_ResetECRAM = DRXD_ResetECRAM; in SetDeviceTypeId()
1551 if (state->type_A) { in SetDeviceTypeId()
1552 state->m_ResetCEFR = DRXD_ResetCEFR; in SetDeviceTypeId()
1553 state->m_InitFE_1 = DRXD_InitFEA2_1; in SetDeviceTypeId()
1554 state->m_InitFE_2 = DRXD_InitFEA2_2; in SetDeviceTypeId()
1555 state->m_InitCP = DRXD_InitCPA2; in SetDeviceTypeId()
1556 state->m_InitCE = DRXD_InitCEA2; in SetDeviceTypeId()
1557 state->m_InitEQ = DRXD_InitEQA2; in SetDeviceTypeId()
1558 state->m_InitEC = DRXD_InitECA2; in SetDeviceTypeId()
1559 if (load_firmware(state, DRX_FW_FILENAME_A2)) in SetDeviceTypeId()
1562 state->m_ResetCEFR = NULL; in SetDeviceTypeId()
1563 state->m_InitFE_1 = DRXD_InitFEB1_1; in SetDeviceTypeId()
1564 state->m_InitFE_2 = DRXD_InitFEB1_2; in SetDeviceTypeId()
1565 state->m_InitCP = DRXD_InitCPB1; in SetDeviceTypeId()
1566 state->m_InitCE = DRXD_InitCEB1; in SetDeviceTypeId()
1567 state->m_InitEQ = DRXD_InitEQB1; in SetDeviceTypeId()
1568 state->m_InitEC = DRXD_InitECB1; in SetDeviceTypeId()
1569 if (load_firmware(state, DRX_FW_FILENAME_B1)) in SetDeviceTypeId()
1572 if (state->diversity) { in SetDeviceTypeId()
1573 state->m_InitDiversityFront = DRXD_InitDiversityFront; in SetDeviceTypeId()
1574 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; in SetDeviceTypeId()
1575 state->m_DisableDiversity = DRXD_DisableDiversity; in SetDeviceTypeId()
1576 state->m_StartDiversityFront = DRXD_StartDiversityFront; in SetDeviceTypeId()
1577 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; in SetDeviceTypeId()
1578 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; in SetDeviceTypeId()
1579 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; in SetDeviceTypeId()
1581 state->m_InitDiversityFront = NULL; in SetDeviceTypeId()
1582 state->m_InitDiversityEnd = NULL; in SetDeviceTypeId()
1583 state->m_DisableDiversity = NULL; in SetDeviceTypeId()
1584 state->m_StartDiversityFront = NULL; in SetDeviceTypeId()
1585 state->m_StartDiversityEnd = NULL; in SetDeviceTypeId()
1586 state->m_DiversityDelay8MHZ = NULL; in SetDeviceTypeId()
1587 state->m_DiversityDelay6MHZ = NULL; in SetDeviceTypeId()
1593 static int CorrectSysClockDeviation(struct drxd_state *state) in CorrectSysClockDeviation() argument
1609 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); in CorrectSysClockDeviation()
1612 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); in CorrectSysClockDeviation()
1616 if (state->type_A) { in CorrectSysClockDeviation()
1624 switch (state->props.bandwidth_hz) { in CorrectSysClockDeviation()
1651 (state->expected_sys_clock_freq)) * in CorrectSysClockDeviation()
1654 (state->expected_sys_clock_freq)); in CorrectSysClockDeviation()
1656 Diff = oscClockDeviation - state->osc_clock_deviation; in CorrectSysClockDeviation()
1659 state->sys_clock_freq = (u16) sysClockFreq; in CorrectSysClockDeviation()
1660 if (oscClockDeviation != state->osc_clock_deviation) { in CorrectSysClockDeviation()
1661 if (state->config.osc_deviation) { in CorrectSysClockDeviation()
1662 state->config.osc_deviation(state->priv, in CorrectSysClockDeviation()
1665 state->osc_clock_deviation = in CorrectSysClockDeviation()
1670 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); in CorrectSysClockDeviation()
1675 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1678 state->cscd_state = CSCD_SAVED; in CorrectSysClockDeviation()
1685 static int DRX_Stop(struct drxd_state *state) in DRX_Stop() argument
1689 if (state->drxd_state != DRXD_STARTED) in DRX_Stop()
1693 if (state->cscd_state != CSCD_SAVED) { in DRX_Stop()
1695 status = DRX_GetLockStatus(state, &lock); in DRX_Stop()
1700 status = StopOC(state); in DRX_Stop()
1704 state->drxd_state = DRXD_STOPPED; in DRX_Stop()
1706 status = ConfigureMPEGOutput(state, 0); in DRX_Stop()
1710 if (state->type_A) { in DRX_Stop()
1712 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); in DRX_Stop()
1716 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1719 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1724 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1727 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1730 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1733 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1736 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1739 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1742 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); in DRX_Stop()
1752 static int SetOperationMode(struct drxd_state *state, int oMode)
1757 if (state->drxd_state != DRXD_STOPPED) {
1762 if (oMode == state->operation_mode) {
1767 if (oMode != OM_Default && !state->diversity) {
1774 status = WriteTable(state, state->m_InitDiversityFront);
1777 status = WriteTable(state, state->m_InitDiversityEnd);
1783 status = WriteTable(state, state->m_DisableDiversity);
1789 state->operation_mode = oMode;
1794 static int StartDiversity(struct drxd_state *state) in StartDiversity() argument
1800 if (state->operation_mode == OM_DVBT_Diversity_Front) { in StartDiversity()
1801 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1804 } else if (state->operation_mode == OM_DVBT_Diversity_End) { in StartDiversity()
1805 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1808 if (state->props.bandwidth_hz == 8000000) { in StartDiversity()
1809 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1813 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1818 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); in StartDiversity()
1827 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); in StartDiversity()
1835 static int SetFrequencyShift(struct drxd_state *state, in SetFrequencyShift() argument
1838 int negativeShift = (state->tuner_mirrors == channelMirrored); in SetFrequencyShift()
1851 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + in SetFrequencyShift()
1853 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1855 state->fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1857 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); in SetFrequencyShift()
1861 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, in SetFrequencyShift()
1862 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1864 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1866 state->org_fe_fs_add_incr = ((1L << 28) - in SetFrequencyShift()
1867 state->org_fe_fs_add_incr); in SetFrequencyShift()
1869 return Write32(state, FE_FS_REG_ADD_INC_LOP__A, in SetFrequencyShift()
1870 state->fe_fs_add_incr, 0); in SetFrequencyShift()
1873 static int SetCfgNoiseCalibration(struct drxd_state *state, in SetCfgNoiseCalibration() argument
1880 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); in SetCfgNoiseCalibration()
1887 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1891 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); in SetCfgNoiseCalibration()
1895 if (!state->type_A) { in SetCfgNoiseCalibration()
1896 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1899 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1908 static int DRX_Start(struct drxd_state *state, s32 off) in DRX_Start() argument
1910 struct dtv_frontend_properties *p = &state->props; in DRX_Start()
1939 if (state->drxd_state != DRXD_STOPPED) in DRX_Start()
1941 status = ResetECOD(state); in DRX_Start()
1944 if (state->type_A) { in DRX_Start()
1945 status = InitSC(state); in DRX_Start()
1949 status = InitFT(state); in DRX_Start()
1952 status = InitCP(state); in DRX_Start()
1955 status = InitCE(state); in DRX_Start()
1958 status = InitEQ(state); in DRX_Start()
1961 status = InitSC(state); in DRX_Start()
1968 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1971 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1975 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); in DRX_Start()
1983 if (state->type_A) { in DRX_Start()
1984 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); in DRX_Start()
1994 if (state->type_A) { in DRX_Start()
1995 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); in DRX_Start()
2028 if (state->type_A) { in DRX_Start()
2029 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2032 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2058 if (state->type_A) { in DRX_Start()
2059 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2062 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2087 if (state->type_A) { in DRX_Start()
2088 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2091 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2119 if (state->type_A) { in DRX_Start()
2120 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2123 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2158 if (state->type_A) { in DRX_Start()
2159 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); in DRX_Start()
2162 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); in DRX_Start()
2165 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); in DRX_Start()
2168 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); in DRX_Start()
2171 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); in DRX_Start()
2175 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); in DRX_Start()
2178 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); in DRX_Start()
2181 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); in DRX_Start()
2184 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); in DRX_Start()
2191 if (state->type_A) { in DRX_Start()
2192 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); in DRX_Start()
2195 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); in DRX_Start()
2198 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2201 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); in DRX_Start()
2204 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2208 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); in DRX_Start()
2211 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); in DRX_Start()
2214 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); in DRX_Start()
2217 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); in DRX_Start()
2225 if (state->type_A) { in DRX_Start()
2226 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); in DRX_Start()
2229 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); in DRX_Start()
2232 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2235 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); in DRX_Start()
2238 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2242 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); in DRX_Start()
2245 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); in DRX_Start()
2248 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); in DRX_Start()
2251 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); in DRX_Start()
2267 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); in DRX_Start()
2273 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); in DRX_Start()
2283 if (state->type_A) { in DRX_Start()
2284 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); in DRX_Start()
2293 if (state->type_A) { in DRX_Start()
2294 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); in DRX_Start()
2301 if (state->type_A) { in DRX_Start()
2302 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); in DRX_Start()
2309 if (state->type_A) { in DRX_Start()
2310 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); in DRX_Start()
2317 if (state->type_A) { in DRX_Start()
2318 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); in DRX_Start()
2344 status = Write16(state, in DRX_Start()
2351 status = Write16(state, in DRX_Start()
2358 status = Write16(state, in DRX_Start()
2367 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); in DRX_Start()
2373 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); in DRX_Start()
2387 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); in DRX_Start()
2392 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2396 if (state->cscd_state == CSCD_INIT) { in DRX_Start()
2398 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); in DRX_Start()
2402 state->cscd_state = CSCD_SET; in DRX_Start()
2408 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, in DRX_Start()
2410 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); in DRX_Start()
2413 …status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_IN… in DRX_Start()
2419 SetFrequencyShift(state, off, mirrorFreqSpect); in DRX_Start()
2424 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); in DRX_Start()
2427 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); in DRX_Start()
2439 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); in DRX_Start()
2444 …status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_… in DRX_Start()
2448 status = StartOC(state); in DRX_Start()
2452 if (state->operation_mode != OM_Default) { in DRX_Start()
2453 status = StartDiversity(state); in DRX_Start()
2458 state->drxd_state = DRXD_STARTED; in DRX_Start()
2464 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) in CDRXD() argument
2484 u32 ulClock = state->config.clock; in CDRXD()
2494 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2495 state->if_agc_cfg.outputLevel = 0; in CDRXD()
2496 state->if_agc_cfg.settleLevel = 140; in CDRXD()
2497 state->if_agc_cfg.minOutputLevel = 0; in CDRXD()
2498 state->if_agc_cfg.maxOutputLevel = 1023; in CDRXD()
2499 state->if_agc_cfg.speed = 904; in CDRXD()
2502 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2503 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); in CDRXD()
2511 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2512 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); in CDRXD()
2513 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); in CDRXD()
2514 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); in CDRXD()
2515 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); in CDRXD()
2518 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); in CDRXD()
2519 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); in CDRXD()
2520 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); in CDRXD()
2522 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); in CDRXD()
2523 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); in CDRXD()
2524 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); in CDRXD()
2526 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2529 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2530 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); in CDRXD()
2538 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2539 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); in CDRXD()
2540 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); in CDRXD()
2541 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); in CDRXD()
2542 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); in CDRXD()
2546 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; in CDRXD()
2549 state->app_env_default = (enum app_env) in CDRXD()
2552 state->app_env_diversity = (enum app_env) in CDRXD()
2557 state->noise_cal.cpOpt = 0; in CDRXD()
2558 state->noise_cal.cpNexpOfs = 40; in CDRXD()
2559 state->noise_cal.tdCal2k = -40; in CDRXD()
2560 state->noise_cal.tdCal8k = -24; in CDRXD()
2563 state->noise_cal.cpOpt = 1; in CDRXD()
2564 state->noise_cal.cpNexpOfs = 0; in CDRXD()
2565 state->noise_cal.tdCal2k = -21; in CDRXD()
2566 state->noise_cal.tdCal8k = -24; in CDRXD()
2568 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); in CDRXD()
2570 state->chip_adr = (state->config.demod_address << 1) | 1; in CDRXD()
2573 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; in CDRXD()
2576 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; in CDRXD()
2579 state->m_HiI2cPatch = NULL; in CDRXD()
2583 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); in CDRXD()
2585 state->expected_sys_clock_freq = 48000; in CDRXD()
2587 state->sys_clock_freq = 48000; in CDRXD()
2588 state->osc_clock_freq = (u16) ulClock; in CDRXD()
2589 state->osc_clock_deviation = 0; in CDRXD()
2590 state->cscd_state = CSCD_INIT; in CDRXD()
2591 state->drxd_state = DRXD_UNINITIALIZED; in CDRXD()
2593 state->PGA = 0; in CDRXD()
2594 state->type_A = 0; in CDRXD()
2595 state->tuner_mirrors = 0; in CDRXD()
2598 state->insert_rs_byte = state->config.insert_rs_byte; in CDRXD()
2599 state->enable_parallel = (ulSerialMode != 1); in CDRXD()
2604 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * in CDRXD()
2608 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * in CDRXD()
2611 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in CDRXD()
2613 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in CDRXD()
2617 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) in DRXD_init() argument
2622 if (state->init_done) in DRXD_init()
2625 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in DRXD_init()
2628 state->operation_mode = OM_Default; in DRXD_init()
2630 status = SetDeviceTypeId(state); in DRXD_init()
2635 if (!state->type_A && state->m_HiI2cPatch != NULL) in DRXD_init()
2636 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2640 if (state->type_A) { in DRXD_init()
2643 status = Write16(state, 0x43012D, 0x047f, 0); in DRXD_init()
2648 status = HI_ResetCommand(state); in DRXD_init()
2652 status = StopAllProcessors(state); in DRXD_init()
2655 status = InitCC(state); in DRXD_init()
2659 state->osc_clock_deviation = 0; in DRXD_init()
2661 if (state->config.osc_deviation) in DRXD_init()
2662 state->osc_clock_deviation = in DRXD_init()
2663 state->config.osc_deviation(state->priv, 0, 0); in DRXD_init()
2667 s32 devA = (s32) (state->osc_clock_deviation) * in DRXD_init()
2668 (s32) (state->expected_sys_clock_freq); in DRXD_init()
2681 state->sys_clock_freq = in DRXD_init()
2682 (u16) ((state->expected_sys_clock_freq) + in DRXD_init()
2685 status = InitHI(state); in DRXD_init()
2688 status = InitAtomicRead(state); in DRXD_init()
2692 status = EnableAndResetMB(state); in DRXD_init()
2695 if (state->type_A) in DRXD_init()
2696 status = ResetCEFR(state); in DRXD_init()
2701 status = DownloadMicrocode(state, fw, fw_size); in DRXD_init()
2705 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2710 if (state->PGA) { in DRXD_init()
2711 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; in DRXD_init()
2712 SetCfgPga(state, 0); /* PGA = 0 dB */ in DRXD_init()
2714 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in DRXD_init()
2717 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in DRXD_init()
2719 status = InitFE(state); in DRXD_init()
2722 status = InitFT(state); in DRXD_init()
2725 status = InitCP(state); in DRXD_init()
2728 status = InitCE(state); in DRXD_init()
2731 status = InitEQ(state); in DRXD_init()
2734 status = InitEC(state); in DRXD_init()
2737 status = InitSC(state); in DRXD_init()
2741 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2744 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2748 state->cscd_state = CSCD_INIT; in DRXD_init()
2749 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2752 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2764 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); in DRXD_init()
2768 status = StopOC(state); in DRXD_init()
2772 state->drxd_state = DRXD_STOPPED; in DRXD_init()
2773 state->init_done = 1; in DRXD_init()
2779 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus) in DRXD_status() argument
2781 DRX_GetLockStatus(state, pLockStatus); in DRXD_status()
2785 ConfigureMPEGOutput(state, 1); in DRXD_status()
2799 struct drxd_state *state = fe->demodulator_priv; in drxd_read_signal_strength() local
2803 res = ReadIFAgc(state, &value); in drxd_read_signal_strength()
2813 struct drxd_state *state = fe->demodulator_priv; in drxd_read_status() local
2816 DRXD_status(state, &lock); in drxd_read_status()
2836 struct drxd_state *state = fe->demodulator_priv; in drxd_init() local
2840 return DRXD_init(state, 0, 0); in drxd_init()
2842 err = DRXD_init(state, state->fw->data, state->fw->size); in drxd_init()
2843 release_firmware(state->fw); in drxd_init()
2849 struct drxd_state *state = fe->demodulator_priv; in drxd_config_i2c() local
2851 if (state->config.disable_i2c_gate_ctrl == 1) in drxd_config_i2c()
2854 return DRX_ConfigureI2CBridge(state, onoff); in drxd_config_i2c()
2887 struct drxd_state *state = fe->demodulator_priv; in drxd_sleep() local
2889 ConfigureMPEGOutput(state, 0); in drxd_sleep()
2901 struct drxd_state *state = fe->demodulator_priv; in drxd_set_frontend() local
2904 state->props = *p; in drxd_set_frontend()
2905 DRX_Stop(state); in drxd_set_frontend()
2915 return DRX_Start(state, off); in drxd_set_frontend()
2920 struct drxd_state *state = fe->demodulator_priv; in drxd_release() local
2922 kfree(state); in drxd_release()
2961 struct drxd_state *state = NULL; in drxd_attach() local
2963 state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL); in drxd_attach()
2964 if (!state) in drxd_attach()
2966 memset(state, 0, sizeof(*state)); in drxd_attach()
2968 state->ops = drxd_ops; in drxd_attach()
2969 state->dev = dev; in drxd_attach()
2970 state->config = *config; in drxd_attach()
2971 state->i2c = i2c; in drxd_attach()
2972 state->priv = priv; in drxd_attach()
2974 mutex_init(&state->mutex); in drxd_attach()
2976 if (Read16(state, 0, 0, 0) < 0) in drxd_attach()
2979 state->frontend.ops = drxd_ops; in drxd_attach()
2980 state->frontend.demodulator_priv = state; in drxd_attach()
2981 ConfigureMPEGOutput(state, 0); in drxd_attach()
2983 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in drxd_attach()
2984 InitHI(state); in drxd_attach()
2986 return &state->frontend; in drxd_attach()
2990 kfree(state); in drxd_attach()