Lines Matching refs:state
38 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
39 static int PowerDownQAM(struct drxk_state *state);
40 static int SetDVBTStandard(struct drxk_state *state,
42 static int SetQAMStandard(struct drxk_state *state,
44 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
46 static int SetDVBTStandard(struct drxk_state *state,
48 static int DVBTStart(struct drxk_state *state);
49 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
51 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
53 static int SwitchAntennaToQAM(struct drxk_state *state);
54 static int SwitchAntennaToDVBT(struct drxk_state *state);
56 static bool IsDVBT(struct drxk_state *state) in IsDVBT() argument
58 return state->m_OperationMode == OM_DVBT; in IsDVBT()
61 static bool IsQAM(struct drxk_state *state) in IsQAM() argument
63 return state->m_OperationMode == OM_QAM_ITU_A || in IsQAM()
64 state->m_OperationMode == OM_QAM_ITU_B || in IsQAM()
65 state->m_OperationMode == OM_QAM_ITU_C; in IsQAM()
107 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
110 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
113 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
302 static int drxk_i2c_lock(struct drxk_state *state) in drxk_i2c_lock() argument
304 i2c_lock_adapter(state->i2c); in drxk_i2c_lock()
305 state->drxk_i2c_exclusive_lock = true; in drxk_i2c_lock()
310 static void drxk_i2c_unlock(struct drxk_state *state) in drxk_i2c_unlock() argument
312 if (!state->drxk_i2c_exclusive_lock) in drxk_i2c_unlock()
315 i2c_unlock_adapter(state->i2c); in drxk_i2c_unlock()
316 state->drxk_i2c_exclusive_lock = false; in drxk_i2c_unlock()
319 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs, in drxk_i2c_transfer() argument
322 if (state->drxk_i2c_exclusive_lock) in drxk_i2c_transfer()
323 return __i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
325 return i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
328 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) in i2c_read1() argument
334 return drxk_i2c_transfer(state, msgs, 1); in i2c_read1()
337 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) in i2c_write() argument
350 status = drxk_i2c_transfer(state, &msg, 1); in i2c_write()
360 static int i2c_read(struct drxk_state *state, in i2c_read() argument
371 status = drxk_i2c_transfer(state, msgs, 2); in i2c_read()
394 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) in read16_flags() argument
397 u8 adr = state->demod_address, mm1[4], mm2[2], len; in read16_flags()
399 if (state->single_master) in read16_flags()
414 status = i2c_read(state, adr, mm1, len, mm2, 2); in read16_flags()
423 static int read16(struct drxk_state *state, u32 reg, u16 *data) in read16() argument
425 return read16_flags(state, reg, data, 0); in read16()
428 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) in read32_flags() argument
431 u8 adr = state->demod_address, mm1[4], mm2[4], len; in read32_flags()
433 if (state->single_master) in read32_flags()
448 status = i2c_read(state, adr, mm1, len, mm2, 4); in read32_flags()
458 static int read32(struct drxk_state *state, u32 reg, u32 *data) in read32() argument
460 return read32_flags(state, reg, data, 0); in read32()
463 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) in write16_flags() argument
465 u8 adr = state->demod_address, mm[6], len; in write16_flags()
467 if (state->single_master) in write16_flags()
484 return i2c_write(state, adr, mm, len + 2); in write16_flags()
487 static int write16(struct drxk_state *state, u32 reg, u16 data) in write16() argument
489 return write16_flags(state, reg, data, 0); in write16()
492 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) in write32_flags() argument
494 u8 adr = state->demod_address, mm[8], len; in write32_flags()
496 if (state->single_master) in write32_flags()
515 return i2c_write(state, adr, mm, len + 4); in write32_flags()
518 static int write32(struct drxk_state *state, u32 reg, u32 data) in write32() argument
520 return write32_flags(state, reg, data, 0); in write32()
523 static int write_block(struct drxk_state *state, u32 Address, in write_block() argument
529 if (state->single_master) in write_block()
533 int Chunk = BlkSize > state->m_ChunkSize ? in write_block()
534 state->m_ChunkSize : BlkSize; in write_block()
535 u8 *AdrBuf = &state->Chunk[0]; in write_block()
545 if (Chunk == state->m_ChunkSize) in write_block()
553 memcpy(&state->Chunk[AdrLength], pBlock, Chunk); in write_block()
562 status = i2c_write(state, state->demod_address, in write_block()
563 &state->Chunk[0], Chunk + AdrLength); in write_block()
580 static int PowerUpDevice(struct drxk_state *state) in PowerUpDevice() argument
588 status = i2c_read1(state, state->demod_address, &data); in PowerUpDevice()
592 status = i2c_write(state, state->demod_address, in PowerUpDevice()
598 status = i2c_read1(state, state->demod_address, in PowerUpDevice()
607 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE); in PowerUpDevice()
610 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in PowerUpDevice()
614 status = write16(state, SIO_CC_PLL_LOCK__A, 1); in PowerUpDevice()
618 state->m_currentPowerMode = DRX_POWER_UP; in PowerUpDevice()
628 static int init_state(struct drxk_state *state) in init_state() argument
684 state->m_hasLNA = false; in init_state()
685 state->m_hasDVBT = false; in init_state()
686 state->m_hasDVBC = false; in init_state()
687 state->m_hasATV = false; in init_state()
688 state->m_hasOOB = false; in init_state()
689 state->m_hasAudio = false; in init_state()
691 if (!state->m_ChunkSize) in init_state()
692 state->m_ChunkSize = 124; in init_state()
694 state->m_oscClockFreq = 0; in init_state()
695 state->m_smartAntInverted = false; in init_state()
696 state->m_bPDownOpenBridge = false; in init_state()
699 state->m_sysClockFreq = 151875; in init_state()
702 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * in init_state()
705 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) in init_state()
706 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; in init_state()
707 state->m_HICfgWakeUpKey = (state->demod_address << 1); in init_state()
709 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_state()
711 state->m_bPowerDown = (ulPowerDown != 0); in init_state()
713 state->m_DRXK_A3_PATCH_CODE = false; in init_state()
717 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); in init_state()
718 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); in init_state()
719 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); in init_state()
720 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); in init_state()
721 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); in init_state()
722 state->m_vsbPgaCfg = 140; in init_state()
725 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); in init_state()
726 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); in init_state()
727 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); in init_state()
728 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); in init_state()
729 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); in init_state()
730 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); in init_state()
731 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); in init_state()
732 state->m_vsbPreSawCfg.reference = 0x07; in init_state()
733 state->m_vsbPreSawCfg.usePreSaw = true; in init_state()
735 state->m_Quality83percent = DEFAULT_MER_83; in init_state()
736 state->m_Quality93percent = DEFAULT_MER_93; in init_state()
738 state->m_Quality83percent = ulQual83; in init_state()
739 state->m_Quality93percent = ulQual93; in init_state()
743 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); in init_state()
744 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); in init_state()
745 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); in init_state()
746 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); in init_state()
747 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); in init_state()
750 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); in init_state()
751 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); in init_state()
752 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); in init_state()
753 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); in init_state()
754 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); in init_state()
755 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); in init_state()
756 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); in init_state()
757 state->m_atvPreSawCfg.reference = 0x04; in init_state()
758 state->m_atvPreSawCfg.usePreSaw = true; in init_state()
762 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; in init_state()
763 state->m_dvbtRfAgcCfg.outputLevel = 0; in init_state()
764 state->m_dvbtRfAgcCfg.minOutputLevel = 0; in init_state()
765 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; in init_state()
766 state->m_dvbtRfAgcCfg.top = 0x2100; in init_state()
767 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; in init_state()
768 state->m_dvbtRfAgcCfg.speed = 1; in init_state()
772 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; in init_state()
773 state->m_dvbtIfAgcCfg.outputLevel = 0; in init_state()
774 state->m_dvbtIfAgcCfg.minOutputLevel = 0; in init_state()
775 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; in init_state()
776 state->m_dvbtIfAgcCfg.top = 13424; in init_state()
777 state->m_dvbtIfAgcCfg.cutOffCurrent = 0; in init_state()
778 state->m_dvbtIfAgcCfg.speed = 3; in init_state()
779 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; in init_state()
780 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; in init_state()
783 state->m_dvbtPreSawCfg.reference = 4; in init_state()
784 state->m_dvbtPreSawCfg.usePreSaw = false; in init_state()
787 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; in init_state()
788 state->m_qamRfAgcCfg.outputLevel = 0; in init_state()
789 state->m_qamRfAgcCfg.minOutputLevel = 6023; in init_state()
790 state->m_qamRfAgcCfg.maxOutputLevel = 27000; in init_state()
791 state->m_qamRfAgcCfg.top = 0x2380; in init_state()
792 state->m_qamRfAgcCfg.cutOffCurrent = 4000; in init_state()
793 state->m_qamRfAgcCfg.speed = 3; in init_state()
796 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; in init_state()
797 state->m_qamIfAgcCfg.outputLevel = 0; in init_state()
798 state->m_qamIfAgcCfg.minOutputLevel = 0; in init_state()
799 state->m_qamIfAgcCfg.maxOutputLevel = 9000; in init_state()
800 state->m_qamIfAgcCfg.top = 0x0511; in init_state()
801 state->m_qamIfAgcCfg.cutOffCurrent = 0; in init_state()
802 state->m_qamIfAgcCfg.speed = 3; in init_state()
803 state->m_qamIfAgcCfg.IngainTgtMax = 5119; in init_state()
804 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; in init_state()
806 state->m_qamPgaCfg = 140; in init_state()
807 state->m_qamPreSawCfg.reference = 4; in init_state()
808 state->m_qamPreSawCfg.usePreSaw = false; in init_state()
810 state->m_OperationMode = OM_NONE; in init_state()
811 state->m_DrxkState = DRXK_UNINITIALIZED; in init_state()
814 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ in init_state()
815 state->m_insertRSByte = false; /* If TRUE; insert RS byte */ in init_state()
816 state->m_invertDATA = false; /* If TRUE; invert DATA signals */ in init_state()
817 state->m_invertERR = false; /* If TRUE; invert ERR signal */ in init_state()
818 state->m_invertSTR = false; /* If TRUE; invert STR signals */ in init_state()
819 state->m_invertVAL = false; /* If TRUE; invert VAL signals */ in init_state()
820 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ in init_state()
825 state->m_DVBTBitrate = ulDVBTBitrate; in init_state()
826 state->m_DVBCBitrate = ulDVBCBitrate; in init_state()
828 state->m_TSDataStrength = (ulTSDataStrength & 0x07); in init_state()
831 state->m_mpegTsStaticBitrate = 19392658; in init_state()
832 state->m_disableTEIhandling = false; in init_state()
835 state->m_insertRSByte = true; in init_state()
837 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; in init_state()
839 state->m_MpegLockTimeOut = ulMpegLockTimeOut; in init_state()
840 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; in init_state()
842 state->m_DemodLockTimeOut = ulDemodLockTimeOut; in init_state()
845 state->m_Constellation = DRX_CONSTELLATION_AUTO; in init_state()
846 state->m_qamInterleaveMode = DRXK_QAM_I12_J17; in init_state()
847 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */ in init_state()
848 state->m_fecRsPrescale = 1; in init_state()
850 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; in init_state()
851 state->m_agcFastClipCtrlDelay = 0; in init_state()
853 state->m_GPIOCfg = (ulGPIOCfg); in init_state()
855 state->m_bPowerDown = false; in init_state()
856 state->m_currentPowerMode = DRX_POWER_DOWN; in init_state()
858 state->m_rfmirror = (ulRfMirror == 0); in init_state()
859 state->m_IfAgcPol = false; in init_state()
863 static int DRXX_Open(struct drxk_state *state) in DRXX_Open() argument
872 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in DRXX_Open()
876 status = read16(state, SIO_TOP_COMM_KEY__A, &key); in DRXX_Open()
879 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in DRXX_Open()
882 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag); in DRXX_Open()
885 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid); in DRXX_Open()
888 status = write16(state, SIO_TOP_COMM_KEY__A, key); in DRXX_Open()
895 static int GetDeviceCapabilities(struct drxk_state *state) in GetDeviceCapabilities() argument
906 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in GetDeviceCapabilities()
909 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in GetDeviceCapabilities()
912 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); in GetDeviceCapabilities()
915 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in GetDeviceCapabilities()
925 state->m_oscClockFreq = 27000; in GetDeviceCapabilities()
929 state->m_oscClockFreq = 20250; in GetDeviceCapabilities()
933 state->m_oscClockFreq = 20250; in GetDeviceCapabilities()
943 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); in GetDeviceCapabilities()
952 state->m_deviceSpin = DRXK_SPIN_A1; in GetDeviceCapabilities()
956 state->m_deviceSpin = DRXK_SPIN_A2; in GetDeviceCapabilities()
960 state->m_deviceSpin = DRXK_SPIN_A3; in GetDeviceCapabilities()
964 state->m_deviceSpin = DRXK_SPIN_UNKNOWN; in GetDeviceCapabilities()
973 state->m_hasLNA = false; in GetDeviceCapabilities()
974 state->m_hasOOB = false; in GetDeviceCapabilities()
975 state->m_hasATV = false; in GetDeviceCapabilities()
976 state->m_hasAudio = false; in GetDeviceCapabilities()
977 state->m_hasDVBT = true; in GetDeviceCapabilities()
978 state->m_hasDVBC = true; in GetDeviceCapabilities()
979 state->m_hasSAWSW = true; in GetDeviceCapabilities()
980 state->m_hasGPIO2 = false; in GetDeviceCapabilities()
981 state->m_hasGPIO1 = false; in GetDeviceCapabilities()
982 state->m_hasIRQN = false; in GetDeviceCapabilities()
986 state->m_hasLNA = false; in GetDeviceCapabilities()
987 state->m_hasOOB = false; in GetDeviceCapabilities()
988 state->m_hasATV = true; in GetDeviceCapabilities()
989 state->m_hasAudio = false; in GetDeviceCapabilities()
990 state->m_hasDVBT = true; in GetDeviceCapabilities()
991 state->m_hasDVBC = false; in GetDeviceCapabilities()
992 state->m_hasSAWSW = true; in GetDeviceCapabilities()
993 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
994 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
995 state->m_hasIRQN = false; in GetDeviceCapabilities()
999 state->m_hasLNA = false; in GetDeviceCapabilities()
1000 state->m_hasOOB = false; in GetDeviceCapabilities()
1001 state->m_hasATV = true; in GetDeviceCapabilities()
1002 state->m_hasAudio = false; in GetDeviceCapabilities()
1003 state->m_hasDVBT = true; in GetDeviceCapabilities()
1004 state->m_hasDVBC = false; in GetDeviceCapabilities()
1005 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1006 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1007 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1008 state->m_hasIRQN = false; in GetDeviceCapabilities()
1012 state->m_hasLNA = false; in GetDeviceCapabilities()
1013 state->m_hasOOB = false; in GetDeviceCapabilities()
1014 state->m_hasATV = true; in GetDeviceCapabilities()
1015 state->m_hasAudio = true; in GetDeviceCapabilities()
1016 state->m_hasDVBT = true; in GetDeviceCapabilities()
1017 state->m_hasDVBC = false; in GetDeviceCapabilities()
1018 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1019 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1020 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1021 state->m_hasIRQN = false; in GetDeviceCapabilities()
1025 state->m_hasLNA = false; in GetDeviceCapabilities()
1026 state->m_hasOOB = false; in GetDeviceCapabilities()
1027 state->m_hasATV = true; in GetDeviceCapabilities()
1028 state->m_hasAudio = true; in GetDeviceCapabilities()
1029 state->m_hasDVBT = true; in GetDeviceCapabilities()
1030 state->m_hasDVBC = true; in GetDeviceCapabilities()
1031 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1032 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1033 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1034 state->m_hasIRQN = false; in GetDeviceCapabilities()
1038 state->m_hasLNA = false; in GetDeviceCapabilities()
1039 state->m_hasOOB = false; in GetDeviceCapabilities()
1040 state->m_hasATV = true; in GetDeviceCapabilities()
1041 state->m_hasAudio = true; in GetDeviceCapabilities()
1042 state->m_hasDVBT = true; in GetDeviceCapabilities()
1043 state->m_hasDVBC = true; in GetDeviceCapabilities()
1044 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1045 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1046 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1047 state->m_hasIRQN = false; in GetDeviceCapabilities()
1051 state->m_hasLNA = false; in GetDeviceCapabilities()
1052 state->m_hasOOB = false; in GetDeviceCapabilities()
1053 state->m_hasATV = true; in GetDeviceCapabilities()
1054 state->m_hasAudio = true; in GetDeviceCapabilities()
1055 state->m_hasDVBT = true; in GetDeviceCapabilities()
1056 state->m_hasDVBC = true; in GetDeviceCapabilities()
1057 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1058 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1059 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1060 state->m_hasIRQN = false; in GetDeviceCapabilities()
1064 state->m_hasLNA = false; in GetDeviceCapabilities()
1065 state->m_hasOOB = false; in GetDeviceCapabilities()
1066 state->m_hasATV = true; in GetDeviceCapabilities()
1067 state->m_hasAudio = false; in GetDeviceCapabilities()
1068 state->m_hasDVBT = true; in GetDeviceCapabilities()
1069 state->m_hasDVBC = true; in GetDeviceCapabilities()
1070 state->m_hasSAWSW = true; in GetDeviceCapabilities()
1071 state->m_hasGPIO2 = true; in GetDeviceCapabilities()
1072 state->m_hasGPIO1 = true; in GetDeviceCapabilities()
1073 state->m_hasIRQN = false; in GetDeviceCapabilities()
1085 state->m_oscClockFreq / 1000, in GetDeviceCapabilities()
1086 state->m_oscClockFreq % 1000); in GetDeviceCapabilities()
1096 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) in HI_Command() argument
1104 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd); in HI_Command()
1112 ((state->m_HICfgCtrl) & in HI_Command()
1123 status = read16(state, SIO_HI_RA_RAM_CMD__A, in HI_Command()
1129 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult); in HI_Command()
1138 static int HI_CfgCommand(struct drxk_state *state) in HI_CfgCommand() argument
1144 mutex_lock(&state->mutex); in HI_CfgCommand()
1146 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout); in HI_CfgCommand()
1149 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl); in HI_CfgCommand()
1152 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey); in HI_CfgCommand()
1155 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay); in HI_CfgCommand()
1158 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv); in HI_CfgCommand()
1161 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); in HI_CfgCommand()
1164 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0); in HI_CfgCommand()
1168 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in HI_CfgCommand()
1170 mutex_unlock(&state->mutex); in HI_CfgCommand()
1176 static int InitHI(struct drxk_state *state) in InitHI() argument
1180 state->m_HICfgWakeUpKey = (state->demod_address << 1); in InitHI()
1181 state->m_HICfgTimeout = 0x96FF; in InitHI()
1183 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in InitHI()
1185 return HI_CfgCommand(state); in InitHI()
1188 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) in MPEGTSConfigurePins() argument
1197 state->m_enableParallel ? "parallel" : "serial"); in MPEGTSConfigurePins()
1200 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in MPEGTSConfigurePins()
1205 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in MPEGTSConfigurePins()
1211 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); in MPEGTSConfigurePins()
1214 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); in MPEGTSConfigurePins()
1217 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000); in MPEGTSConfigurePins()
1220 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); in MPEGTSConfigurePins()
1223 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000); in MPEGTSConfigurePins()
1226 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); in MPEGTSConfigurePins()
1229 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); in MPEGTSConfigurePins()
1232 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); in MPEGTSConfigurePins()
1235 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); in MPEGTSConfigurePins()
1238 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); in MPEGTSConfigurePins()
1241 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); in MPEGTSConfigurePins()
1244 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); in MPEGTSConfigurePins()
1250 ((state->m_TSDataStrength << in MPEGTSConfigurePins()
1252 sioPdrMclkCfg = ((state->m_TSClockkStrength << in MPEGTSConfigurePins()
1256 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1260 if (state->enable_merr_cfg) in MPEGTSConfigurePins()
1263 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); in MPEGTSConfigurePins()
1266 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg); in MPEGTSConfigurePins()
1270 if (state->m_enableParallel == true) { in MPEGTSConfigurePins()
1272 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1275 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1278 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1281 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1284 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1287 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1290 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1294 sioPdrMdxCfg = ((state->m_TSDataStrength << in MPEGTSConfigurePins()
1298 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000); in MPEGTSConfigurePins()
1301 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000); in MPEGTSConfigurePins()
1304 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000); in MPEGTSConfigurePins()
1307 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000); in MPEGTSConfigurePins()
1310 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000); in MPEGTSConfigurePins()
1313 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000); in MPEGTSConfigurePins()
1316 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000); in MPEGTSConfigurePins()
1320 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg); in MPEGTSConfigurePins()
1323 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg); in MPEGTSConfigurePins()
1328 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000); in MPEGTSConfigurePins()
1332 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in MPEGTSConfigurePins()
1339 static int MPEGTSDisable(struct drxk_state *state) in MPEGTSDisable() argument
1343 return MPEGTSConfigurePins(state, false); in MPEGTSDisable()
1346 static int BLChainCmd(struct drxk_state *state, in BLChainCmd() argument
1354 mutex_lock(&state->mutex); in BLChainCmd()
1355 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); in BLChainCmd()
1358 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset); in BLChainCmd()
1361 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements); in BLChainCmd()
1364 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); in BLChainCmd()
1371 status = read16(state, SIO_BL_STATUS__A, &blStatus); in BLChainCmd()
1386 mutex_unlock(&state->mutex); in BLChainCmd()
1391 static int DownloadMicrocode(struct drxk_state *state, in DownloadMicrocode() argument
1444 status = write_block(state, Address, BlockSize, pSrc); in DownloadMicrocode()
1455 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) in DVBTEnableOFDMTokenRing() argument
1470 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); in DVBTEnableOFDMTokenRing()
1476 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); in DVBTEnableOFDMTokenRing()
1480 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); in DVBTEnableOFDMTokenRing()
1492 static int MPEGTSStop(struct drxk_state *state) in MPEGTSStop() argument
1501 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); in MPEGTSStop()
1505 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); in MPEGTSStop()
1510 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode); in MPEGTSStop()
1514 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode); in MPEGTSStop()
1523 static int scu_command(struct drxk_state *state, in scu_command() argument
1546 mutex_lock(&state->mutex); in scu_command()
1557 write_block(state, SCU_RAM_PARAM_0__A - in scu_command()
1563 status = read16(state, SCU_RAM_COMMAND__A, &curCmd); in scu_command()
1578 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]); in scu_command()
1616 mutex_unlock(&state->mutex); in scu_command()
1620 static int SetIqmAf(struct drxk_state *state, bool active) in SetIqmAf() argument
1628 status = read16(state, IQM_AF_STDBY__A, &data); in SetIqmAf()
1646 status = write16(state, IQM_AF_STDBY__A, data); in SetIqmAf()
1654 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode) in CtrlPowerMode() argument
1687 if (state->m_currentPowerMode == *mode) in CtrlPowerMode()
1691 if (state->m_currentPowerMode != DRX_POWER_UP) { in CtrlPowerMode()
1692 status = PowerUpDevice(state); in CtrlPowerMode()
1695 status = DVBTEnableOFDMTokenRing(state, true); in CtrlPowerMode()
1712 switch (state->m_OperationMode) { in CtrlPowerMode()
1714 status = MPEGTSStop(state); in CtrlPowerMode()
1717 status = PowerDownDVBT(state, false); in CtrlPowerMode()
1723 status = MPEGTSStop(state); in CtrlPowerMode()
1726 status = PowerDownQAM(state); in CtrlPowerMode()
1733 status = DVBTEnableOFDMTokenRing(state, false); in CtrlPowerMode()
1736 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode); in CtrlPowerMode()
1739 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in CtrlPowerMode()
1744 state->m_HICfgCtrl |= in CtrlPowerMode()
1746 status = HI_CfgCommand(state); in CtrlPowerMode()
1751 state->m_currentPowerMode = *mode; in CtrlPowerMode()
1760 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) in PowerDownDVBT() argument
1769 status = read16(state, SCU_COMM_EXEC__A, &data); in PowerDownDVBT()
1774 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NUL… in PowerDownDVBT()
1778 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NU… in PowerDownDVBT()
1784 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in PowerDownDVBT()
1787 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in PowerDownDVBT()
1790 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in PowerDownDVBT()
1795 status = SetIqmAf(state, false); in PowerDownDVBT()
1801 status = CtrlPowerMode(state, &powerMode); in PowerDownDVBT()
1811 static int SetOperationMode(struct drxk_state *state, in SetOperationMode() argument
1824 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in SetOperationMode()
1829 if (state->m_OperationMode == oMode) in SetOperationMode()
1832 switch (state->m_OperationMode) { in SetOperationMode()
1837 status = MPEGTSStop(state); in SetOperationMode()
1840 status = PowerDownDVBT(state, true); in SetOperationMode()
1843 state->m_OperationMode = OM_NONE; in SetOperationMode()
1847 status = MPEGTSStop(state); in SetOperationMode()
1850 status = PowerDownQAM(state); in SetOperationMode()
1853 state->m_OperationMode = OM_NONE; in SetOperationMode()
1867 state->m_OperationMode = oMode; in SetOperationMode()
1868 status = SetDVBTStandard(state, oMode); in SetOperationMode()
1875 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C'); in SetOperationMode()
1876 state->m_OperationMode = oMode; in SetOperationMode()
1877 status = SetQAMStandard(state, oMode); in SetOperationMode()
1891 static int Start(struct drxk_state *state, s32 offsetFreq, in Start() argument
1900 if (state->m_DrxkState != DRXK_STOPPED && in Start()
1901 state->m_DrxkState != DRXK_DTV_STARTED) in Start()
1904 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON); in Start()
1907 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; in Start()
1911 switch (state->m_OperationMode) { in Start()
1915 status = SetQAM(state, IFreqkHz, OffsetkHz); in Start()
1918 state->m_DrxkState = DRXK_DTV_STARTED; in Start()
1922 status = MPEGTSStop(state); in Start()
1925 status = SetDVBT(state, IFreqkHz, OffsetkHz); in Start()
1928 status = DVBTStart(state); in Start()
1931 state->m_DrxkState = DRXK_DTV_STARTED; in Start()
1942 static int ShutDown(struct drxk_state *state) in ShutDown() argument
1946 MPEGTSStop(state); in ShutDown()
1950 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus) in GetLockStatus() argument
1962 switch (state->m_OperationMode) { in GetLockStatus()
1966 status = GetQAMLockStatus(state, pLockStatus); in GetLockStatus()
1969 status = GetDVBTLockStatus(state, pLockStatus); in GetLockStatus()
1980 static int MPEGTSStart(struct drxk_state *state) in MPEGTSStart() argument
1987 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); in MPEGTSStart()
1991 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); in MPEGTSStart()
1994 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); in MPEGTSStart()
2001 static int MPEGTSDtoInit(struct drxk_state *state) in MPEGTSDtoInit() argument
2008 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000); in MPEGTSDtoInit()
2011 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C); in MPEGTSDtoInit()
2014 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A); in MPEGTSDtoInit()
2017 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008); in MPEGTSDtoInit()
2020 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006); in MPEGTSDtoInit()
2023 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680); in MPEGTSDtoInit()
2026 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080); in MPEGTSDtoInit()
2029 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4); in MPEGTSDtoInit()
2034 status = write16(state, FEC_OC_OCR_INVERT__A, 0); in MPEGTSDtoInit()
2037 status = write16(state, FEC_OC_SNC_LWM__A, 2); in MPEGTSDtoInit()
2040 status = write16(state, FEC_OC_SNC_HWM__A, 12); in MPEGTSDtoInit()
2048 static int MPEGTSDtoSetup(struct drxk_state *state, in MPEGTSDtoSetup() argument
2068 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode); in MPEGTSDtoSetup()
2071 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); in MPEGTSDtoSetup()
2076 if (state->m_insertRSByte == true) { in MPEGTSDtoSetup()
2087 if (state->m_enableParallel == false) { in MPEGTSDtoSetup()
2094 maxBitRate = state->m_DVBTBitrate; in MPEGTSDtoSetup()
2097 staticCLK = state->m_DVBTStaticCLK; in MPEGTSDtoSetup()
2103 maxBitRate = state->m_DVBCBitrate; in MPEGTSDtoSetup()
2104 staticCLK = state->m_DVBCStaticCLK; in MPEGTSDtoSetup()
2136 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) in MPEGTSDtoSetup()
2151 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen); in MPEGTSDtoSetup()
2154 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); in MPEGTSDtoSetup()
2157 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode); in MPEGTSDtoSetup()
2160 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode); in MPEGTSDtoSetup()
2163 status = write16(state, FEC_OC_MODE__A, fecOcRegMode); in MPEGTSDtoSetup()
2166 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode); in MPEGTSDtoSetup()
2171 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate); in MPEGTSDtoSetup()
2174 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate); in MPEGTSDtoSetup()
2177 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode); in MPEGTSDtoSetup()
2184 static int MPEGTSConfigurePolarity(struct drxk_state *state) in MPEGTSConfigurePolarity() argument
2199 if (state->m_invertDATA == true) in MPEGTSConfigurePolarity()
2202 if (state->m_invertERR == true) in MPEGTSConfigurePolarity()
2205 if (state->m_invertSTR == true) in MPEGTSConfigurePolarity()
2208 if (state->m_invertVAL == true) in MPEGTSConfigurePolarity()
2211 if (state->m_invertCLK == true) in MPEGTSConfigurePolarity()
2214 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); in MPEGTSConfigurePolarity()
2219 static int SetAgcRf(struct drxk_state *state, in SetAgcRf() argument
2234 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcRf()
2238 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcRf()
2241 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcRf()
2249 if (state->m_RfAgcPol) in SetAgcRf()
2253 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcRf()
2258 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); in SetAgcRf()
2267 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); in SetAgcRf()
2271 if (IsDVBT(state)) in SetAgcRf()
2272 pIfAgcSettings = &state->m_dvbtIfAgcCfg; in SetAgcRf()
2273 else if (IsQAM(state)) in SetAgcRf()
2274 pIfAgcSettings = &state->m_qamIfAgcCfg; in SetAgcRf()
2276 pIfAgcSettings = &state->m_atvIfAgcCfg; in SetAgcRf()
2284 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top); in SetAgcRf()
2289 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent); in SetAgcRf()
2294 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel); in SetAgcRf()
2302 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcRf()
2306 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcRf()
2311 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcRf()
2315 if (state->m_RfAgcPol) in SetAgcRf()
2319 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcRf()
2324 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0); in SetAgcRf()
2329 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel); in SetAgcRf()
2336 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcRf()
2340 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcRf()
2345 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcRf()
2349 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcRf()
2366 static int SetAgcIf(struct drxk_state *state, in SetAgcIf() argument
2379 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcIf()
2383 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcIf()
2387 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcIf()
2395 if (state->m_IfAgcPol) in SetAgcIf()
2399 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcIf()
2404 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data); in SetAgcIf()
2412 status = write16(state, SCU_RAM_AGC_KI_RED__A, data); in SetAgcIf()
2416 if (IsQAM(state)) in SetAgcIf()
2417 pRfAgcSettings = &state->m_qamRfAgcCfg; in SetAgcIf()
2419 pRfAgcSettings = &state->m_atvRfAgcCfg; in SetAgcIf()
2423 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top); in SetAgcIf()
2431 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcIf()
2435 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcIf()
2439 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcIf()
2447 if (state->m_IfAgcPol) in SetAgcIf()
2451 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcIf()
2456 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel); in SetAgcIf()
2464 status = read16(state, IQM_AF_STDBY__A, &data); in SetAgcIf()
2468 status = write16(state, IQM_AF_STDBY__A, data); in SetAgcIf()
2473 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data); in SetAgcIf()
2477 status = write16(state, SCU_RAM_AGC_CONFIG__A, data); in SetAgcIf()
2485 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top); in SetAgcIf()
2492 static int GetQAMSignalToNoise(struct drxk_state *state, in GetQAMSignalToNoise() argument
2507 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower); in GetQAMSignalToNoise()
2513 switch (state->props.modulation) { in GetQAMSignalToNoise()
2541 static int GetDVBTSignalToNoise(struct drxk_state *state, in GetDVBTSignalToNoise() argument
2561 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); in GetDVBTSignalToNoise()
2564 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt); in GetDVBTSignalToNoise()
2567 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp); in GetDVBTSignalToNoise()
2570 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data); in GetDVBTSignalToNoise()
2579 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data); in GetDVBTSignalToNoise()
2588 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams); in GetDVBTSignalToNoise()
2640 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) in GetSignalToNoise() argument
2645 switch (state->m_OperationMode) { in GetSignalToNoise()
2647 return GetDVBTSignalToNoise(state, pSignalToNoise); in GetSignalToNoise()
2650 return GetQAMSignalToNoise(state, pSignalToNoise); in GetSignalToNoise()
2658 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2692 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2695 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2700 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2723 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2735 status = GetQAMSignalToNoise(state, &SignalToNoise);
2739 switch (state->props.modulation) {
2770 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2774 switch (state->m_OperationMode) {
2776 return GetDVBTQuality(state, pQuality);
2778 return GetDVBCQuality(state, pQuality);
2800 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) in ConfigureI2CBridge() argument
2806 if (state->m_DrxkState == DRXK_UNINITIALIZED) in ConfigureI2CBridge()
2808 if (state->m_DrxkState == DRXK_POWERED_DOWN) in ConfigureI2CBridge()
2811 if (state->no_i2c_bridge) in ConfigureI2CBridge()
2814 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); in ConfigureI2CBridge()
2818 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); in ConfigureI2CBridge()
2822 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); in ConfigureI2CBridge()
2827 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0); in ConfigureI2CBridge()
2835 static int SetPreSaw(struct drxk_state *state, in SetPreSaw() argument
2846 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference); in SetPreSaw()
2853 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, in BLDirectCmd() argument
2864 mutex_lock(&state->mutex); in BLDirectCmd()
2865 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT); in BLDirectCmd()
2868 status = write16(state, SIO_BL_TGT_HDR__A, blockbank); in BLDirectCmd()
2871 status = write16(state, SIO_BL_TGT_ADDR__A, offset); in BLDirectCmd()
2874 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset); in BLDirectCmd()
2877 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements); in BLDirectCmd()
2880 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); in BLDirectCmd()
2886 status = read16(state, SIO_BL_STATUS__A, &blStatus); in BLDirectCmd()
2899 mutex_unlock(&state->mutex); in BLDirectCmd()
2904 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) in ADCSyncMeasurement() argument
2912 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); in ADCSyncMeasurement()
2915 status = write16(state, IQM_AF_START_LOCK__A, 1); in ADCSyncMeasurement()
2920 status = read16(state, IQM_AF_PHASE0__A, &data); in ADCSyncMeasurement()
2925 status = read16(state, IQM_AF_PHASE1__A, &data); in ADCSyncMeasurement()
2930 status = read16(state, IQM_AF_PHASE2__A, &data); in ADCSyncMeasurement()
2942 static int ADCSynchronization(struct drxk_state *state) in ADCSynchronization() argument
2949 status = ADCSyncMeasurement(state, &count); in ADCSynchronization()
2957 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg); in ADCSynchronization()
2970 status = write16(state, IQM_AF_CLKNEG__A, clkNeg); in ADCSynchronization()
2973 status = ADCSyncMeasurement(state, &count); in ADCSynchronization()
2986 static int SetFrequencyShifter(struct drxk_state *state, in SetFrequencyShifter() argument
2993 bool tunerMirror = !state->m_bMirrorFreqSpect; in SetFrequencyShifter()
2998 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3); in SetFrequencyShifter()
3009 if ((state->m_OperationMode == OM_QAM_ITU_A) || in SetFrequencyShifter()
3010 (state->m_OperationMode == OM_QAM_ITU_C) || in SetFrequencyShifter()
3011 (state->m_OperationMode == OM_DVBT)) in SetFrequencyShifter()
3035 imageToSelect = state->m_rfmirror ^ tunerMirror ^ in SetFrequencyShifter()
3037 state->m_IqmFsRateOfs = in SetFrequencyShifter()
3041 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; in SetFrequencyShifter()
3045 status = write32(state, IQM_FS_RATE_OFS_LO__A, in SetFrequencyShifter()
3046 state->m_IqmFsRateOfs); in SetFrequencyShifter()
3052 static int InitAGC(struct drxk_state *state, bool isDTV) in InitAGC() argument
3082 if (!IsQAM(state)) { in InitAGC()
3083 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode); in InitAGC()
3101 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay; in InitAGC()
3103 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay); in InitAGC()
3107 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); in InitAGC()
3110 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt); in InitAGC()
3113 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin); in InitAGC()
3116 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax); in InitAGC()
3119 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); in InitAGC()
3122 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax); in InitAGC()
3125 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); in InitAGC()
3128 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0); in InitAGC()
3131 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0); in InitAGC()
3134 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); in InitAGC()
3137 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); in InitAGC()
3140 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); in InitAGC()
3144 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); in InitAGC()
3147 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt); in InitAGC()
3150 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen); in InitAGC()
3154 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023); in InitAGC()
3157 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); in InitAGC()
3160 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50); in InitAGC()
3164 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); in InitAGC()
3167 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin); in InitAGC()
3170 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin); in InitAGC()
3173 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); in InitAGC()
3176 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); in InitAGC()
3179 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); in InitAGC()
3182 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0); in InitAGC()
3185 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117); in InitAGC()
3188 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657); in InitAGC()
3191 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0); in InitAGC()
3194 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0); in InitAGC()
3197 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0); in InitAGC()
3200 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1); in InitAGC()
3203 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0); in InitAGC()
3206 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0); in InitAGC()
3209 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0); in InitAGC()
3212 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1); in InitAGC()
3215 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500); in InitAGC()
3218 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500); in InitAGC()
3223 status = read16(state, SCU_RAM_AGC_KI__A, &data); in InitAGC()
3233 status = write16(state, SCU_RAM_AGC_KI__A, data); in InitAGC()
3240 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr) in DVBTQAMGetAccPktErr() argument
3246 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); in DVBTQAMGetAccPktErr()
3248 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr); in DVBTQAMGetAccPktErr()
3254 static int DVBTScCommand(struct drxk_state *state, in DVBTScCommand() argument
3266 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec); in DVBTScCommand()
3278 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); in DVBTScCommand()
3290 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd); in DVBTScCommand()
3308 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1); in DVBTScCommand()
3312 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0); in DVBTScCommand()
3317 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd); in DVBTScCommand()
3330 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); in DVBTScCommand()
3337 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); in DVBTScCommand()
3354 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); in DVBTScCommand()
3374 static int PowerUpDVBT(struct drxk_state *state) in PowerUpDVBT() argument
3380 status = CtrlPowerMode(state, &powerMode); in PowerUpDVBT()
3386 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled) in DVBTCtrlSetIncEnable() argument
3392 status = write16(state, IQM_CF_BYPASSDET__A, 0); in DVBTCtrlSetIncEnable()
3394 status = write16(state, IQM_CF_BYPASSDET__A, 1); in DVBTCtrlSetIncEnable()
3401 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled) in DVBTCtrlSetFrEnable() argument
3409 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, in DVBTCtrlSetFrEnable()
3413 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); in DVBTCtrlSetFrEnable()
3421 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state, in DVBTCtrlSetEchoThreshold() argument
3428 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data); in DVBTCtrlSetEchoThreshold()
3449 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); in DVBTCtrlSetEchoThreshold()
3456 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, in DVBTCtrlSetSqiSpeed() argument
3471 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A, in DVBTCtrlSetSqiSpeed()
3489 static int DVBTActivatePresets(struct drxk_state *state) in DVBTActivatePresets() argument
3499 status = DVBTCtrlSetIncEnable(state, &setincenable); in DVBTActivatePresets()
3502 status = DVBTCtrlSetFrEnable(state, &setfrenable); in DVBTActivatePresets()
3505 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k); in DVBTActivatePresets()
3508 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k); in DVBTActivatePresets()
3511 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax); in DVBTActivatePresets()
3528 static int SetDVBTStandard(struct drxk_state *state, in SetDVBTStandard() argument
3537 PowerUpDVBT(state); in SetDVBTStandard()
3539 SwitchAntennaToDVBT(state); in SetDVBTStandard()
3541 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NU… in SetDVBTStandard()
3546 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, … in SetDVBTStandard()
3551 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in SetDVBTStandard()
3554 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in SetDVBTStandard()
3557 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in SetDVBTStandard()
3563 status = write16(state, IQM_AF_UPD_SEL__A, 1); in SetDVBTStandard()
3567 status = write16(state, IQM_AF_CLP_LEN__A, 0); in SetDVBTStandard()
3571 status = write16(state, IQM_AF_SNS_LEN__A, 0); in SetDVBTStandard()
3575 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); in SetDVBTStandard()
3578 status = SetIqmAf(state, true); in SetDVBTStandard()
3582 status = write16(state, IQM_AF_AGC_RF__A, 0); in SetDVBTStandard()
3587 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */ in SetDVBTStandard()
3590 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */ in SetDVBTStandard()
3593 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */ in SetDVBTStandard()
3597 status = write16(state, IQM_RC_STRETCH__A, 16); in SetDVBTStandard()
3600 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ in SetDVBTStandard()
3603 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ in SetDVBTStandard()
3606 status = write16(state, IQM_CF_SCALE__A, 1600); in SetDVBTStandard()
3609 status = write16(state, IQM_CF_SCALE_SH__A, 0); in SetDVBTStandard()
3614 status = write16(state, IQM_AF_CLP_TH__A, 448); in SetDVBTStandard()
3617 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */ in SetDVBTStandard()
3621 …status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIME… in SetDVBTStandard()
3625 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */ in SetDVBTStandard()
3628 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2); in SetDVBTStandard()
3632 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1); in SetDVBTStandard()
3635 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); in SetDVBTStandard()
3640 status = ADCSynchronization(state); in SetDVBTStandard()
3643 status = SetPreSaw(state, &state->m_dvbtPreSawCfg); in SetDVBTStandard()
3648 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in SetDVBTStandard()
3652 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true); in SetDVBTStandard()
3655 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true); in SetDVBTStandard()
3660 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data); in SetDVBTStandard()
3664 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data); in SetDVBTStandard()
3669 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in SetDVBTStandard()
3673 if (!state->m_DRXK_A3_ROM_CODE) { in SetDVBTStandard()
3675 …status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDela… in SetDVBTStandard()
3682 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1); in SetDVBTStandard()
3685 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2); in SetDVBTStandard()
3691 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */ in SetDVBTStandard()
3697 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400); in SetDVBTStandard()
3701 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000); in SetDVBTStandard()
3705 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001); in SetDVBTStandard()
3710 status = MPEGTSDtoSetup(state, OM_DVBT); in SetDVBTStandard()
3714 status = DVBTActivatePresets(state); in SetDVBTStandard()
3730 static int DVBTStart(struct drxk_state *state) in DVBTStart() argument
3740 …status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK_… in DVBTStart()
3744 status = MPEGTSStart(state); in DVBTStart()
3747 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); in DVBTStart()
3765 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, in SetDVBT() argument
3778 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NUL… in SetDVBT()
3783 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in SetDVBT()
3788 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP); in SetDVBT()
3791 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP); in SetDVBT()
3797 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP); in SetDVBT()
3804 switch (state->props.transmission_mode) { in SetDVBT()
3818 switch (state->props.guard_interval) { in SetDVBT()
3838 switch (state->props.hierarchy) { in SetDVBT()
3859 switch (state->props.modulation) { in SetDVBT()
3896 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); in SetDVBT()
3902 switch (state->props.code_rate_HP) { in SetDVBT()
3931 switch (state->props.bandwidth_hz) { in SetDVBT()
3933 state->props.bandwidth_hz = 8000000; in SetDVBT()
3937 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); in SetDVBT()
3941 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7); in SetDVBT()
3944 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7); in SetDVBT()
3947 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7); in SetDVBT()
3950 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); in SetDVBT()
3956 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); in SetDVBT()
3960 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8); in SetDVBT()
3963 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8); in SetDVBT()
3966 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4); in SetDVBT()
3969 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); in SetDVBT()
3975 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); in SetDVBT()
3979 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19); in SetDVBT()
3982 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19); in SetDVBT()
3985 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14); in SetDVBT()
3988 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); in SetDVBT()
4008 ((state->m_sysClockFreq * in SetDVBT()
4021 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs); in SetDVBT()
4032 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); in SetDVBT()
4039 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in SetDVBT()
4044 status = write16(state, OFDM_SC_COMM_STATE__A, 0); in SetDVBT()
4047 status = write16(state, OFDM_SC_COMM_EXEC__A, 1); in SetDVBT()
4052 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NU… in SetDVBT()
4062 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, in SetDVBT()
4067 if (!state->m_DRXK_A3_ROM_CODE) in SetDVBT()
4068 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed); in SetDVBT()
4086 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) in GetDVBTLockStatus() argument
4102 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); in GetDVBTLockStatus()
4108 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); in GetDVBTLockStatus()
4127 static int PowerUpQAM(struct drxk_state *state) in PowerUpQAM() argument
4133 status = CtrlPowerMode(state, &powerMode); in PowerUpQAM()
4142 static int PowerDownQAM(struct drxk_state *state) in PowerDownQAM() argument
4149 status = read16(state, SCU_COMM_EXEC__A, &data); in PowerDownQAM()
4158 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); in PowerDownQAM()
4161 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL… in PowerDownQAM()
4166 status = SetIqmAf(state, false); in PowerDownQAM()
4188 static int SetQAMMeasurement(struct drxk_state *state, in SetQAMMeasurement() argument
4249 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod); in SetQAMMeasurement()
4252 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); in SetQAMMeasurement()
4255 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod); in SetQAMMeasurement()
4262 static int SetQAM16(struct drxk_state *state) in SetQAM16() argument
4269 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517); in SetQAM16()
4272 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517); in SetQAM16()
4275 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517); in SetQAM16()
4278 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517); in SetQAM16()
4281 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517); in SetQAM16()
4284 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517); in SetQAM16()
4288 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2); in SetQAM16()
4291 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2); in SetQAM16()
4294 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2); in SetQAM16()
4297 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2); in SetQAM16()
4300 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2); in SetQAM16()
4303 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM16()
4307 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in SetQAM16()
4310 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in SetQAM16()
4313 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM16()
4318 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16); in SetQAM16()
4323 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM16()
4326 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM16()
4329 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM16()
4332 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM16()
4335 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM16()
4338 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM16()
4341 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM16()
4344 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM16()
4348 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM16()
4351 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); in SetQAM16()
4354 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); in SetQAM16()
4357 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM16()
4360 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); in SetQAM16()
4363 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in SetQAM16()
4366 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM16()
4369 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); in SetQAM16()
4372 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32); in SetQAM16()
4375 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM16()
4378 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM16()
4381 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in SetQAM16()
4388 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140); in SetQAM16()
4391 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); in SetQAM16()
4394 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95); in SetQAM16()
4397 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120); in SetQAM16()
4400 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230); in SetQAM16()
4403 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105); in SetQAM16()
4407 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM16()
4410 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in SetQAM16()
4413 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24); in SetQAM16()
4420 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16); in SetQAM16()
4423 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220); in SetQAM16()
4426 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25); in SetQAM16()
4429 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6); in SetQAM16()
4432 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); in SetQAM16()
4435 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); in SetQAM16()
4438 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); in SetQAM16()
4455 static int SetQAM32(struct drxk_state *state) in SetQAM32() argument
4463 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707); in SetQAM32()
4466 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707); in SetQAM32()
4469 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707); in SetQAM32()
4472 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707); in SetQAM32()
4475 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707); in SetQAM32()
4478 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707); in SetQAM32()
4483 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3); in SetQAM32()
4486 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3); in SetQAM32()
4489 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3); in SetQAM32()
4492 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3); in SetQAM32()
4495 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); in SetQAM32()
4498 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM32()
4502 status = write16(state, QAM_SY_SYNC_HWM__A, 6); in SetQAM32()
4505 status = write16(state, QAM_SY_SYNC_AWM__A, 5); in SetQAM32()
4508 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM32()
4514 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32); in SetQAM32()
4521 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM32()
4524 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM32()
4527 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM32()
4530 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM32()
4533 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM32()
4536 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM32()
4539 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM32()
4542 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM32()
4546 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM32()
4549 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20); in SetQAM32()
4552 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80); in SetQAM32()
4555 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM32()
4558 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20); in SetQAM32()
4561 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in SetQAM32()
4564 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM32()
4567 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16); in SetQAM32()
4570 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16); in SetQAM32()
4573 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM32()
4576 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM32()
4579 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); in SetQAM32()
4586 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90); in SetQAM32()
4589 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50); in SetQAM32()
4592 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in SetQAM32()
4595 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in SetQAM32()
4598 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170); in SetQAM32()
4601 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); in SetQAM32()
4605 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM32()
4608 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in SetQAM32()
4611 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10); in SetQAM32()
4618 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); in SetQAM32()
4621 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140); in SetQAM32()
4624 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); in SetQAM32()
4627 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); in SetQAM32()
4630 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); in SetQAM32()
4633 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); in SetQAM32()
4636 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); in SetQAM32()
4650 static int SetQAM64(struct drxk_state *state) in SetQAM64() argument
4657 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336); in SetQAM64()
4660 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618); in SetQAM64()
4663 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988); in SetQAM64()
4666 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809); in SetQAM64()
4669 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809); in SetQAM64()
4672 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609); in SetQAM64()
4677 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4); in SetQAM64()
4680 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4); in SetQAM64()
4683 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4); in SetQAM64()
4686 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4); in SetQAM64()
4689 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3); in SetQAM64()
4692 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM64()
4696 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in SetQAM64()
4699 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in SetQAM64()
4702 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM64()
4707 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64); in SetQAM64()
4714 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM64()
4717 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM64()
4720 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM64()
4723 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM64()
4726 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM64()
4729 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM64()
4732 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM64()
4735 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM64()
4739 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM64()
4742 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30); in SetQAM64()
4745 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100); in SetQAM64()
4748 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM64()
4751 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30); in SetQAM64()
4754 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50); in SetQAM64()
4757 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM64()
4760 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in SetQAM64()
4763 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); in SetQAM64()
4766 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM64()
4769 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM64()
4772 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in SetQAM64()
4779 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100); in SetQAM64()
4782 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in SetQAM64()
4785 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in SetQAM64()
4788 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110); in SetQAM64()
4791 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200); in SetQAM64()
4794 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95); in SetQAM64()
4798 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM64()
4801 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in SetQAM64()
4804 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15); in SetQAM64()
4811 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12); in SetQAM64()
4814 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141); in SetQAM64()
4817 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7); in SetQAM64()
4820 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0); in SetQAM64()
4823 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); in SetQAM64()
4826 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); in SetQAM64()
4829 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); in SetQAM64()
4844 static int SetQAM128(struct drxk_state *state) in SetQAM128() argument
4851 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564); in SetQAM128()
4854 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598); in SetQAM128()
4857 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394); in SetQAM128()
4860 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409); in SetQAM128()
4863 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656); in SetQAM128()
4866 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238); in SetQAM128()
4871 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6); in SetQAM128()
4874 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6); in SetQAM128()
4877 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6); in SetQAM128()
4880 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6); in SetQAM128()
4883 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5); in SetQAM128()
4886 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM128()
4890 status = write16(state, QAM_SY_SYNC_HWM__A, 6); in SetQAM128()
4893 status = write16(state, QAM_SY_SYNC_AWM__A, 5); in SetQAM128()
4896 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM128()
4903 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128); in SetQAM128()
4910 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM128()
4913 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM128()
4916 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM128()
4919 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM128()
4922 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM128()
4925 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM128()
4928 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM128()
4931 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM128()
4935 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM128()
4938 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40); in SetQAM128()
4941 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120); in SetQAM128()
4944 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM128()
4947 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40); in SetQAM128()
4950 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60); in SetQAM128()
4953 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM128()
4956 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in SetQAM128()
4959 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64); in SetQAM128()
4962 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM128()
4965 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM128()
4968 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0); in SetQAM128()
4975 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); in SetQAM128()
4978 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in SetQAM128()
4981 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in SetQAM128()
4984 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in SetQAM128()
4987 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140); in SetQAM128()
4990 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100); in SetQAM128()
4994 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM128()
4997 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5); in SetQAM128()
5001 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); in SetQAM128()
5007 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); in SetQAM128()
5010 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65); in SetQAM128()
5013 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5); in SetQAM128()
5016 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3); in SetQAM128()
5019 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); in SetQAM128()
5022 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); in SetQAM128()
5025 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); in SetQAM128()
5040 static int SetQAM256(struct drxk_state *state) in SetQAM256() argument
5047 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502); in SetQAM256()
5050 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084); in SetQAM256()
5053 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543); in SetQAM256()
5056 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931); in SetQAM256()
5059 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629); in SetQAM256()
5062 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385); in SetQAM256()
5067 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8); in SetQAM256()
5070 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8); in SetQAM256()
5073 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8); in SetQAM256()
5076 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8); in SetQAM256()
5079 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6); in SetQAM256()
5082 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0); in SetQAM256()
5086 status = write16(state, QAM_SY_SYNC_HWM__A, 5); in SetQAM256()
5089 status = write16(state, QAM_SY_SYNC_AWM__A, 4); in SetQAM256()
5092 status = write16(state, QAM_SY_SYNC_LWM__A, 3); in SetQAM256()
5098 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256); in SetQAM256()
5105 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15); in SetQAM256()
5108 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40); in SetQAM256()
5111 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12); in SetQAM256()
5114 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24); in SetQAM256()
5117 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24); in SetQAM256()
5120 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12); in SetQAM256()
5123 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16); in SetQAM256()
5126 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16); in SetQAM256()
5130 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5); in SetQAM256()
5133 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50); in SetQAM256()
5136 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250); in SetQAM256()
5139 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5); in SetQAM256()
5142 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50); in SetQAM256()
5145 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125); in SetQAM256()
5148 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16); in SetQAM256()
5151 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25); in SetQAM256()
5154 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48); in SetQAM256()
5157 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5); in SetQAM256()
5160 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10); in SetQAM256()
5163 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10); in SetQAM256()
5170 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50); in SetQAM256()
5173 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60); in SetQAM256()
5176 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80); in SetQAM256()
5179 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100); in SetQAM256()
5182 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150); in SetQAM256()
5185 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110); in SetQAM256()
5189 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40); in SetQAM256()
5192 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4); in SetQAM256()
5195 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12); in SetQAM256()
5202 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8); in SetQAM256()
5205 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74); in SetQAM256()
5208 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18); in SetQAM256()
5211 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13); in SetQAM256()
5214 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7); in SetQAM256()
5217 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0); in SetQAM256()
5220 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); in SetQAM256()
5235 static int QAMResetQAM(struct drxk_state *state) in QAMResetQAM() argument
5242 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); in QAMResetQAM()
5246 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NUL… in QAMResetQAM()
5261 static int QAMSetSymbolrate(struct drxk_state *state) in QAMSetSymbolrate() argument
5272 adcFrequency = (state->m_sysClockFreq * 1000) / 3; in QAMSetSymbolrate()
5275 if (state->props.symbol_rate <= 1188750) in QAMSetSymbolrate()
5277 else if (state->props.symbol_rate <= 2377500) in QAMSetSymbolrate()
5279 else if (state->props.symbol_rate <= 4755000) in QAMSetSymbolrate()
5281 status = write16(state, IQM_FD_RATESEL__A, ratesel); in QAMSetSymbolrate()
5288 symbFreq = state->props.symbol_rate * (1 << ratesel); in QAMSetSymbolrate()
5297 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate); in QAMSetSymbolrate()
5300 state->m_iqmRcRate = iqmRcRate; in QAMSetSymbolrate()
5304 symbFreq = state->props.symbol_rate; in QAMSetSymbolrate()
5315 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate); in QAMSetSymbolrate()
5332 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) in GetQAMLockStatus() argument
5339 status = scu_command(state, in GetQAMLockStatus()
5371 static int QAMDemodulatorCommand(struct drxk_state *state, in QAMDemodulatorCommand() argument
5378 setParamParameters[0] = state->m_Constellation; /* modulation */ in QAMDemodulatorCommand()
5384 if (state->m_OperationMode == OM_QAM_ITU_C) in QAMDemodulatorCommand()
5389 status = scu_command(state, in QAMDemodulatorCommand()
5395 status = scu_command(state, in QAMDemodulatorCommand()
5400 if (state->m_OperationMode == OM_QAM_ITU_C) in QAMDemodulatorCommand()
5410 status = scu_command(state, in QAMDemodulatorCommand()
5427 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, in SetQAM() argument
5432 int qamDemodParamCount = state->qam_demod_parameter_count; in SetQAM()
5441 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP); in SetQAM()
5444 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); in SetQAM()
5447 status = QAMResetQAM(state); in SetQAM()
5456 status = QAMSetSymbolrate(state); in SetQAM()
5461 switch (state->props.modulation) { in SetQAM()
5463 state->m_Constellation = DRX_CONSTELLATION_QAM256; in SetQAM()
5467 state->m_Constellation = DRX_CONSTELLATION_QAM64; in SetQAM()
5470 state->m_Constellation = DRX_CONSTELLATION_QAM16; in SetQAM()
5473 state->m_Constellation = DRX_CONSTELLATION_QAM32; in SetQAM()
5476 state->m_Constellation = DRX_CONSTELLATION_QAM128; in SetQAM()
5487 if (state->qam_demod_parameter_count == 4 in SetQAM()
5488 || !state->qam_demod_parameter_count) { in SetQAM()
5490 status = QAMDemodulatorCommand(state, qamDemodParamCount); in SetQAM()
5496 if (state->qam_demod_parameter_count == 2 in SetQAM()
5497 || (!state->qam_demod_parameter_count && status < 0)) { in SetQAM()
5499 status = QAMDemodulatorCommand(state, qamDemodParamCount); in SetQAM()
5506 state->qam_demod_parameter_count, in SetQAM()
5507 state->microcode_name); in SetQAM()
5509 } else if (!state->qam_demod_parameter_count) { in SetQAM()
5518 state->qam_demod_parameter_count = qamDemodParamCount; in SetQAM()
5530 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); in SetQAM()
5535 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate); in SetQAM()
5540 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE); in SetQAM()
5543 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE); in SetQAM()
5548 status = write16(state, QAM_LC_RATE_LIMIT__A, 3); in SetQAM()
5551 status = write16(state, QAM_LC_LPF_FACTORP__A, 4); in SetQAM()
5554 status = write16(state, QAM_LC_LPF_FACTORI__A, 4); in SetQAM()
5557 status = write16(state, QAM_LC_MODE__A, 7); in SetQAM()
5561 status = write16(state, QAM_LC_QUAL_TAB0__A, 1); in SetQAM()
5564 status = write16(state, QAM_LC_QUAL_TAB1__A, 1); in SetQAM()
5567 status = write16(state, QAM_LC_QUAL_TAB2__A, 1); in SetQAM()
5570 status = write16(state, QAM_LC_QUAL_TAB3__A, 1); in SetQAM()
5573 status = write16(state, QAM_LC_QUAL_TAB4__A, 2); in SetQAM()
5576 status = write16(state, QAM_LC_QUAL_TAB5__A, 2); in SetQAM()
5579 status = write16(state, QAM_LC_QUAL_TAB6__A, 2); in SetQAM()
5582 status = write16(state, QAM_LC_QUAL_TAB8__A, 2); in SetQAM()
5585 status = write16(state, QAM_LC_QUAL_TAB9__A, 2); in SetQAM()
5588 status = write16(state, QAM_LC_QUAL_TAB10__A, 2); in SetQAM()
5591 status = write16(state, QAM_LC_QUAL_TAB12__A, 2); in SetQAM()
5594 status = write16(state, QAM_LC_QUAL_TAB15__A, 3); in SetQAM()
5597 status = write16(state, QAM_LC_QUAL_TAB16__A, 3); in SetQAM()
5600 status = write16(state, QAM_LC_QUAL_TAB20__A, 4); in SetQAM()
5603 status = write16(state, QAM_LC_QUAL_TAB25__A, 4); in SetQAM()
5608 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS); in SetQAM()
5613 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in SetQAM()
5618 switch (state->props.modulation) { in SetQAM()
5620 status = SetQAM16(state); in SetQAM()
5623 status = SetQAM32(state); in SetQAM()
5627 status = SetQAM64(state); in SetQAM()
5630 status = SetQAM128(state); in SetQAM()
5633 status = SetQAM256(state); in SetQAM()
5643 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in SetQAM()
5650 status = MPEGTSDtoSetup(state, state->m_OperationMode); in SetQAM()
5655 status = MPEGTSStart(state); in SetQAM()
5658 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); in SetQAM()
5661 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE); in SetQAM()
5664 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE); in SetQAM()
5669 …status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NUL… in SetQAM()
5682 static int SetQAMStandard(struct drxk_state *state, in SetQAMStandard() argument
5695 SwitchAntennaToQAM(state); in SetQAMStandard()
5698 status = PowerUpQAM(state); in SetQAMStandard()
5702 status = QAMResetQAM(state); in SetQAMStandard()
5708 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP); in SetQAMStandard()
5711 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); in SetQAMStandard()
5719 …status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIM… in SetQAMStandard()
5722 …status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENT… in SetQAMStandard()
5725 …status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENT… in SetQAMStandard()
5733 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B)); in SetQAMStandard()
5736 status = write16(state, IQM_CF_SYMMETRIC__A, 0); in SetQAMStandard()
5739 …status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)… in SetQAMStandard()
5743 status = write16(state, IQM_RC_STRETCH__A, 21); in SetQAMStandard()
5746 status = write16(state, IQM_AF_CLP_LEN__A, 0); in SetQAMStandard()
5749 status = write16(state, IQM_AF_CLP_TH__A, 448); in SetQAMStandard()
5752 status = write16(state, IQM_AF_SNS_LEN__A, 0); in SetQAMStandard()
5755 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0); in SetQAMStandard()
5759 status = write16(state, IQM_FS_ADJ_SEL__A, 1); in SetQAMStandard()
5762 status = write16(state, IQM_RC_ADJ_SEL__A, 1); in SetQAMStandard()
5765 status = write16(state, IQM_CF_ADJ_SEL__A, 1); in SetQAMStandard()
5768 status = write16(state, IQM_AF_UPD_SEL__A, 0); in SetQAMStandard()
5773 status = write16(state, IQM_CF_CLP_VAL__A, 500); in SetQAMStandard()
5776 status = write16(state, IQM_CF_DATATH__A, 1000); in SetQAMStandard()
5779 status = write16(state, IQM_CF_BYPASSDET__A, 1); in SetQAMStandard()
5782 status = write16(state, IQM_CF_DET_LCT__A, 0); in SetQAMStandard()
5785 status = write16(state, IQM_CF_WND_LEN__A, 1); in SetQAMStandard()
5788 status = write16(state, IQM_CF_PKDTH__A, 1); in SetQAMStandard()
5791 status = write16(state, IQM_AF_INC_BYPASS__A, 1); in SetQAMStandard()
5796 status = SetIqmAf(state, true); in SetQAMStandard()
5799 status = write16(state, IQM_AF_START_LOCK__A, 0x01); in SetQAMStandard()
5804 status = ADCSynchronization(state); in SetQAMStandard()
5809 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000); in SetQAMStandard()
5814 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD); in SetQAMStandard()
5821 status = InitAGC(state, true); in SetQAMStandard()
5824 status = SetPreSaw(state, &(state->m_qamPreSawCfg)); in SetQAMStandard()
5829 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true); in SetQAMStandard()
5832 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true); in SetQAMStandard()
5837 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in SetQAMStandard()
5844 static int WriteGPIO(struct drxk_state *state) in WriteGPIO() argument
5851 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in WriteGPIO()
5856 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); in WriteGPIO()
5860 if (state->m_hasSAWSW) { in WriteGPIO()
5861 if (state->UIO_mask & 0x0001) { /* UIO-1 */ in WriteGPIO()
5863 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); in WriteGPIO()
5868 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in WriteGPIO()
5871 if ((state->m_GPIO & 0x0001) == 0) in WriteGPIO()
5876 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in WriteGPIO()
5880 if (state->UIO_mask & 0x0002) { /* UIO-2 */ in WriteGPIO()
5882 status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg); in WriteGPIO()
5887 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in WriteGPIO()
5890 if ((state->m_GPIO & 0x0002) == 0) in WriteGPIO()
5895 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in WriteGPIO()
5899 if (state->UIO_mask & 0x0004) { /* UIO-3 */ in WriteGPIO()
5901 status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg); in WriteGPIO()
5906 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); in WriteGPIO()
5909 if ((state->m_GPIO & 0x0004) == 0) in WriteGPIO()
5914 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value); in WriteGPIO()
5920 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); in WriteGPIO()
5927 static int SwitchAntennaToQAM(struct drxk_state *state) in SwitchAntennaToQAM() argument
5934 if (!state->antenna_gpio) in SwitchAntennaToQAM()
5937 gpio_state = state->m_GPIO & state->antenna_gpio; in SwitchAntennaToQAM()
5939 if (state->antenna_dvbt ^ gpio_state) { in SwitchAntennaToQAM()
5941 if (state->antenna_dvbt) in SwitchAntennaToQAM()
5942 state->m_GPIO &= ~state->antenna_gpio; in SwitchAntennaToQAM()
5944 state->m_GPIO |= state->antenna_gpio; in SwitchAntennaToQAM()
5945 status = WriteGPIO(state); in SwitchAntennaToQAM()
5952 static int SwitchAntennaToDVBT(struct drxk_state *state) in SwitchAntennaToDVBT() argument
5959 if (!state->antenna_gpio) in SwitchAntennaToDVBT()
5962 gpio_state = state->m_GPIO & state->antenna_gpio; in SwitchAntennaToDVBT()
5964 if (!(state->antenna_dvbt ^ gpio_state)) { in SwitchAntennaToDVBT()
5966 if (state->antenna_dvbt) in SwitchAntennaToDVBT()
5967 state->m_GPIO |= state->antenna_gpio; in SwitchAntennaToDVBT()
5969 state->m_GPIO &= ~state->antenna_gpio; in SwitchAntennaToDVBT()
5970 status = WriteGPIO(state); in SwitchAntennaToDVBT()
5978 static int PowerDownDevice(struct drxk_state *state) in PowerDownDevice() argument
5989 if (state->m_bPDownOpenBridge) { in PowerDownDevice()
5991 status = ConfigureI2CBridge(state, true); in PowerDownDevice()
5996 status = DVBTEnableOFDMTokenRing(state, false); in PowerDownDevice()
6000 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK); in PowerDownDevice()
6003 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in PowerDownDevice()
6006 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in PowerDownDevice()
6007 status = HI_CfgCommand(state); in PowerDownDevice()
6015 static int init_drxk(struct drxk_state *state) in init_drxk() argument
6022 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { in init_drxk()
6023 drxk_i2c_lock(state); in init_drxk()
6024 status = PowerUpDevice(state); in init_drxk()
6027 status = DRXX_Open(state); in init_drxk()
6031 …status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO… in init_drxk()
6034 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); in init_drxk()
6039 state->m_DRXK_A3_PATCH_CODE = true; in init_drxk()
6040 status = GetDeviceCapabilities(state); in init_drxk()
6047 state->m_HICfgBridgeDelay = in init_drxk()
6048 (u16) ((state->m_oscClockFreq / 1000) * in init_drxk()
6051 if (state->m_HICfgBridgeDelay > in init_drxk()
6053 state->m_HICfgBridgeDelay = in init_drxk()
6057 state->m_HICfgBridgeDelay += in init_drxk()
6058 state->m_HICfgBridgeDelay << in init_drxk()
6061 status = InitHI(state); in init_drxk()
6066 if (!(state->m_DRXK_A1_ROM_CODE) in init_drxk()
6067 && !(state->m_DRXK_A2_ROM_CODE)) in init_drxk()
6070 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); in init_drxk()
6076 status = MPEGTSDisable(state); in init_drxk()
6081 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP); in init_drxk()
6084 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP); in init_drxk()
6089 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON); in init_drxk()
6094 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE); in init_drxk()
6097 status = BLChainCmd(state, 0, 6, 100); in init_drxk()
6101 if (state->fw) { in init_drxk()
6102 status = DownloadMicrocode(state, state->fw->data, in init_drxk()
6103 state->fw->size); in init_drxk()
6109 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); in init_drxk()
6114 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); in init_drxk()
6117 status = DRXX_Open(state); in init_drxk()
6124 status = CtrlPowerMode(state, &powerMode); in init_drxk()
6139 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion); in init_drxk()
6147 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion); in init_drxk()
6163 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); in init_drxk()
6169 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP); in init_drxk()
6173 status = MPEGTSDtoInit(state); in init_drxk()
6176 status = MPEGTSStop(state); in init_drxk()
6179 status = MPEGTSConfigurePolarity(state); in init_drxk()
6182 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput); in init_drxk()
6186 status = WriteGPIO(state); in init_drxk()
6190 state->m_DrxkState = DRXK_STOPPED; in init_drxk()
6192 if (state->m_bPowerDown) { in init_drxk()
6193 status = PowerDownDevice(state); in init_drxk()
6196 state->m_DrxkState = DRXK_POWERED_DOWN; in init_drxk()
6198 state->m_DrxkState = DRXK_STOPPED; in init_drxk()
6202 if (state->m_hasDVBC) { in init_drxk()
6203 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; in init_drxk()
6204 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; in init_drxk()
6205 strlcat(state->frontend.ops.info.name, " DVB-C", in init_drxk()
6206 sizeof(state->frontend.ops.info.name)); in init_drxk()
6208 if (state->m_hasDVBT) { in init_drxk()
6209 state->frontend.ops.delsys[n++] = SYS_DVBT; in init_drxk()
6210 strlcat(state->frontend.ops.info.name, " DVB-T", in init_drxk()
6211 sizeof(state->frontend.ops.info.name)); in init_drxk()
6213 drxk_i2c_unlock(state); in init_drxk()
6217 state->m_DrxkState = DRXK_NO_DEV; in init_drxk()
6218 drxk_i2c_unlock(state); in init_drxk()
6228 struct drxk_state *state = context; in load_firmware_cb() local
6234 state->microcode_name); in load_firmware_cb()
6237 state->microcode_name); in load_firmware_cb()
6238 state->microcode_name = NULL; in load_firmware_cb()
6251 state->fw = fw; in load_firmware_cb()
6253 init_drxk(state); in load_firmware_cb()
6258 struct drxk_state *state = fe->demodulator_priv; in drxk_release() local
6261 if (state->fw) in drxk_release()
6262 release_firmware(state->fw); in drxk_release()
6264 kfree(state); in drxk_release()
6269 struct drxk_state *state = fe->demodulator_priv; in drxk_sleep() local
6273 if (state->m_DrxkState == DRXK_NO_DEV) in drxk_sleep()
6275 if (state->m_DrxkState == DRXK_UNINITIALIZED) in drxk_sleep()
6278 ShutDown(state); in drxk_sleep()
6284 struct drxk_state *state = fe->demodulator_priv; in drxk_gate_ctrl() local
6288 if (state->m_DrxkState == DRXK_NO_DEV) in drxk_gate_ctrl()
6291 return ConfigureI2CBridge(state, enable ? true : false); in drxk_gate_ctrl()
6298 struct drxk_state *state = fe->demodulator_priv; in drxk_set_parameters() local
6303 if (state->m_DrxkState == DRXK_NO_DEV) in drxk_set_parameters()
6306 if (state->m_DrxkState == DRXK_UNINITIALIZED) in drxk_set_parameters()
6322 old_delsys = state->props.delivery_system; in drxk_set_parameters()
6323 state->props = *p; in drxk_set_parameters()
6326 ShutDown(state); in drxk_set_parameters()
6330 if (!state->m_hasDVBC) in drxk_set_parameters()
6332 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false; in drxk_set_parameters()
6333 if (state->m_itut_annex_c) in drxk_set_parameters()
6334 SetOperationMode(state, OM_QAM_ITU_C); in drxk_set_parameters()
6336 SetOperationMode(state, OM_QAM_ITU_A); in drxk_set_parameters()
6339 if (!state->m_hasDVBT) in drxk_set_parameters()
6341 SetOperationMode(state, OM_DVBT); in drxk_set_parameters()
6349 Start(state, 0, IF); in drxk_set_parameters()
6366 static int get_strength(struct drxk_state *state, u64 *strength) in get_strength() argument
6381 if (IsDVBT(state)) { in get_strength()
6382 rfAgc = state->m_dvbtRfAgcCfg; in get_strength()
6383 ifAgc = state->m_dvbtIfAgcCfg; in get_strength()
6384 } else if (IsQAM(state)) { in get_strength()
6385 rfAgc = state->m_qamRfAgcCfg; in get_strength()
6386 ifAgc = state->m_qamIfAgcCfg; in get_strength()
6388 rfAgc = state->m_atvRfAgcCfg; in get_strength()
6389 ifAgc = state->m_atvIfAgcCfg; in get_strength()
6394 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); in get_strength()
6399 read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc); in get_strength()
6427 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, in get_strength()
6432 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, in get_strength()
6470 struct drxk_state *state = fe->demodulator_priv; in drxk_get_stats() local
6483 if (state->m_DrxkState == DRXK_NO_DEV) in drxk_get_stats()
6485 if (state->m_DrxkState == DRXK_UNINITIALIZED) in drxk_get_stats()
6489 state->fe_status = 0; in drxk_get_stats()
6490 GetLockStatus(state, &stat); in drxk_get_stats()
6492 state->fe_status |= 0x1f; in drxk_get_stats()
6494 state->fe_status |= 0x0f; in drxk_get_stats()
6496 state->fe_status |= 0x07; in drxk_get_stats()
6501 get_strength(state, &c->strength.stat[0].uvalue); in drxk_get_stats()
6506 GetSignalToNoise(state, &cnr); in drxk_get_stats()
6532 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16); in drxk_get_stats()
6537 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16); in drxk_get_stats()
6543 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16); in drxk_get_stats()
6548 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16); in drxk_get_stats()
6553 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16); in drxk_get_stats()
6558 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16); in drxk_get_stats()
6562 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); in drxk_get_stats()
6591 struct drxk_state *state = fe->demodulator_priv; in drxk_read_status() local
6600 *status = state->fe_status; in drxk_read_status()
6608 struct drxk_state *state = fe->demodulator_priv; in drxk_read_signal_strength() local
6613 if (state->m_DrxkState == DRXK_NO_DEV) in drxk_read_signal_strength()
6615 if (state->m_DrxkState == DRXK_UNINITIALIZED) in drxk_read_signal_strength()
6624 struct drxk_state *state = fe->demodulator_priv; in drxk_read_snr() local
6629 if (state->m_DrxkState == DRXK_NO_DEV) in drxk_read_snr()
6631 if (state->m_DrxkState == DRXK_UNINITIALIZED) in drxk_read_snr()
6634 GetSignalToNoise(state, &snr2); in drxk_read_snr()
6645 struct drxk_state *state = fe->demodulator_priv; in drxk_read_ucblocks() local
6650 if (state->m_DrxkState == DRXK_NO_DEV) in drxk_read_ucblocks()
6652 if (state->m_DrxkState == DRXK_UNINITIALIZED) in drxk_read_ucblocks()
6655 DVBTQAMGetAccPktErr(state, &err); in drxk_read_ucblocks()
6663 struct drxk_state *state = fe->demodulator_priv; in drxk_get_tune_settings() local
6668 if (state->m_DrxkState == DRXK_NO_DEV) in drxk_get_tune_settings()
6670 if (state->m_DrxkState == DRXK_UNINITIALIZED) in drxk_get_tune_settings()
6723 struct drxk_state *state = NULL; in drxk_attach() local
6728 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); in drxk_attach()
6729 if (!state) in drxk_attach()
6732 state->i2c = i2c; in drxk_attach()
6733 state->demod_address = adr; in drxk_attach()
6734 state->single_master = config->single_master; in drxk_attach()
6735 state->microcode_name = config->microcode_name; in drxk_attach()
6736 state->qam_demod_parameter_count = config->qam_demod_parameter_count; in drxk_attach()
6737 state->no_i2c_bridge = config->no_i2c_bridge; in drxk_attach()
6738 state->antenna_gpio = config->antenna_gpio; in drxk_attach()
6739 state->antenna_dvbt = config->antenna_dvbt; in drxk_attach()
6740 state->m_ChunkSize = config->chunk_size; in drxk_attach()
6741 state->enable_merr_cfg = config->enable_merr_cfg; in drxk_attach()
6744 state->m_DVBTStaticCLK = 0; in drxk_attach()
6745 state->m_DVBCStaticCLK = 0; in drxk_attach()
6747 state->m_DVBTStaticCLK = 1; in drxk_attach()
6748 state->m_DVBCStaticCLK = 1; in drxk_attach()
6753 state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07; in drxk_attach()
6755 state->m_TSClockkStrength = 0x06; in drxk_attach()
6758 state->m_enableParallel = true; in drxk_attach()
6760 state->m_enableParallel = false; in drxk_attach()
6763 state->UIO_mask = config->antenna_gpio; in drxk_attach()
6766 if (!state->antenna_dvbt && state->antenna_gpio) in drxk_attach()
6767 state->m_GPIO |= state->antenna_gpio; in drxk_attach()
6769 state->m_GPIO &= ~state->antenna_gpio; in drxk_attach()
6771 mutex_init(&state->mutex); in drxk_attach()
6773 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); in drxk_attach()
6774 state->frontend.demodulator_priv = state; in drxk_attach()
6776 init_state(state); in drxk_attach()
6779 if (state->microcode_name) { in drxk_attach()
6783 status = request_firmware(&fw, state->microcode_name, in drxk_attach()
6784 state->i2c->dev.parent); in drxk_attach()
6787 load_firmware_cb(fw, state); in drxk_attach()
6790 state->microcode_name, in drxk_attach()
6791 state->i2c->dev.parent, in drxk_attach()
6793 state, load_firmware_cb); in drxk_attach()
6800 } else if (init_drxk(state) < 0) in drxk_attach()
6805 p = &state->frontend.dtv_property_cache; in drxk_attach()
6825 return &state->frontend; in drxk_attach()
6829 kfree(state); in drxk_attach()