217 	u8 r12, r15, r17, r18, r3D, r82, r84, r89;  in mxl111sf_config_pin_mux_modes()  local
234 	ret = mxl111sf_read_reg(state, 0x82, &r82);  in mxl111sf_config_pin_mux_modes()
264 		r82 |= PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
266 		r82 |= PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
268 		r82 |= PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
270 		r82 |= PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
292 		r82 |= PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
294 		r82 |= PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
296 		r82 |= PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
298 		r82 |= PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
320 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
322 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
324 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
326 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
348 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
350 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
352 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
354 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
376 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
378 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
380 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
382 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
404 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
406 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
408 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
410 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
432 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
434 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
436 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
438 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
460 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
462 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
464 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
466 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
488 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
490 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
492 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
494 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
517 		r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
519 		r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
521 		r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
523 		r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;  in mxl111sf_config_pin_mux_modes()
543 	ret = mxl111sf_write_reg(state, 0x82, r82);  in mxl111sf_config_pin_mux_modes()