Lines Matching refs:BIT
108 #define TWSI_CTRL_LD_EXIST BIT(23)
109 #define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */
110 #define TWSI_CTRL_SW_LDSTART BIT(11)
122 #define PCIE_PHYMISC_FORCE_RCV_DET BIT(2)
135 #define TWSI_DEBUG_DEV_EXIST BIT(29)
138 #define DMA_DBG_VENDOR_MSG BIT(0)
151 #define OTP_CTRL_CLK_EN BIT(1)
154 #define PM_CTRL_HOTRST BIT(31)
155 #define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on
157 #define PM_CTRL_SA_DLY_EN BIT(29)
158 #define PM_CTRL_L0S_BUFSRX_EN BIT(28)
166 #define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */
181 #define PM_CTRL_RCVR_WT_TIMER BIT(15) /* 1:1us, 0:2ms */
182 #define PM_CTRL_CLK_PWM_VER1_1 BIT(14) /* 0:1.0a,1:1.1 */
183 #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */
184 #define PM_CTRL_ASPM_L0S_EN BIT(12)
185 #define PM_CTRL_RXL1_AFTER_L0S BIT(11) /* l1dv2.0+ */
190 #define PM_CTRL_SERDES_BUFS_RX_L1_EN BIT(7)
191 #define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */
192 #define PM_CTRL_SERDES_PLL_L1_EN BIT(5)
193 #define PM_CTRL_SERDES_L1_EN BIT(4)
194 #define PM_CTRL_ASPM_L1_EN BIT(3)
195 #define PM_CTRL_CLK_REQ_EN BIT(2)
196 #define PM_CTRL_RBER_EN BIT(1)
197 #define PM_CTRL_SPRSDWER_EN BIT(0)
205 #define MASTER_CTRL_OTP_SEL BIT(31)
210 #define MASTER_CTRL_INT_RDCLR BIT(14)
211 #define MASTER_CTRL_CLK_SEL_DIS BIT(12) /* 1:alwys sel pclk from
213 #define MASTER_CTRL_RX_ITIMER_EN BIT(11) /* IRQ MODURATION FOR RX */
214 #define MASTER_CTRL_TX_ITIMER_EN BIT(10) /* MODURATION FOR TX/RX */
215 #define MASTER_CTRL_MANU_INT BIT(9) /* SOFT MANUAL INT */
216 #define MASTER_CTRL_MANUTIMER_EN BIT(8)
217 #define MASTER_CTRL_SA_TIMER_EN BIT(7) /* SYS ALIVE TIMER EN */
218 #define MASTER_CTRL_OOB_DIS BIT(6) /* OUT OF BOX DIS */
219 #define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */
220 #define MASTER_CTRL_BERT_START BIT(4)
223 #define MASTER_PCIE_RST BIT(1)
224 #define MASTER_CTRL_SOFT_RST BIT(0) /* RST MAC & DMA */
239 #define GPHY_CTRL_BP_VLTGSW BIT(18)
240 #define GPHY_CTRL_100AB_EN BIT(17)
241 #define GPHY_CTRL_10AB_EN BIT(16)
242 #define GPHY_CTRL_PHY_PLL_BYPASS BIT(15)
243 #define GPHY_CTRL_PWDOWN_HW BIT(14) /* affect MAC&PHY, to low pw */
244 #define GPHY_CTRL_PHY_PLL_ON BIT(13) /* 1:pll always on, 0:can sw */
245 #define GPHY_CTRL_SEL_ANA_RST BIT(12)
246 #define GPHY_CTRL_HIB_PULSE BIT(11)
247 #define GPHY_CTRL_HIB_EN BIT(10)
248 #define GPHY_CTRL_GIGA_DIS BIT(9)
249 #define GPHY_CTRL_PHY_IDDQ_DIS BIT(8) /* pw on RST */
250 #define GPHY_CTRL_PHY_IDDQ BIT(7) /* bit8 affect bit7 while rb */
251 #define GPHY_CTRL_LPW_EXIT BIT(6)
252 #define GPHY_CTRL_GATE_25M_EN BIT(5)
253 #define GPHY_CTRL_REV_ANEG BIT(4)
254 #define GPHY_CTRL_ANEG_NOW BIT(3)
255 #define GPHY_CTRL_LED_MODE BIT(2)
256 #define GPHY_CTRL_RTL_MODE BIT(1)
257 #define GPHY_CTRL_EXT_RESET BIT(0) /* 1:out of DSP RST status */
268 #define IDLE_STATUS_CALIB_DONE BIT(13)
273 #define IDLE_STATUS_TXQ_BUSY BIT(3)
274 #define IDLE_STATUS_RXQ_BUSY BIT(2)
275 #define IDLE_STATUS_TXMAC_BUSY BIT(1)
276 #define IDLE_STATUS_RXMAC_BUSY BIT(0)
285 #define MDIO_CTRL_MODE_EXT BIT(30)
286 #define MDIO_CTRL_POST_READ BIT(29)
287 #define MDIO_CTRL_AP_EN BIT(28)
288 #define MDIO_CTRL_BUSY BIT(27)
298 #define MDIO_CTRL_START BIT(23)
299 #define MDIO_CTRL_SPRES_PRMBL BIT(22)
300 #define MDIO_CTRL_OP_READ BIT(21) /* 1:read, 0:write */
334 #define SERDES_PHY_CLK_SLOWDOWN BIT(18)
335 #define SERDES_MAC_CLK_SLOWDOWN BIT(17)
338 #define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */
339 #define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */
340 #define SERDES_BUFS_RX_EN BIT(11)
341 #define SERDES_PD_RX BIT(10)
342 #define SERDES_PLL_EN BIT(9)
343 #define SERDES_EN BIT(8)
344 #define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */
351 #define SERDES_VCO_SLOW BIT(3)
352 #define SERDES_VCO_FAST BIT(2)
353 #define SERDES_LOCK_DETECT_EN BIT(1)
354 #define SERDES_LOCK_DETECT BIT(0)
360 #define LPI_CTRL_CHK_DA BIT(31)
365 #define LPI_CTRL_ENH_EN BIT(5)
366 #define LPI_CTRL_CHK_RX BIT(4)
367 #define LPI_CTRL_CHK_STATE BIT(3)
368 #define LPI_CTRL_GMII BIT(2)
369 #define LPI_CTRL_TO_PHY BIT(1)
370 #define LPI_CTRL_EN BIT(0)
378 #define MAC_CTRL_SPEED_MODE_SW BIT(30) /* 0:phy,1:sw */
379 #define MAC_CTRL_HASH_ALG_CRC32 BIT(29) /* 1:legacy,0:lw_5b */
380 #define MAC_CTRL_SINGLE_PAUSE_EN BIT(28)
381 #define MAC_CTRL_DBG BIT(27)
382 #define MAC_CTRL_BC_EN BIT(26)
383 #define MAC_CTRL_MC_ALL_EN BIT(25)
384 #define MAC_CTRL_RX_CHKSUM_EN BIT(24)
385 #define MAC_CTRL_TX_HUGE BIT(23)
386 #define MAC_CTRL_DBG_TX_BKPRESURE BIT(22)
391 #define MAC_CTRL_TX_SIMURST BIT(19)
392 #define MAC_CTRL_SCNT BIT(17)
393 #define MAC_CTRL_TX_PAUSE BIT(16)
394 #define MAC_CTRL_PROMIS_EN BIT(15)
395 #define MAC_CTRL_RMV_VLAN BIT(14)
398 #define MAC_CTRL_HUGE_EN BIT(9)
399 #define MAC_CTRL_LENCHK BIT(8)
400 #define MAC_CTRL_PAD BIT(7)
401 #define MAC_CTRL_ADD_CRC BIT(6)
402 #define MAC_CTRL_DUPLX BIT(5)
403 #define MAC_CTRL_LOOPBACK BIT(4)
404 #define MAC_CTRL_RX_FLOW BIT(3)
405 #define MAC_CTRL_TX_FLOW BIT(2)
406 #define MAC_CTRL_RX_EN BIT(1)
407 #define MAC_CTRL_TX_EN BIT(0)
451 #define WOL_PT7_MATCH BIT(31)
452 #define WOL_PT6_MATCH BIT(30)
453 #define WOL_PT5_MATCH BIT(29)
454 #define WOL_PT4_MATCH BIT(28)
455 #define WOL_PT3_MATCH BIT(27)
456 #define WOL_PT2_MATCH BIT(26)
457 #define WOL_PT1_MATCH BIT(25)
458 #define WOL_PT0_MATCH BIT(24)
459 #define WOL_PT7_EN BIT(23)
460 #define WOL_PT6_EN BIT(22)
461 #define WOL_PT5_EN BIT(21)
462 #define WOL_PT4_EN BIT(20)
463 #define WOL_PT3_EN BIT(19)
464 #define WOL_PT2_EN BIT(18)
465 #define WOL_PT1_EN BIT(17)
466 #define WOL_PT0_EN BIT(16)
467 #define WOL_LNKCHG_ST BIT(10)
468 #define WOL_MAGIC_ST BIT(9)
469 #define WOL_PATTERN_ST BIT(8)
470 #define WOL_OOB_EN BIT(6)
471 #define WOL_LINK_CHG_PME_EN BIT(5)
472 #define WOL_LINK_CHG_EN BIT(4)
473 #define WOL_MAGIC_PME_EN BIT(3)
474 #define WOL_MAGIC_EN BIT(2)
475 #define WOL_PATTERN_PME_EN BIT(1)
476 #define WOL_PATTERN_EN BIT(0)
561 #define TXQ_CTRL_PEDING_CLR BIT(8)
562 #define TXQ_CTRL_LS_8023_EN BIT(7)
563 #define TXQ_CTRL_ENH_MODE BIT(6)
564 #define TXQ_CTRL_EN BIT(5)
565 #define TXQ_CTRL_IP_OPTION_EN BIT(4)
606 #define IPV6_CHKSUM_CTRL_EN BIT(7)
616 #define RSS_NIP_QUEUE_SEL BIT(28) /* 0:q0, 1:table */
617 #define RRS_HASH_CTRL_EN BIT(29)
618 #define RX_CUT_THRU_EN BIT(30)
619 #define RXQ_CTRL_EN BIT(31)
641 #define DMA_CTRL_SMB_NOW BIT(31)
642 #define DMA_CTRL_WPEND_CLR BIT(30)
643 #define DMA_CTRL_RPEND_CLR BIT(29)
650 #define DMA_CTRL_RREQ_PRI_DATA BIT(10) /* 0:tpd, 1:data */
655 #define L1C_CTRL_DMA_RCB_LEN128 BIT(3) /* 0:64bytes,1:128bytes */