Lines Matching refs:phy
30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
1493 params->phy[phy_index].mdio_ctrl); in bnx2x_set_mdio_emac_per_phy()
1799 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { in bnx2x_xmac_enable()
1830 (params->phy[INT_PHY].supported & in bnx2x_xmac_enable()
2632 struct bnx2x_phy *phy, in bnx2x_cl22_write() argument
2639 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_write()
2640 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2644 tmp = ((phy->addr << 21) | (reg << 16) | val | in bnx2x_cl22_write()
2647 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2652 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_write()
2662 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2667 struct bnx2x_phy *phy, in bnx2x_cl22_read() argument
2675 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_read()
2676 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2680 val = ((phy->addr << 21) | (reg << 16) | in bnx2x_cl22_read()
2683 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2688 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_read()
2701 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2708 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read() argument
2715 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { in bnx2x_cl45_read()
2718 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_read()
2721 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_read()
2722 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2725 val = ((phy->addr << 21) | (devad << 16) | reg | in bnx2x_cl45_read()
2728 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2733 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_read()
2746 val = ((phy->addr << 21) | (devad << 16) | in bnx2x_cl45_read()
2749 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2754 val = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_read()
2769 if (phy->flags & FLAGS_MDC_MDIO_WA) { in bnx2x_cl45_read()
2770 phy->flags ^= FLAGS_DUMMY_READ; in bnx2x_cl45_read()
2771 if (phy->flags & FLAGS_DUMMY_READ) { in bnx2x_cl45_read()
2773 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_read()
2777 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_read()
2778 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2783 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_write() argument
2790 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { in bnx2x_cl45_write()
2793 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_write()
2796 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_write()
2797 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2801 tmp = ((phy->addr << 21) | (devad << 16) | reg | in bnx2x_cl45_write()
2804 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2809 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_write()
2821 tmp = ((phy->addr << 21) | (devad << 16) | val | in bnx2x_cl45_write()
2824 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2829 tmp = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_write()
2843 if (phy->flags & FLAGS_MDC_MDIO_WA) { in bnx2x_cl45_write()
2844 phy->flags ^= FLAGS_DUMMY_READ; in bnx2x_cl45_write()
2845 if (phy->flags & FLAGS_DUMMY_READ) { in bnx2x_cl45_write()
2847 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_write()
2850 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_write()
2851 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2994 static int bnx2x_eee_disable(struct bnx2x_phy *phy, in bnx2x_eee_disable() argument
3003 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); in bnx2x_eee_disable()
3010 static int bnx2x_eee_advertise(struct bnx2x_phy *phy, in bnx2x_eee_advertise() argument
3029 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); in bnx2x_eee_advertise()
3047 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, in bnx2x_eee_an_resolve() argument
3056 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); in bnx2x_eee_an_resolve()
3057 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); in bnx2x_eee_an_resolve()
3124 struct bnx2x_phy *phy, in bnx2x_bsc_read() argument
3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read_or_write() argument
3215 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_or_write()
3216 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); in bnx2x_cl45_read_or_write()
3220 struct bnx2x_phy *phy, in bnx2x_cl45_read_and_write() argument
3224 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_and_write()
3225 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); in bnx2x_cl45_read_and_write()
3236 if (params->phy[phy_index].addr == phy_addr) { in bnx2x_phy_read()
3238 ¶ms->phy[phy_index], devad, in bnx2x_phy_read()
3253 if (params->phy[phy_index].addr == phy_addr) { in bnx2x_phy_write()
3255 ¶ms->phy[phy_index], devad, in bnx2x_phy_write()
3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, in bnx2x_get_warpcore_lane() argument
3316 struct bnx2x_phy *phy) in bnx2x_set_aer_mmd() argument
3325 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? in bnx2x_set_aer_mmd()
3326 (phy->addr + ser_lane) : 0; in bnx2x_set_aer_mmd()
3329 aer_val = bnx2x_get_warpcore_lane(phy, params); in bnx2x_set_aer_mmd()
3336 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_set_aer_mmd()
3343 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_aer_mmd()
3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy, in bnx2x_xgxs_specific_func() argument
3395 phy->def_md_devad); in bnx2x_xgxs_specific_func()
3414 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, in bnx2x_xgxs_deassert()
3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, in bnx2x_calc_ieee_aneg_adv() argument
3427 switch (phy->req_flow_ctrl) { in bnx2x_calc_ieee_aneg_adv()
3476 params->phy[actual_phy_idx].req_flow_ctrl = in set_phy_vars()
3479 params->phy[actual_phy_idx].req_line_speed = in set_phy_vars()
3482 params->phy[actual_phy_idx].speed_cap_mask = in set_phy_vars()
3485 params->phy[actual_phy_idx].req_duplex = in set_phy_vars()
3494 params->phy[actual_phy_idx].req_flow_ctrl, in set_phy_vars()
3495 params->phy[actual_phy_idx].req_line_speed, in set_phy_vars()
3496 params->phy[actual_phy_idx].speed_cap_mask); in set_phy_vars()
3501 struct bnx2x_phy *phy, in bnx2x_ext_phy_set_pause() argument
3507 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); in bnx2x_ext_phy_set_pause()
3512 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_ext_phy_set_pause()
3524 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); in bnx2x_ext_phy_set_pause()
3555 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, in bnx2x_ext_phy_update_adv_fc() argument
3563 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { in bnx2x_ext_phy_update_adv_fc()
3564 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); in bnx2x_ext_phy_update_adv_fc()
3565 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); in bnx2x_ext_phy_update_adv_fc()
3568 u8 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_ext_phy_update_adv_fc()
3570 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3577 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3579 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3582 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3584 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3594 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3597 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3610 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, in bnx2x_ext_phy_resolve_fc() argument
3616 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { in bnx2x_ext_phy_resolve_fc()
3618 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_ext_phy_resolve_fc()
3619 bnx2x_ext_phy_update_adv_fc(phy, params, vars); in bnx2x_ext_phy_resolve_fc()
3621 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_ext_phy_resolve_fc()
3622 } else if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_ext_phy_resolve_fc()
3626 bnx2x_ext_phy_update_adv_fc(phy, params, vars); in bnx2x_ext_phy_resolve_fc()
3648 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, in bnx2x_warpcore_enable_AN_KR2() argument
3675 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR2()
3679 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR2()
3687 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, in bnx2x_warpcore_set_lpi_passthrough() argument
3693 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3695 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3699 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy, in bnx2x_warpcore_restart_AN_KR() argument
3704 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_restart_AN_KR()
3705 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_restart_AN_KR()
3707 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_restart_AN_KR()
3711 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_restart_AN_KR()
3714 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, in bnx2x_warpcore_enable_AN_KR() argument
3733 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR()
3736 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3740 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3745 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || in bnx2x_warpcore_enable_AN_KR()
3751 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); in bnx2x_warpcore_enable_AN_KR()
3755 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || in bnx2x_warpcore_enable_AN_KR()
3760 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3763 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3765 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_enable_AN_KR()
3770 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_enable_AN_KR()
3771 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3775 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_warpcore_enable_AN_KR()
3776 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3779 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3782 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3787 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3791 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3801 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3808 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_warpcore_enable_AN_KR()
3811 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3818 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3822 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3825 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_warpcore_enable_AN_KR()
3826 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || in bnx2x_warpcore_enable_AN_KR()
3827 (phy->req_line_speed == SPEED_20000)) { in bnx2x_warpcore_enable_AN_KR()
3829 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3832 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3836 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3838 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_enable_AN_KR()
3840 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); in bnx2x_warpcore_enable_AN_KR()
3844 bnx2x_warpcore_restart_AN_KR(phy, params); in bnx2x_warpcore_enable_AN_KR()
3847 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, in bnx2x_warpcore_set_10G_KR() argument
3867 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_set_10G_KR()
3870 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_set_10G_KR()
3872 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_10G_KR()
3875 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3878 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3881 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3884 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3887 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_set_10G_KR()
3889 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3892 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3896 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3900 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3904 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3908 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3910 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3915 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, in bnx2x_warpcore_set_10G_XFI() argument
3924 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3928 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3932 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); in bnx2x_warpcore_set_10G_XFI()
3935 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3939 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3943 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3947 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3952 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3954 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3959 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3994 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3998 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_set_10G_XFI()
3999 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4002 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4007 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4011 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4014 bnx2x_warpcore_set_lpi_passthrough(phy, params); in bnx2x_warpcore_set_10G_XFI()
4017 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4021 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4025 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4029 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy, in bnx2x_warpcore_set_20G_force_KR2() argument
4035 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4039 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4042 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_set_20G_force_KR2()
4044 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4046 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4049 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4053 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4057 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4060 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4063 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4067 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4069 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4073 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4076 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4079 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_set_20G_force_KR2()
4083 struct bnx2x_phy *phy, in bnx2x_warpcore_set_20G_DXGXS() argument
4087 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4091 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4094 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4097 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4100 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4103 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4106 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4109 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4112 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4115 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4119 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4123 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4127 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4131 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4136 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, in bnx2x_warpcore_set_sgmii_speed() argument
4145 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4148 bnx2x_warpcore_set_lpi_passthrough(phy, params); in bnx2x_warpcore_set_sgmii_speed()
4150 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_warpcore_set_sgmii_speed()
4152 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4157 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4160 switch (phy->req_line_speed) { in bnx2x_warpcore_set_sgmii_speed()
4171 "Speed not supported: 0x%x\n", phy->req_line_speed); in bnx2x_warpcore_set_sgmii_speed()
4175 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_warpcore_set_sgmii_speed()
4178 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4182 phy->req_line_speed); in bnx2x_warpcore_set_sgmii_speed()
4183 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4189 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4196 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4201 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4203 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4208 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4213 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4219 struct bnx2x_phy *phy, in bnx2x_warpcore_reset_lane() argument
4224 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4230 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4232 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4236 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, in bnx2x_warpcore_clear_regs() argument
4259 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4263 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, in bnx2x_warpcore_clear_regs()
4266 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_clear_regs()
4267 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4311 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, in bnx2x_is_sfp_module_plugged() argument
4329 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, in bnx2x_warpcore_get_sigdet() argument
4335 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_get_sigdet()
4337 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, in bnx2x_warpcore_get_sigdet()
4343 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, in bnx2x_warpcore_config_runtime() argument
4350 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_runtime()
4358 if (!(bnx2x_warpcore_get_sigdet(phy, params))) { in bnx2x_warpcore_config_runtime()
4372 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, in bnx2x_warpcore_config_runtime()
4388 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_runtime()
4389 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_runtime()
4392 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_config_runtime()
4408 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, in bnx2x_warpcore_config_sfi() argument
4411 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_sfi()
4413 bnx2x_warpcore_clear_regs(phy, params, lane); in bnx2x_warpcore_config_sfi()
4416 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { in bnx2x_warpcore_config_sfi()
4418 bnx2x_warpcore_set_10G_XFI(phy, params, 0); in bnx2x_warpcore_config_sfi()
4421 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); in bnx2x_warpcore_config_sfi()
4426 struct bnx2x_phy *phy, in bnx2x_sfp_e3_set_transmitter() argument
4442 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) in bnx2x_sfp_e3_set_transmitter()
4446 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, in bnx2x_warpcore_config_init() argument
4453 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_init()
4461 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_config_init()
4462 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_init()
4465 (phy->req_line_speed && in bnx2x_warpcore_config_init()
4466 ((phy->req_line_speed == SPEED_100) || in bnx2x_warpcore_config_init()
4467 (phy->req_line_speed == SPEED_10)))) { in bnx2x_warpcore_config_init()
4470 bnx2x_warpcore_clear_regs(phy, params, lane); in bnx2x_warpcore_config_init()
4471 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); in bnx2x_warpcore_config_init()
4477 bnx2x_warpcore_enable_AN_KR(phy, params, vars); in bnx2x_warpcore_config_init()
4480 bnx2x_warpcore_set_10G_KR(phy, params, vars); in bnx2x_warpcore_config_init()
4485 bnx2x_warpcore_clear_regs(phy, params, lane); in bnx2x_warpcore_config_init()
4488 bnx2x_warpcore_set_10G_XFI(phy, params, 1); in bnx2x_warpcore_config_init()
4497 bnx2x_warpcore_set_sgmii_speed(phy, in bnx2x_warpcore_config_init()
4510 if (bnx2x_is_sfp_module_plugged(phy, params)) in bnx2x_warpcore_config_init()
4511 bnx2x_sfp_module_detection(phy, params); in bnx2x_warpcore_config_init()
4513 bnx2x_sfp_e3_set_transmitter(params, phy, 1); in bnx2x_warpcore_config_init()
4515 bnx2x_warpcore_config_sfi(phy, params); in bnx2x_warpcore_config_init()
4524 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); in bnx2x_warpcore_config_init()
4527 bnx2x_sfp_module_detection(phy, params); in bnx2x_warpcore_config_init()
4531 bnx2x_warpcore_enable_AN_KR(phy, params, vars); in bnx2x_warpcore_config_init()
4534 bnx2x_warpcore_set_20G_force_KR2(phy, params); in bnx2x_warpcore_config_init()
4546 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_init()
4550 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, in bnx2x_warpcore_link_reset() argument
4555 bnx2x_sfp_e3_set_transmitter(params, phy, 0); in bnx2x_warpcore_link_reset()
4557 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_link_reset()
4559 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_link_reset()
4563 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4566 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4570 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_link_reset()
4573 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4577 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4579 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_link_reset()
4581 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4584 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_warpcore_link_reset()
4586 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4589 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4593 if (phy->flags & FLAGS_WC_DUAL_MODE) { in bnx2x_warpcore_link_reset()
4598 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4601 bnx2x_set_aer_mmd(params, phy); in bnx2x_warpcore_link_reset()
4605 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, in bnx2x_set_warpcore_loopback() argument
4612 params->loopback_mode, phy->req_line_speed); in bnx2x_set_warpcore_loopback()
4614 if (phy->req_line_speed < SPEED_10000 || in bnx2x_set_warpcore_loopback()
4615 phy->supported & SUPPORTED_20000baseKR2_Full) { in bnx2x_set_warpcore_loopback()
4619 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_warpcore_loopback()
4622 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4626 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_set_warpcore_loopback()
4627 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4630 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_set_warpcore_loopback()
4632 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4637 bnx2x_set_aer_mmd(params, phy); in bnx2x_set_warpcore_loopback()
4640 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4643 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4787 params->phy[INT_PHY].media_type = in bnx2x_link_status_update()
4790 params->phy[EXT_PHY1].media_type = in bnx2x_link_status_update()
4793 params->phy[EXT_PHY2].media_type = in bnx2x_link_status_update()
4824 struct bnx2x_phy *phy) in bnx2x_set_master_ln() argument
4833 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4838 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4845 struct bnx2x_phy *phy, in bnx2x_reset_unicore() argument
4851 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4856 CL22_WR_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4869 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4889 struct bnx2x_phy *phy) in bnx2x_set_swap_lanes() argument
4905 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4912 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4918 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4924 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4930 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, in bnx2x_set_parallel_detection() argument
4935 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4939 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) in bnx2x_set_parallel_detection()
4944 phy->speed_cap_mask, control2); in bnx2x_set_parallel_detection()
4945 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4950 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && in bnx2x_set_parallel_detection()
4951 (phy->speed_cap_mask & in bnx2x_set_parallel_detection()
4955 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4960 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4969 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4975 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4983 static void bnx2x_set_autoneg(struct bnx2x_phy *phy, in bnx2x_set_autoneg() argument
4992 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5003 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5009 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5020 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5025 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5038 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5045 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5051 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5059 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5063 if (phy->speed_cap_mask & in bnx2x_set_autoneg()
5066 if (phy->speed_cap_mask & in bnx2x_set_autoneg()
5070 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5081 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5087 static void bnx2x_program_serdes(struct bnx2x_phy *phy, in bnx2x_program_serdes() argument
5095 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5101 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_program_serdes()
5103 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5110 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5130 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5136 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, in bnx2x_set_brcm_cl37_advertisement() argument
5143 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) in bnx2x_set_brcm_cl37_advertisement()
5145 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) in bnx2x_set_brcm_cl37_advertisement()
5147 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5151 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5156 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, in bnx2x_set_ieee_aneg_advertisement() argument
5164 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5167 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5172 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5177 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, in bnx2x_restart_autoneg() argument
5188 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5193 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5201 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5208 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5217 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, in bnx2x_initialize_sgmii_process() argument
5226 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5235 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5245 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5273 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_initialize_sgmii_process()
5276 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5283 bnx2x_restart_autoneg(phy, params, 0); in bnx2x_initialize_sgmii_process()
5289 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, in bnx2x_direct_parallel_detect_used() argument
5294 if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_direct_parallel_detect_used()
5296 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5300 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5310 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5323 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, in bnx2x_update_adv_fc() argument
5338 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5342 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5352 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5356 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5370 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, in bnx2x_flow_ctrl_resolve() argument
5379 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { in bnx2x_flow_ctrl_resolve()
5381 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_flow_ctrl_resolve()
5382 bnx2x_update_adv_fc(phy, params, vars, gp_status); in bnx2x_flow_ctrl_resolve()
5384 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_flow_ctrl_resolve()
5385 } else if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_flow_ctrl_resolve()
5389 if (bnx2x_direct_parallel_detect_used(phy, params)) { in bnx2x_flow_ctrl_resolve()
5393 bnx2x_update_adv_fc(phy, params, vars, gp_status); in bnx2x_flow_ctrl_resolve()
5398 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, in bnx2x_check_fallback_to_cl37() argument
5405 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5413 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5420 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5436 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5457 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5462 bnx2x_restart_autoneg(phy, params, 0); in bnx2x_check_fallback_to_cl37()
5466 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, in bnx2x_xgxs_an_resolve() argument
5475 if (bnx2x_direct_parallel_detect_used(phy, params)) in bnx2x_xgxs_an_resolve()
5479 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, in bnx2x_get_link_speed_duplex() argument
5487 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_get_link_speed_duplex()
5570 static int bnx2x_link_settings_status(struct bnx2x_phy *phy, in bnx2x_link_settings_status() argument
5580 CL22_RD_OVER_CL45(bp, phy, in bnx2x_link_settings_status()
5591 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, in bnx2x_link_settings_status()
5599 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); in bnx2x_link_settings_status()
5600 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_link_settings_status()
5601 bnx2x_xgxs_an_resolve(phy, params, vars, in bnx2x_link_settings_status()
5605 if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_link_settings_status()
5608 bnx2x_check_fallback_to_cl37(phy, params); in bnx2x_link_settings_status()
5617 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, in bnx2x_link_settings_status()
5628 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, in bnx2x_link_settings_status()
5644 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, in bnx2x_warpcore_read_status() argument
5652 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_read_status()
5655 (phy->flags & FLAGS_WC_DUAL_MODE)) { in bnx2x_warpcore_read_status()
5656 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5658 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5661 } else if ((phy->req_line_speed > SPEED_10000) && in bnx2x_warpcore_read_status()
5662 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { in bnx2x_warpcore_read_status()
5664 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5666 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5672 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_warpcore_read_status()
5674 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5683 if (phy->supported & SUPPORTED_20000baseKR2_Full) { in bnx2x_warpcore_read_status()
5685 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5687 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5693 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_warpcore_read_status()
5695 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5703 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5710 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_warpcore_read_status()
5719 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5730 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5744 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5747 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5757 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, in bnx2x_warpcore_read_status()
5767 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_set_gmii_tx_driver() local
5773 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5787 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5796 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5850 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, in bnx2x_set_preemphasis() argument
5859 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5862 phy->rx_preemphasis[i]); in bnx2x_set_preemphasis()
5867 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5870 phy->tx_preemphasis[i]); in bnx2x_set_preemphasis()
5874 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, in bnx2x_xgxs_config_init() argument
5885 bnx2x_set_preemphasis(phy, params); in bnx2x_xgxs_config_init()
5894 bnx2x_set_autoneg(phy, params, vars, 0); in bnx2x_xgxs_config_init()
5897 bnx2x_program_serdes(phy, params, vars); in bnx2x_xgxs_config_init()
5903 bnx2x_set_brcm_cl37_advertisement(phy, params); in bnx2x_xgxs_config_init()
5906 bnx2x_set_ieee_aneg_advertisement(phy, params, in bnx2x_xgxs_config_init()
5910 bnx2x_set_autoneg(phy, params, vars, enable_cl73); in bnx2x_xgxs_config_init()
5913 bnx2x_restart_autoneg(phy, params, enable_cl73); in bnx2x_xgxs_config_init()
5919 bnx2x_initialize_sgmii_process(phy, params, vars); in bnx2x_xgxs_config_init()
5923 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, in bnx2x_prepare_xgxs() argument
5929 if ((phy->req_line_speed && in bnx2x_prepare_xgxs()
5930 ((phy->req_line_speed == SPEED_100) || in bnx2x_prepare_xgxs()
5931 (phy->req_line_speed == SPEED_10))) || in bnx2x_prepare_xgxs()
5932 (!phy->req_line_speed && in bnx2x_prepare_xgxs()
5933 (phy->speed_cap_mask >= in bnx2x_prepare_xgxs()
5935 (phy->speed_cap_mask < in bnx2x_prepare_xgxs()
5937 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) in bnx2x_prepare_xgxs()
5942 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_prepare_xgxs()
5943 bnx2x_set_aer_mmd(params, phy); in bnx2x_prepare_xgxs()
5944 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_prepare_xgxs()
5945 bnx2x_set_master_ln(params, phy); in bnx2x_prepare_xgxs()
5947 rc = bnx2x_reset_unicore(params, phy, 0); in bnx2x_prepare_xgxs()
5952 bnx2x_set_aer_mmd(params, phy); in bnx2x_prepare_xgxs()
5954 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { in bnx2x_prepare_xgxs()
5955 bnx2x_set_master_ln(params, phy); in bnx2x_prepare_xgxs()
5956 bnx2x_set_swap_lanes(params, phy); in bnx2x_prepare_xgxs()
5963 struct bnx2x_phy *phy, in bnx2x_wait_reset_complete() argument
5969 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) in bnx2x_wait_reset_complete()
5970 bnx2x_cl22_read(bp, phy, in bnx2x_wait_reset_complete()
5973 bnx2x_cl45_read(bp, phy, in bnx2x_wait_reset_complete()
6005 params->phy[INT_PHY].type != in bnx2x_link_int_enable()
6015 params->phy[INT_PHY].type != in bnx2x_link_int_enable()
6171 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); in bnx2x_get_ext_phy_fw_version()
6173 if (params->phy[EXT_PHY1].format_fw_ver) { in bnx2x_get_ext_phy_fw_version()
6174 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, in bnx2x_get_ext_phy_fw_version()
6180 (params->phy[EXT_PHY2].ver_addr != 0)) { in bnx2x_get_ext_phy_fw_version()
6181 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); in bnx2x_get_ext_phy_fw_version()
6182 if (params->phy[EXT_PHY2].format_fw_ver) { in bnx2x_get_ext_phy_fw_version()
6186 status |= params->phy[EXT_PHY2].format_fw_ver( in bnx2x_get_ext_phy_fw_version()
6197 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, in bnx2x_set_xgxs_loopback() argument
6203 if (phy->req_line_speed != SPEED_1000) { in bnx2x_set_xgxs_loopback()
6217 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6223 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6230 bnx2x_set_aer_mmd(params, phy); in bnx2x_set_xgxs_loopback()
6240 bnx2x_cl45_read(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6244 bnx2x_cl45_write(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6267 if (params->phy[phy_idx].set_link_led) { in bnx2x_set_led()
6268 params->phy[phy_idx].set_link_led( in bnx2x_set_led()
6269 ¶ms->phy[phy_idx], params, mode); in bnx2x_set_led()
6281 if (params->phy[EXT_PHY1].type == in bnx2x_set_led()
6299 if (((params->phy[EXT_PHY1].type == in bnx2x_set_led()
6301 (params->phy[EXT_PHY1].type == in bnx2x_set_led()
6337 } else if ((params->phy[EXT_PHY1].type == in bnx2x_set_led()
6401 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; in bnx2x_test_link()
6443 ext_phy_link_up = params->phy[EXT_PHY1].read_status( in bnx2x_test_link()
6444 ¶ms->phy[EXT_PHY1], in bnx2x_test_link()
6450 serdes_phy_type = ((params->phy[phy_index].media_type == in bnx2x_test_link()
6452 (params->phy[phy_index].media_type == in bnx2x_test_link()
6454 (params->phy[phy_index].media_type == in bnx2x_test_link()
6456 (params->phy[phy_index].media_type == in bnx2x_test_link()
6461 if (params->phy[phy_index].read_status) { in bnx2x_test_link()
6463 params->phy[phy_index].read_status( in bnx2x_test_link()
6464 ¶ms->phy[phy_index], in bnx2x_test_link()
6486 vars->line_speed = params->phy[INT_PHY].req_line_speed; in bnx2x_link_initialize()
6493 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); in bnx2x_link_initialize()
6499 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || in bnx2x_link_initialize()
6501 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_link_initialize() local
6505 bnx2x_set_parallel_detection(phy, params); in bnx2x_link_initialize()
6506 if (params->phy[INT_PHY].config_init) in bnx2x_link_initialize()
6507 params->phy[INT_PHY].config_init(phy, in bnx2x_link_initialize()
6514 if (params->phy[INT_PHY].supported & in bnx2x_link_initialize()
6525 if (params->phy[phy_index].supported & in bnx2x_link_initialize()
6536 params->phy[phy_index].config_init( in bnx2x_link_initialize()
6537 ¶ms->phy[phy_index], in bnx2x_link_initialize()
6551 static void bnx2x_int_link_reset(struct bnx2x_phy *phy, in bnx2x_int_link_reset() argument
6559 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, in bnx2x_common_ext_link_reset() argument
6707 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { in bnx2x_update_link_up()
6754 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); in bnx2x_link_update()
6784 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; in bnx2x_link_update() local
6785 if (!phy->read_status) in bnx2x_link_update()
6788 cur_link_up = phy->read_status(phy, params, in bnx2x_link_update()
6842 if (params->phy[INT_PHY].read_status) in bnx2x_link_update()
6843 params->phy[INT_PHY].read_status( in bnx2x_link_update()
6844 ¶ms->phy[INT_PHY], in bnx2x_link_update()
6864 if (params->phy[EXT_PHY2].phy_specific_func) { in bnx2x_link_update()
6867 params->phy[EXT_PHY2].phy_specific_func( in bnx2x_link_update()
6868 ¶ms->phy[EXT_PHY2], in bnx2x_link_update()
6875 if (params->phy[active_external_phy].supported & in bnx2x_link_update()
6889 if (params->phy[phy_index].flags & in bnx2x_link_update()
6936 params->phy[EXT_PHY1].flags & in bnx2x_link_update()
6938 if (!(params->phy[EXT_PHY1].flags & in bnx2x_link_update()
6947 if (params->phy[INT_PHY].config_init) in bnx2x_link_update()
6948 params->phy[INT_PHY].config_init( in bnx2x_link_update()
6949 ¶ms->phy[INT_PHY], params, in bnx2x_link_update()
7002 struct bnx2x_phy *phy, in bnx2x_save_bcm_spirom_ver() argument
7007 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7009 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7012 phy->ver_addr); in bnx2x_save_bcm_spirom_ver()
7016 struct bnx2x_phy *phy, in bnx2x_ext_phy_10G_an_resolve() argument
7020 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7023 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7035 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, in bnx2x_8073_resolve_fc() argument
7040 if (phy->req_line_speed == SPEED_10 || in bnx2x_8073_resolve_fc()
7041 phy->req_line_speed == SPEED_100) { in bnx2x_8073_resolve_fc()
7042 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_8073_resolve_fc()
7046 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && in bnx2x_8073_resolve_fc()
7051 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7055 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7069 struct bnx2x_phy *phy, in bnx2x_8073_8727_external_rom_boot() argument
7078 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7084 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7089 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7094 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7100 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7120 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7123 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7129 ((fw_msgout & 0xff) != 0x03 && (phy->type == in bnx2x_8073_8727_external_rom_boot()
7133 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7136 bnx2x_save_bcm_spirom_ver(bp, phy, port); in bnx2x_8073_8727_external_rom_boot()
7149 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_is_snr_needed() argument
7155 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7164 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7175 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_xaui_wa() argument
7179 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7194 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7213 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7231 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_807x_force_10G() argument
7234 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7236 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7238 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7240 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7245 struct bnx2x_phy *phy, in bnx2x_8073_set_pause_cl37() argument
7250 bnx2x_cl45_read(bp, phy, in bnx2x_8073_set_pause_cl37()
7255 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_8073_set_pause_cl37()
7274 bnx2x_cl45_write(bp, phy, in bnx2x_8073_set_pause_cl37()
7279 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, in bnx2x_8073_specific_func() argument
7287 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7289 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7295 static int bnx2x_8073_config_init(struct bnx2x_phy *phy, in bnx2x_8073_config_init() argument
7315 bnx2x_8073_specific_func(phy, params, PHY_INIT); in bnx2x_8073_config_init()
7316 bnx2x_8073_set_pause_cl37(params, phy, vars); in bnx2x_8073_config_init()
7318 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7321 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7331 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7334 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7347 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7350 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7356 bnx2x_807x_force_10G(bp, phy); in bnx2x_8073_config_init()
7360 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7363 if (phy->req_line_speed != SPEED_AUTO_NEG) { in bnx2x_8073_config_init()
7364 if (phy->req_line_speed == SPEED_10000) { in bnx2x_8073_config_init()
7366 } else if (phy->req_line_speed == SPEED_2500) { in bnx2x_8073_config_init()
7375 if (phy->speed_cap_mask & in bnx2x_8073_config_init()
7380 if (phy->speed_cap_mask & in bnx2x_8073_config_init()
7387 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); in bnx2x_8073_config_init()
7388 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); in bnx2x_8073_config_init()
7390 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && in bnx2x_8073_config_init()
7391 (phy->req_line_speed == SPEED_AUTO_NEG)) || in bnx2x_8073_config_init()
7392 (phy->req_line_speed == SPEED_2500)) { in bnx2x_8073_config_init()
7395 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7408 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); in bnx2x_8073_config_init()
7411 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); in bnx2x_8073_config_init()
7412 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, in bnx2x_8073_config_init()
7413 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? in bnx2x_8073_config_init()
7417 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in bnx2x_8073_config_init()
7423 if (bnx2x_8073_is_snr_needed(bp, phy)) in bnx2x_8073_config_init()
7424 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7429 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); in bnx2x_8073_config_init()
7431 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); in bnx2x_8073_config_init()
7433 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_8073_config_init()
7437 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in bnx2x_8073_config_init()
7443 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, in bnx2x_8073_read_status() argument
7453 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7459 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7461 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7465 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7469 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7475 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7479 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7481 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7487 ((phy->req_line_speed != SPEED_10000))) { in bnx2x_8073_read_status()
7488 if (bnx2x_8073_xaui_wa(bp, phy) != 0) in bnx2x_8073_read_status()
7491 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7493 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7497 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7499 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7505 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { in bnx2x_8073_read_status()
7510 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7515 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7519 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7550 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7563 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7568 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_8073_read_status()
7569 bnx2x_8073_resolve_fc(phy, params, vars); in bnx2x_8073_read_status()
7574 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_8073_read_status()
7588 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, in bnx2x_8073_link_reset() argument
7607 static int bnx2x_8705_config_init(struct bnx2x_phy *phy, in bnx2x_8705_config_init() argument
7618 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8705_config_init()
7619 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8705_config_init()
7621 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7623 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7625 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7627 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7634 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, in bnx2x_8705_read_status() argument
7642 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7646 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7650 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7653 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7655 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7662 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_8705_read_status()
7671 struct bnx2x_phy *phy, in bnx2x_set_disable_pmd_transmit() argument
7688 bnx2x_cl45_write(bp, phy, in bnx2x_set_disable_pmd_transmit()
7708 struct bnx2x_phy *phy, in bnx2x_sfp_e1e2_set_transmitter() argument
7726 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7736 bnx2x_cl45_write(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7765 struct bnx2x_phy *phy, in bnx2x_sfp_set_transmitter() argument
7771 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); in bnx2x_sfp_set_transmitter()
7773 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); in bnx2x_sfp_set_transmitter()
7776 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_8726_read_sfp_module_eeprom() argument
7790 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7795 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7800 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7806 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7825 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7832 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7864 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_warpcore_read_sfp_module_eeprom() argument
7891 rc = bnx2x_bsc_read(params, phy, dev_addr, addr32, 0, byte_cnt, in bnx2x_warpcore_read_sfp_module_eeprom()
7905 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_8727_read_sfp_module_eeprom() argument
7923 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7929 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7935 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7941 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7946 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7952 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7963 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7982 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7989 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8000 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, in bnx2x_read_sfp_module_eeprom() argument
8015 switch (phy->type) { in bnx2x_read_sfp_module_eeprom()
8033 rc = read_func(phy, params, dev_addr, addr, xfer_size, in bnx2x_read_sfp_module_eeprom()
8042 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, in bnx2x_get_edc_mode() argument
8050 phy->media_type = ETH_PHY_UNSPECIFIED; in bnx2x_get_edc_mode()
8052 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_get_edc_mode()
8066 phy->media_type = ETH_PHY_DA_TWINAX; in bnx2x_get_edc_mode()
8070 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_get_edc_mode()
8108 phy->media_type = ETH_PHY_SFP_1G_FIBER; in bnx2x_get_edc_mode()
8109 if (phy->req_line_speed != SPEED_1000) { in bnx2x_get_edc_mode()
8110 phy->req_line_speed = SPEED_1000; in bnx2x_get_edc_mode()
8123 if (params->phy[idx].type == phy->type) { in bnx2x_get_edc_mode()
8128 phy->media_type = ETH_PHY_SFPP_10G_FIBER; in bnx2x_get_edc_mode()
8129 phy->req_line_speed = params->req_line_speed[cfg_idx]; in bnx2x_get_edc_mode()
8143 if (&(params->phy[phy_idx]) == phy) { in bnx2x_get_edc_mode()
8146 media_types |= ((phy->media_type & in bnx2x_get_edc_mode()
8155 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_get_edc_mode()
8176 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, in bnx2x_verify_sfp_module() argument
8184 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; in bnx2x_verify_sfp_module()
8214 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); in bnx2x_verify_sfp_module()
8222 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_verify_sfp_module()
8231 if (bnx2x_read_sfp_module_eeprom(phy, in bnx2x_verify_sfp_module()
8246 phy->flags |= FLAGS_SFP_NOT_APPROVED; in bnx2x_verify_sfp_module()
8250 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, in bnx2x_wait_for_sfp_module_initialized() argument
8263 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_wait_for_sfp_module_initialized()
8265 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, in bnx2x_wait_for_sfp_module_initialized()
8268 rc = bnx2x_read_sfp_module_eeprom(phy, params, in bnx2x_wait_for_sfp_module_initialized()
8279 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0, in bnx2x_wait_for_sfp_module_initialized()
8285 struct bnx2x_phy *phy, in bnx2x_8727_power_module() argument
8300 if (phy->flags & FLAGS_NOC) in bnx2x_8727_power_module()
8310 bnx2x_cl45_write(bp, phy, in bnx2x_8727_power_module()
8317 struct bnx2x_phy *phy, in bnx2x_8726_set_limiting_mode() argument
8322 bnx2x_cl45_read(bp, phy, in bnx2x_8726_set_limiting_mode()
8331 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8345 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8349 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8353 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8357 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8366 struct bnx2x_phy *phy, in bnx2x_8727_set_limiting_mode() argument
8371 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8376 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8381 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8386 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8391 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8399 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, in bnx2x_8727_specific_func() argument
8407 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_specific_func()
8410 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) in bnx2x_8727_specific_func()
8411 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_8727_specific_func()
8414 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8417 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8420 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8423 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_specific_func()
8427 if (phy->flags & FLAGS_NOC) in bnx2x_8727_specific_func()
8432 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_specific_func()
8434 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8507 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, in bnx2x_warpcore_hw_reset() argument
8522 struct bnx2x_phy *phy, in bnx2x_power_sfp_module() argument
8528 switch (phy->type) { in bnx2x_power_sfp_module()
8531 bnx2x_8727_power_module(params->bp, phy, power); in bnx2x_power_sfp_module()
8541 struct bnx2x_phy *phy, in bnx2x_warpcore_set_limiting_mode() argument
8548 u8 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_set_limiting_mode()
8550 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8567 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8570 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8574 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_set_limiting_mode()
8575 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_set_limiting_mode()
8580 struct bnx2x_phy *phy, in bnx2x_set_limiting_mode() argument
8583 switch (phy->type) { in bnx2x_set_limiting_mode()
8585 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8589 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8592 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); in bnx2x_set_limiting_mode()
8597 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, in bnx2x_sfp_module_detection() argument
8608 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_sfp_module_detection()
8612 bnx2x_power_sfp_module(params, phy, 1); in bnx2x_sfp_module_detection()
8613 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { in bnx2x_sfp_module_detection()
8616 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { in bnx2x_sfp_module_detection()
8628 bnx2x_power_sfp_module(params, phy, 0); in bnx2x_sfp_module_detection()
8639 bnx2x_set_limiting_mode(params, phy, edc_mode); in bnx2x_sfp_module_detection()
8647 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_sfp_module_detection()
8655 struct bnx2x_phy *phy; in bnx2x_handle_module_detect_int() local
8659 phy = ¶ms->phy[INT_PHY]; in bnx2x_handle_module_detect_int()
8661 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_handle_module_detect_int()
8663 phy = ¶ms->phy[EXT_PHY1]; in bnx2x_handle_module_detect_int()
8681 bnx2x_set_aer_mmd(params, phy); in bnx2x_handle_module_detect_int()
8683 bnx2x_power_sfp_module(params, phy, 1); in bnx2x_handle_module_detect_int()
8687 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { in bnx2x_handle_module_detect_int()
8688 bnx2x_sfp_module_detection(phy, params); in bnx2x_handle_module_detect_int()
8695 bnx2x_cl45_read(bp, phy, in bnx2x_handle_module_detect_int()
8702 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_handle_module_detect_int()
8703 bnx2x_warpcore_config_sfi(phy, params); in bnx2x_handle_module_detect_int()
8704 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_handle_module_detect_int()
8717 phy->media_type = ETH_PHY_NOT_PRESENT; in bnx2x_handle_module_detect_int()
8725 struct bnx2x_phy *phy, in bnx2x_sfp_mask_fault() argument
8730 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8733 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8737 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); in bnx2x_sfp_mask_fault()
8742 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); in bnx2x_sfp_mask_fault()
8747 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, in bnx2x_8706_8726_read_status() argument
8756 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8759 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8706_8726_read_status()
8763 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8765 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8769 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8771 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8773 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8775 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8789 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_8706_8726_read_status()
8795 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8797 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8809 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, in bnx2x_8706_config_init() argument
8821 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8706_config_init()
8822 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8706_config_init()
8826 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8841 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); in bnx2x_8706_config_init()
8845 val |= (phy->rx_preemphasis[i] & 0x7); in bnx2x_8706_config_init()
8848 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); in bnx2x_8706_config_init()
8852 if (phy->req_line_speed == SPEED_10000) { in bnx2x_8706_config_init()
8855 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8858 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8862 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8869 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8873 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8876 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8879 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8883 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8885 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8888 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8892 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8706_config_init()
8905 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8908 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8915 static int bnx2x_8706_read_status(struct bnx2x_phy *phy, in bnx2x_8706_read_status() argument
8919 return bnx2x_8706_8726_read_status(phy, params, vars); in bnx2x_8706_read_status()
8925 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, in bnx2x_8726_config_loopback() argument
8930 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); in bnx2x_8726_config_loopback()
8933 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, in bnx2x_8726_external_rom_boot() argument
8941 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8945 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8950 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8954 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8963 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
8968 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8726_external_rom_boot()
8971 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, in bnx2x_8726_read_status() argument
8977 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); in bnx2x_8726_read_status()
8979 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_status()
8992 static int bnx2x_8726_config_init(struct bnx2x_phy *phy, in bnx2x_8726_config_init() argument
8999 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8726_config_init()
9000 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8726_config_init()
9002 bnx2x_8726_external_rom_boot(phy, params); in bnx2x_8726_config_init()
9009 bnx2x_sfp_module_detection(phy, params); in bnx2x_8726_config_init()
9011 if (phy->req_line_speed == SPEED_1000) { in bnx2x_8726_config_init()
9013 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9015 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9017 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9019 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9022 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_8726_config_init()
9023 (phy->speed_cap_mask & in bnx2x_8726_config_init()
9025 ((phy->speed_cap_mask & in bnx2x_8726_config_init()
9030 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_8726_config_init()
9031 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9033 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9035 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9037 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9039 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9044 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9046 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9051 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9060 phy->tx_preemphasis[0], in bnx2x_8726_config_init()
9061 phy->tx_preemphasis[1]); in bnx2x_8726_config_init()
9062 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9065 phy->tx_preemphasis[0]); in bnx2x_8726_config_init()
9067 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9070 phy->tx_preemphasis[1]); in bnx2x_8726_config_init()
9077 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, in bnx2x_8726_link_reset() argument
9083 bnx2x_cl45_write(bp, phy, in bnx2x_8726_link_reset()
9092 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, in bnx2x_8727_set_link_led() argument
9100 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_set_link_led()
9117 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9123 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9127 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9133 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9138 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, in bnx2x_8727_hw_reset() argument
9153 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, in bnx2x_8727_config_speed() argument
9159 if ((phy->req_line_speed == SPEED_1000) || in bnx2x_8727_config_speed()
9160 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { in bnx2x_8727_config_speed()
9162 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9164 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9166 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9173 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9177 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9181 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_8727_config_speed()
9182 ((phy->speed_cap_mask & in bnx2x_8727_config_speed()
9184 ((phy->speed_cap_mask & in bnx2x_8727_config_speed()
9189 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9191 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9197 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9200 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9202 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9204 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9210 static int bnx2x_8727_config_init(struct bnx2x_phy *phy, in bnx2x_8727_config_init() argument
9219 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8727_config_init()
9223 bnx2x_8727_specific_func(phy, params, PHY_INIT); in bnx2x_8727_config_init()
9227 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9234 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_config_init()
9236 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9240 bnx2x_set_disable_pmd_transmit(params, phy, 0); in bnx2x_8727_config_init()
9242 bnx2x_8727_power_module(bp, phy, 1); in bnx2x_8727_config_init()
9244 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9247 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9250 bnx2x_8727_config_speed(phy, params); in bnx2x_8727_config_init()
9257 phy->tx_preemphasis[0], in bnx2x_8727_config_init()
9258 phy->tx_preemphasis[1]); in bnx2x_8727_config_init()
9259 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9261 phy->tx_preemphasis[0]); in bnx2x_8727_config_init()
9263 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9265 phy->tx_preemphasis[1]); in bnx2x_8727_config_init()
9279 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9283 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9285 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9288 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9296 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, in bnx2x_8727_handle_mod_abs() argument
9305 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9313 phy->media_type = ETH_PHY_NOT_PRESENT; in bnx2x_8727_handle_mod_abs()
9322 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_handle_mod_abs()
9324 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9331 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9347 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_handle_mod_abs()
9349 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9358 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9365 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_handle_mod_abs()
9367 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) in bnx2x_8727_handle_mod_abs()
9368 bnx2x_sfp_module_detection(phy, params); in bnx2x_8727_handle_mod_abs()
9373 bnx2x_8727_config_speed(phy, params); in bnx2x_8727_handle_mod_abs()
9381 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, in bnx2x_8727_read_status() argument
9392 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9399 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9405 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8727_read_status()
9408 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9414 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9420 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { in bnx2x_8727_read_status()
9422 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9441 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9445 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9450 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9454 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9457 bnx2x_8727_power_module(params->bp, phy, 0); in bnx2x_8727_read_status()
9464 bnx2x_8727_handle_mod_abs(phy, params); in bnx2x_8727_read_status()
9466 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9471 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { in bnx2x_8727_read_status()
9473 bnx2x_sfp_set_transmitter(params, phy, 1); in bnx2x_8727_read_status()
9479 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9504 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9507 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9516 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_8727_read_status()
9522 (phy->req_line_speed == SPEED_1000)) { in bnx2x_8727_read_status()
9523 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9533 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9540 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, in bnx2x_8727_link_reset() argument
9546 bnx2x_set_disable_pmd_transmit(params, phy, 1); in bnx2x_8727_link_reset()
9549 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_link_reset()
9551 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); in bnx2x_8727_link_reset()
9558 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, in bnx2x_save_848xx_spirom_version() argument
9572 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_save_848xx_spirom_version()
9573 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_save_848xx_spirom_version()
9574 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9576 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9581 bnx2x_cl45_write(bp, phy, reg_set[i].devad, in bnx2x_save_848xx_spirom_version()
9585 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9594 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9600 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); in bnx2x_save_848xx_spirom_version()
9601 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); in bnx2x_save_848xx_spirom_version()
9602 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); in bnx2x_save_848xx_spirom_version()
9604 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9613 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9618 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9620 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); in bnx2x_save_848xx_spirom_version()
9623 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9628 struct bnx2x_phy *phy) in bnx2x_848xx_set_led() argument
9641 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_led()
9647 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_led()
9652 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_848xx_set_led()
9655 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_848xx_set_led()
9656 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) in bnx2x_848xx_set_led()
9662 bnx2x_cl45_read_or_write(bp, phy, in bnx2x_848xx_set_led()
9667 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, in bnx2x_848xx_specific_func() argument
9674 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && in bnx2x_848xx_specific_func()
9675 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_848xx_specific_func()
9677 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848xx_specific_func()
9686 bnx2x_848xx_set_led(bp, phy); in bnx2x_848xx_specific_func()
9691 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, in bnx2x_848xx_cmn_config_init() argument
9698 bnx2x_848xx_specific_func(phy, params, PHY_INIT); in bnx2x_848xx_cmn_config_init()
9699 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9703 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9707 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_848xx_cmn_config_init()
9708 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9712 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9719 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9720 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9722 (phy->req_line_speed == SPEED_1000)) { in bnx2x_848xx_cmn_config_init()
9725 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9731 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9736 if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9737 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9744 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9749 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9750 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9753 (phy->supported & in bnx2x_848xx_cmn_config_init()
9758 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9764 if ((phy->req_line_speed == SPEED_100) && in bnx2x_848xx_cmn_config_init()
9765 (phy->supported & in bnx2x_848xx_cmn_config_init()
9770 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9777 if ((phy->req_line_speed == SPEED_10) && in bnx2x_848xx_cmn_config_init()
9778 (phy->supported & in bnx2x_848xx_cmn_config_init()
9782 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9788 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9792 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9798 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && in bnx2x_848xx_cmn_config_init()
9799 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || in bnx2x_848xx_cmn_config_init()
9801 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9805 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9806 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9808 (phy->req_line_speed == SPEED_10000)) { in bnx2x_848xx_cmn_config_init()
9813 bp, phy, in bnx2x_848xx_cmn_config_init()
9817 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9821 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9829 static int bnx2x_8481_config_init(struct bnx2x_phy *phy, in bnx2x_8481_config_init() argument
9840 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8481_config_init()
9842 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8481_config_init()
9843 return bnx2x_848xx_cmn_config_init(phy, params, vars); in bnx2x_8481_config_init()
9848 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, in bnx2x_84833_cmd_hdlr() argument
9856 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9860 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9873 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9877 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9880 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9894 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9898 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9904 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, in bnx2x_84833_pair_swap_cfg() argument
9925 status = bnx2x_84833_cmd_hdlr(phy, params, in bnx2x_84833_pair_swap_cfg()
9971 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, in bnx2x_84833_hw_reset_phy() argument
9983 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
9986 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10004 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, in bnx2x_8483x_disable_eee() argument
10015 rc = bnx2x_84833_cmd_hdlr(phy, params, in bnx2x_8483x_disable_eee()
10022 return bnx2x_eee_disable(phy, params, vars); in bnx2x_8483x_disable_eee()
10025 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, in bnx2x_8483x_enable_eee() argument
10033 rc = bnx2x_84833_cmd_hdlr(phy, params, in bnx2x_8483x_enable_eee()
10040 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); in bnx2x_8483x_enable_eee()
10044 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, in bnx2x_848x3_config_init() argument
10062 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_config_init()
10068 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_config_init()
10073 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_848x3_config_init()
10077 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && in bnx2x_848x3_config_init()
10078 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_848x3_config_init()
10085 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); in bnx2x_848x3_config_init()
10086 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); in bnx2x_848x3_config_init()
10090 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10126 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) in bnx2x_848x3_config_init()
10129 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10134 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_848x3_config_init()
10135 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_848x3_config_init()
10136 bnx2x_84833_pair_swap_cfg(phy, params, vars); in bnx2x_848x3_config_init()
10143 rc = bnx2x_84833_cmd_hdlr(phy, params, in bnx2x_848x3_config_init()
10150 rc = bnx2x_848xx_cmn_config_init(phy, params, vars); in bnx2x_848x3_config_init()
10152 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848x3_config_init()
10154 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_config_init()
10160 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10166 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10170 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10180 bnx2x_8483x_disable_eee(phy, params, vars); in bnx2x_848x3_config_init()
10184 if ((phy->req_duplex == DUPLEX_FULL) && in bnx2x_848x3_config_init()
10188 rc = bnx2x_8483x_enable_eee(phy, params, vars); in bnx2x_848x3_config_init()
10190 rc = bnx2x_8483x_disable_eee(phy, params, vars); in bnx2x_848x3_config_init()
10199 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_848x3_config_init()
10200 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { in bnx2x_848x3_config_init()
10202 bnx2x_cl45_read_and_write(bp, phy, in bnx2x_848x3_config_init()
10210 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, in bnx2x_848xx_read_status() argument
10221 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10223 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10233 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_848xx_read_status()
10238 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_read_status()
10243 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10274 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10281 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10293 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_848xx_read_status()
10296 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10314 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10324 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10332 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_848xx_read_status()
10333 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) in bnx2x_848xx_read_status()
10334 bnx2x_eee_an_resolve(phy, params, vars); in bnx2x_848xx_read_status()
10349 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, in bnx2x_8481_hw_reset() argument
10358 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, in bnx2x_8481_link_reset() argument
10361 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10363 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10367 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, in bnx2x_848x3_link_reset() argument
10379 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_link_reset()
10384 bnx2x_cl45_read(bp, phy, in bnx2x_848x3_link_reset()
10388 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_link_reset()
10394 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, in bnx2x_848xx_set_link_led() argument
10415 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10420 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10425 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10430 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10436 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10451 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10456 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10461 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10466 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10472 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10476 if (phy->type == in bnx2x_848xx_set_link_led()
10493 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10507 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10514 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10520 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10525 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10530 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10535 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10540 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10544 if (phy->type == in bnx2x_848xx_set_link_led()
10561 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10577 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10586 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10593 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10598 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10603 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10608 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10614 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10620 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10626 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10630 if (phy->type == in bnx2x_848xx_set_link_led()
10635 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10654 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_848xx_set_link_led()
10662 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, in bnx2x_54618se_specific_func() argument
10672 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10675 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_specific_func()
10680 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10684 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10691 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, in bnx2x_54618se_config_init() argument
10721 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10723 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_54618se_config_init()
10729 bnx2x_54618se_specific_func(phy, params, PHY_INIT); in bnx2x_54618se_config_init()
10731 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10734 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10738 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10744 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_54618se_config_init()
10755 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10759 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10763 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10772 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_54618se_config_init()
10773 (phy->speed_cap_mask & in bnx2x_54618se_config_init()
10775 (phy->req_line_speed == SPEED_1000)) { in bnx2x_54618se_config_init()
10778 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
10784 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10787 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10792 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_54618se_config_init()
10793 (phy->speed_cap_mask & in bnx2x_54618se_config_init()
10800 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
10806 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_54618se_config_init()
10807 (phy->speed_cap_mask & in bnx2x_54618se_config_init()
10812 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
10818 if (phy->req_line_speed == SPEED_100) { in bnx2x_54618se_config_init()
10821 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10826 if (phy->req_line_speed == SPEED_10) { in bnx2x_54618se_config_init()
10828 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10834 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { in bnx2x_54618se_config_init()
10837 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, in bnx2x_54618se_config_init()
10840 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); in bnx2x_54618se_config_init()
10842 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); in bnx2x_54618se_config_init()
10847 bnx2x_eee_disable(phy, params, vars); in bnx2x_54618se_config_init()
10849 (phy->req_duplex == DUPLEX_FULL) && in bnx2x_54618se_config_init()
10857 bnx2x_eee_advertise(phy, params, vars, in bnx2x_54618se_config_init()
10861 bnx2x_eee_disable(phy, params, vars); in bnx2x_54618se_config_init()
10867 if (phy->flags & FLAGS_EEE) { in bnx2x_54618se_config_init()
10877 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_54618se_config_init()
10882 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10886 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
10889 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10896 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, in bnx2x_5461x_set_link_led() argument
10902 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
10905 bnx2x_cl22_read(bp, phy, in bnx2x_5461x_set_link_led()
10925 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
10932 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, in bnx2x_54618se_link_reset() argument
10942 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); in bnx2x_54618se_link_reset()
10957 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, in bnx2x_54618se_read_status() argument
10967 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
10973 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11010 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11016 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11026 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_54618se_read_status()
11030 bnx2x_cl22_read(bp, phy, 0x5, &val); in bnx2x_54618se_read_status()
11048 bnx2x_cl22_read(bp, phy, 0xa, &val); in bnx2x_54618se_read_status()
11056 if ((phy->flags & FLAGS_EEE) && in bnx2x_54618se_read_status()
11058 bnx2x_eee_an_resolve(phy, params, vars); in bnx2x_54618se_read_status()
11064 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, in bnx2x_54618se_config_loopback() argument
11075 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); in bnx2x_54618se_config_loopback()
11082 bnx2x_cl22_read(bp, phy, 0x00, &val); in bnx2x_54618se_config_loopback()
11085 bnx2x_cl22_write(bp, phy, 0x00, val); in bnx2x_54618se_config_loopback()
11091 bnx2x_cl22_write(bp, phy, 0x18, 7); in bnx2x_54618se_config_loopback()
11092 bnx2x_cl22_read(bp, phy, 0x18, &val); in bnx2x_54618se_config_loopback()
11093 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); in bnx2x_54618se_config_loopback()
11107 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, in bnx2x_7101_config_loopback() argument
11112 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_loopback()
11116 static int bnx2x_7101_config_init(struct bnx2x_phy *phy, in bnx2x_7101_config_init() argument
11129 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_7101_config_init()
11131 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11134 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11137 bnx2x_ext_phy_set_pause(params, phy, vars); in bnx2x_7101_config_init()
11139 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11142 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11146 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11149 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11152 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); in bnx2x_7101_config_init()
11156 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, in bnx2x_7101_read_status() argument
11163 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11165 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11169 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11171 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11178 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11185 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_7101_read_status()
11186 bnx2x_ext_phy_resolve_fc(phy, params, vars); in bnx2x_7101_read_status()
11209 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_sfx7101_sp_sw_reset() argument
11213 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11220 bnx2x_cl45_write(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11225 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11234 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, in bnx2x_7101_hw_reset() argument
11244 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, in bnx2x_7101_set_link_led() argument
11261 bnx2x_cl45_write(bp, phy, in bnx2x_7101_set_link_led()
11767 struct bnx2x_phy *phy, u8 port, in bnx2x_populate_preemphasis() argument
11795 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); in bnx2x_populate_preemphasis()
11796 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); in bnx2x_populate_preemphasis()
11798 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); in bnx2x_populate_preemphasis()
11799 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); in bnx2x_populate_preemphasis()
11826 struct bnx2x_phy *phy) in bnx2x_populate_int_phy() argument
11842 *phy = phy_warpcore; in bnx2x_populate_int_phy()
11844 phy->flags |= FLAGS_4_PORT_MODE; in bnx2x_populate_int_phy()
11846 phy->flags &= ~FLAGS_4_PORT_MODE; in bnx2x_populate_int_phy()
11857 phy->supported &= (SUPPORTED_10baseT_Half | in bnx2x_populate_int_phy()
11866 phy->media_type = ETH_PHY_BASE_T; in bnx2x_populate_int_phy()
11869 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
11874 phy->media_type = ETH_PHY_XFP_FIBER; in bnx2x_populate_int_phy()
11877 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
11882 phy->media_type = ETH_PHY_SFPP_10G_FIBER; in bnx2x_populate_int_phy()
11885 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
11886 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
11894 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
11895 phy->flags |= FLAGS_WC_DUAL_MODE; in bnx2x_populate_int_phy()
11896 phy->supported &= (SUPPORTED_20000baseMLD2_Full | in bnx2x_populate_int_phy()
11902 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
11903 phy->flags |= FLAGS_WC_DUAL_MODE; in bnx2x_populate_int_phy()
11904 phy->supported &= (SUPPORTED_20000baseKR2_Full | in bnx2x_populate_int_phy()
11911 phy->flags &= ~FLAGS_TX_ERROR_CHECK; in bnx2x_populate_int_phy()
11924 phy->flags |= FLAGS_MDC_MDIO_WA; in bnx2x_populate_int_phy()
11926 phy->flags |= FLAGS_MDC_MDIO_WA_B0; in bnx2x_populate_int_phy()
11933 *phy = phy_serdes; in bnx2x_populate_int_phy()
11939 *phy = phy_xgxs; in bnx2x_populate_int_phy()
11946 phy->addr = (u8)phy_addr; in bnx2x_populate_int_phy()
11947 phy->mdio_ctrl = bnx2x_get_emac_base(bp, in bnx2x_populate_int_phy()
11951 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; in bnx2x_populate_int_phy()
11953 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; in bnx2x_populate_int_phy()
11956 port, phy->addr, phy->mdio_ctrl); in bnx2x_populate_int_phy()
11958 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); in bnx2x_populate_int_phy()
11967 struct bnx2x_phy *phy) in bnx2x_populate_ext_phy() argument
11978 *phy = phy_8073; in bnx2x_populate_ext_phy()
11981 *phy = phy_8705; in bnx2x_populate_ext_phy()
11984 *phy = phy_8706; in bnx2x_populate_ext_phy()
11988 *phy = phy_8726; in bnx2x_populate_ext_phy()
11993 *phy = phy_8727; in bnx2x_populate_ext_phy()
11994 phy->flags |= FLAGS_NOC; in bnx2x_populate_ext_phy()
11999 *phy = phy_8727; in bnx2x_populate_ext_phy()
12002 *phy = phy_8481; in bnx2x_populate_ext_phy()
12005 *phy = phy_84823; in bnx2x_populate_ext_phy()
12008 *phy = phy_84833; in bnx2x_populate_ext_phy()
12011 *phy = phy_84834; in bnx2x_populate_ext_phy()
12015 *phy = phy_54618se; in bnx2x_populate_ext_phy()
12017 phy->flags |= FLAGS_EEE; in bnx2x_populate_ext_phy()
12020 *phy = phy_7101; in bnx2x_populate_ext_phy()
12023 *phy = phy_null; in bnx2x_populate_ext_phy()
12026 *phy = phy_null; in bnx2x_populate_ext_phy()
12034 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); in bnx2x_populate_ext_phy()
12035 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); in bnx2x_populate_ext_phy()
12044 phy->ver_addr = shmem_base + offsetof(struct shmem_region, in bnx2x_populate_ext_phy()
12056 phy->ver_addr = shmem2_base + in bnx2x_populate_ext_phy()
12067 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); in bnx2x_populate_ext_phy()
12069 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_populate_ext_phy()
12070 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && in bnx2x_populate_ext_phy()
12071 (phy->ver_addr)) { in bnx2x_populate_ext_phy()
12075 u32 raw_ver = REG_RD(bp, phy->ver_addr); in bnx2x_populate_ext_phy()
12078 phy->supported &= ~(SUPPORTED_100baseT_Half | in bnx2x_populate_ext_phy()
12085 phy->addr, phy->mdio_ctrl); in bnx2x_populate_ext_phy()
12090 u32 shmem2_base, u8 port, struct bnx2x_phy *phy) in bnx2x_populate_phy() argument
12093 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; in bnx2x_populate_phy()
12095 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); in bnx2x_populate_phy()
12097 port, phy); in bnx2x_populate_phy()
12102 struct bnx2x_phy *phy, in bnx2x_phy_def_cfg() argument
12112 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12120 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12127 phy_index, link_config, phy->speed_cap_mask); in bnx2x_phy_def_cfg()
12129 phy->req_duplex = DUPLEX_FULL; in bnx2x_phy_def_cfg()
12132 phy->req_duplex = DUPLEX_HALF; in bnx2x_phy_def_cfg()
12134 phy->req_line_speed = SPEED_10; in bnx2x_phy_def_cfg()
12137 phy->req_duplex = DUPLEX_HALF; in bnx2x_phy_def_cfg()
12139 phy->req_line_speed = SPEED_100; in bnx2x_phy_def_cfg()
12142 phy->req_line_speed = SPEED_1000; in bnx2x_phy_def_cfg()
12145 phy->req_line_speed = SPEED_2500; in bnx2x_phy_def_cfg()
12148 phy->req_line_speed = SPEED_10000; in bnx2x_phy_def_cfg()
12151 phy->req_line_speed = SPEED_AUTO_NEG; in bnx2x_phy_def_cfg()
12157 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; in bnx2x_phy_def_cfg()
12160 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; in bnx2x_phy_def_cfg()
12163 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; in bnx2x_phy_def_cfg()
12166 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; in bnx2x_phy_def_cfg()
12169 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_phy_def_cfg()
12211 struct bnx2x_phy *phy; in bnx2x_phy_probe() local
12229 phy = ¶ms->phy[actual_phy_idx]; in bnx2x_phy_probe()
12232 phy) != 0) { in bnx2x_phy_probe()
12239 *phy = phy_null; in bnx2x_phy_probe()
12242 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) in bnx2x_phy_probe()
12247 phy->flags &= ~FLAGS_TX_ERROR_CHECK; in bnx2x_phy_probe()
12251 phy->flags |= FLAGS_MDC_MDIO_WA_G; in bnx2x_phy_probe()
12265 media_types |= ((phy->media_type & in bnx2x_phy_probe()
12272 bnx2x_phy_def_cfg(params, phy, phy_index); in bnx2x_phy_probe()
12335 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); in bnx2x_init_xmac_loopback()
12336 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); in bnx2x_init_xmac_loopback()
12337 params->phy[INT_PHY].config_loopback( in bnx2x_init_xmac_loopback()
12338 ¶ms->phy[INT_PHY], in bnx2x_init_xmac_loopback()
12364 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; in bnx2x_init_xgxs_loopback()
12402 if (params->phy[phy_index].config_loopback) in bnx2x_init_xgxs_loopback()
12403 params->phy[phy_index].config_loopback( in bnx2x_init_xgxs_loopback()
12404 ¶ms->phy[phy_index], in bnx2x_init_xgxs_loopback()
12446 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; in bnx2x_avoid_link_flap() local
12447 if (phy->phy_specific_func) { in bnx2x_avoid_link_flap()
12449 phy->phy_specific_func(phy, params, PHY_INIT); in bnx2x_avoid_link_flap()
12451 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || in bnx2x_avoid_link_flap()
12452 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || in bnx2x_avoid_link_flap()
12453 (phy->media_type == ETH_PHY_DA_TWINAX)) in bnx2x_avoid_link_flap()
12454 bnx2x_verify_sfp_module(phy, params); in bnx2x_avoid_link_flap()
12700 if (params->phy[phy_index].link_reset) { in bnx2x_link_reset()
12702 ¶ms->phy[phy_index]); in bnx2x_link_reset()
12703 params->phy[phy_index].link_reset( in bnx2x_link_reset()
12704 ¶ms->phy[phy_index], in bnx2x_link_reset()
12707 if (params->phy[phy_index].flags & in bnx2x_link_reset()
12719 if (params->phy[INT_PHY].link_reset) in bnx2x_link_reset()
12720 params->phy[INT_PHY].link_reset( in bnx2x_link_reset()
12721 ¶ms->phy[INT_PHY], params); in bnx2x_link_reset()
12802 struct bnx2x_phy phy[PORT_MAX]; in bnx2x_8073_common_init_phy() local
12828 port_of_path, &phy[port]) != in bnx2x_8073_common_init_phy()
12849 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8073_common_init_phy()
12858 if (phy[PORT_0].addr & 0x1) { in bnx2x_8073_common_init_phy()
12859 phy_blk[PORT_0] = &(phy[PORT_1]); in bnx2x_8073_common_init_phy()
12860 phy_blk[PORT_1] = &(phy[PORT_0]); in bnx2x_8073_common_init_phy()
12862 phy_blk[PORT_0] = &(phy[PORT_0]); in bnx2x_8073_common_init_phy()
12863 phy_blk[PORT_1] = &(phy[PORT_1]); in bnx2x_8073_common_init_phy()
12930 struct bnx2x_phy phy; in bnx2x_8726_common_init_phy() local
12953 port, &phy) != in bnx2x_8726_common_init_phy()
12960 bnx2x_cl45_write(bp, &phy, in bnx2x_8726_common_init_phy()
13025 struct bnx2x_phy phy[PORT_MAX]; in bnx2x_8727_common_init_phy() local
13069 port_of_path, &phy[port]) != in bnx2x_8727_common_init_phy()
13084 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8727_common_init_phy()
13090 if (phy[PORT_0].addr & 0x1) { in bnx2x_8727_common_init_phy()
13091 phy_blk[PORT_0] = &(phy[PORT_1]); in bnx2x_8727_common_init_phy()
13092 phy_blk[PORT_1] = &(phy[PORT_0]); in bnx2x_8727_common_init_phy()
13094 phy_blk[PORT_0] = &(phy[PORT_0]); in bnx2x_8727_common_init_phy()
13095 phy_blk[PORT_1] = &(phy[PORT_1]); in bnx2x_8727_common_init_phy()
13394 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, in bnx2x_sfp_tx_fault_detection() argument
13430 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { in bnx2x_sfp_tx_fault_detection()
13439 struct bnx2x_phy *phy) in bnx2x_disable_kr2() argument
13464 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_disable_kr2()
13471 bnx2x_warpcore_restart_AN_KR(phy, params); in bnx2x_disable_kr2()
13476 struct bnx2x_phy *phy) in bnx2x_kr2_recovery() argument
13480 bnx2x_warpcore_enable_AN_KR2(phy, params, vars); in bnx2x_kr2_recovery()
13481 bnx2x_warpcore_restart_AN_KR(phy, params); in bnx2x_kr2_recovery()
13486 struct bnx2x_phy *phy) in bnx2x_check_kr2_wa() argument
13502 sigdet = bnx2x_warpcore_get_sigdet(phy, params); in bnx2x_check_kr2_wa()
13505 bnx2x_kr2_recovery(params, vars, phy); in bnx2x_check_kr2_wa()
13511 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_check_kr2_wa()
13512 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_check_kr2_wa()
13514 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13516 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13518 bnx2x_set_aer_mmd(params, phy); in bnx2x_check_kr2_wa()
13523 bnx2x_kr2_recovery(params, vars, phy); in bnx2x_check_kr2_wa()
13542 bnx2x_kr2_recovery(params, vars, phy); in bnx2x_check_kr2_wa()
13550 bnx2x_disable_kr2(params, vars, phy); in bnx2x_check_kr2_wa()
13560 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { in bnx2x_period_func()
13561 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); in bnx2x_period_func()
13570 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_period_func() local
13571 bnx2x_set_aer_mmd(params, phy); in bnx2x_period_func()
13572 if ((phy->supported & SUPPORTED_20000baseKR2_Full) && in bnx2x_period_func()
13573 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) in bnx2x_period_func()
13574 bnx2x_check_kr2_wa(params, vars, phy); in bnx2x_period_func()
13577 bnx2x_warpcore_config_runtime(phy, params, vars); in bnx2x_period_func()
13584 if (bnx2x_is_sfp_module_plugged(phy, params)) { in bnx2x_period_func()
13585 bnx2x_sfp_tx_fault_detection(phy, params, vars); in bnx2x_period_func()
13604 struct bnx2x_phy phy; in bnx2x_fan_failure_det_req() local
13608 port, &phy) in bnx2x_fan_failure_det_req()
13613 fan_failure_det_req |= (phy.flags & in bnx2x_fan_failure_det_req()
13632 if (params->phy[phy_index].hw_reset) { in bnx2x_hw_reset_phy()
13633 params->phy[phy_index].hw_reset( in bnx2x_hw_reset_phy()
13634 ¶ms->phy[phy_index], in bnx2x_hw_reset_phy()
13636 params->phy[phy_index] = phy_null; in bnx2x_hw_reset_phy()
13656 struct bnx2x_phy phy; in bnx2x_init_mod_abs_int() local
13660 shmem2_base, port, &phy) in bnx2x_init_mod_abs_int()
13665 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { in bnx2x_init_mod_abs_int()