Lines Matching refs:rb
51 static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb,
53 static enum bfa_status bfa_ioc_ct2_pll_init(void __iomem *rb,
245 void __iomem *rb; in bfa_ioc_ct_reg_init() local
248 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct_reg_init()
250 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox; in bfa_ioc_ct_reg_init()
251 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox; in bfa_ioc_ct_reg_init()
252 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn; in bfa_ioc_ct_reg_init()
255 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; in bfa_ioc_ct_reg_init()
256 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
257 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
258 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
259 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
260 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
261 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
263 ioc->ioc_regs.heartbeat = rb + BFA_IOC1_HBEAT_REG; in bfa_ioc_ct_reg_init()
264 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
265 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
266 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
267 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
268 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
269 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
275 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG; in bfa_ioc_ct_reg_init()
276 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG; in bfa_ioc_ct_reg_init()
277 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + APP_PLL_LCLK_CTL_REG; in bfa_ioc_ct_reg_init()
278 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + APP_PLL_SCLK_CTL_REG; in bfa_ioc_ct_reg_init()
283 ioc->ioc_regs.ioc_sem_reg = rb + HOST_SEM0_REG; in bfa_ioc_ct_reg_init()
284 ioc->ioc_regs.ioc_usage_sem_reg = rb + HOST_SEM1_REG; in bfa_ioc_ct_reg_init()
285 ioc->ioc_regs.ioc_init_sem_reg = rb + HOST_SEM2_REG; in bfa_ioc_ct_reg_init()
286 ioc->ioc_regs.ioc_usage_reg = rb + BFA_FW_USE_COUNT; in bfa_ioc_ct_reg_init()
287 ioc->ioc_regs.ioc_fail_sync = rb + BFA_IOC_FAIL_SYNC; in bfa_ioc_ct_reg_init()
292 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START; in bfa_ioc_ct_reg_init()
298 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); in bfa_ioc_ct_reg_init()
304 void __iomem *rb; in bfa_ioc_ct2_reg_init() local
307 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct2_reg_init()
309 ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox; in bfa_ioc_ct2_reg_init()
310 ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox; in bfa_ioc_ct2_reg_init()
311 ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn; in bfa_ioc_ct2_reg_init()
312 ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn; in bfa_ioc_ct2_reg_init()
313 ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu; in bfa_ioc_ct2_reg_init()
314 ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read; in bfa_ioc_ct2_reg_init()
317 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG; in bfa_ioc_ct2_reg_init()
318 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
319 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
320 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
321 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
323 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC1_HBEAT_REG; in bfa_ioc_ct2_reg_init()
324 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
325 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
326 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
327 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
333 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG; in bfa_ioc_ct2_reg_init()
334 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG; in bfa_ioc_ct2_reg_init()
335 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + CT2_APP_PLL_LCLK_CTL_REG; in bfa_ioc_ct2_reg_init()
336 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + CT2_APP_PLL_SCLK_CTL_REG; in bfa_ioc_ct2_reg_init()
341 ioc->ioc_regs.ioc_sem_reg = rb + CT2_HOST_SEM0_REG; in bfa_ioc_ct2_reg_init()
342 ioc->ioc_regs.ioc_usage_sem_reg = rb + CT2_HOST_SEM1_REG; in bfa_ioc_ct2_reg_init()
343 ioc->ioc_regs.ioc_init_sem_reg = rb + CT2_HOST_SEM2_REG; in bfa_ioc_ct2_reg_init()
344 ioc->ioc_regs.ioc_usage_reg = rb + CT2_BFA_FW_USE_COUNT; in bfa_ioc_ct2_reg_init()
345 ioc->ioc_regs.ioc_fail_sync = rb + CT2_BFA_IOC_FAIL_SYNC; in bfa_ioc_ct2_reg_init()
350 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START; in bfa_ioc_ct2_reg_init()
356 ioc->ioc_regs.err_set = rb + ERR_SET_REG; in bfa_ioc_ct2_reg_init()
365 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_map_port() local
371 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
380 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct2_map_port() local
383 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
391 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_isr_mode_set() local
394 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
413 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
441 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_nw_ioc_ct2_poweron() local
444 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
447 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_nw_ioc_ct2_poweron()
453 rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
455 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_nw_ioc_ct2_poweron()
569 bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) in bfa_ioc_ct_pll_init() argument
584 writel(0, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
588 (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
590 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
592 (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
594 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_ct_pll_init()
595 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_ct_pll_init()
596 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
597 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
598 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
599 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
600 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
601 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
604 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
607 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
610 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
613 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
614 readl(rb + HOSTFN0_INT_MSK); in bfa_ioc_ct_pll_init()
616 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
617 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
620 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
623 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
626 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
627 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
629 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
631 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
634 writel(0, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
635 writel(0, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
638 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
640 r32 = readl((rb + MBIST_STAT_REG)); in bfa_ioc_ct_pll_init()
641 writel(0, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
646 bfa_ioc_ct2_sclk_init(void __iomem *rb) in bfa_ioc_ct2_sclk_init() argument
653 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
657 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
663 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
665 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
670 r32 = readl((rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_sclk_init()
672 (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_sclk_init()
674 r32 = readl((rb + CT2_PCIE_MISC_REG)); in bfa_ioc_ct2_sclk_init()
676 (rb + CT2_PCIE_MISC_REG)); in bfa_ioc_ct2_sclk_init()
681 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
684 writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
698 bfa_ioc_ct2_lclk_init(void __iomem *rb) in bfa_ioc_ct2_lclk_init() argument
705 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
709 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
714 r32 = readl((rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
715 writel(r32, (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
720 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
721 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
726 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
729 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
738 bfa_ioc_ct2_mem_init(void __iomem *rb) in bfa_ioc_ct2_mem_init() argument
742 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
744 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
747 writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG)); in bfa_ioc_ct2_mem_init()
749 writel(0, (rb + CT2_MBIST_CTL_REG)); in bfa_ioc_ct2_mem_init()
753 bfa_ioc_ct2_mac_reset(void __iomem *rb) in bfa_ioc_ct2_mac_reset() argument
757 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_mac_reset()
758 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_mac_reset()
763 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_mac_reset()
765 (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_mac_reset()
770 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_mac_reset()
772 (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_mac_reset()
776 (rb + CT2_CSI_MAC_CONTROL_REG(0))); in bfa_ioc_ct2_mac_reset()
778 (rb + CT2_CSI_MAC_CONTROL_REG(1))); in bfa_ioc_ct2_mac_reset()
786 bfa_ioc_ct2_nfc_halted(void __iomem *rb) in bfa_ioc_ct2_nfc_halted() argument
790 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_halted()
798 bfa_ioc_ct2_nfc_resume(void __iomem *rb) in bfa_ioc_ct2_nfc_resume() argument
803 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG); in bfa_ioc_ct2_nfc_resume()
805 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_resume()
814 bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) in bfa_ioc_ct2_pll_init() argument
819 wgn = readl(rb + CT2_WGN_STATUS); in bfa_ioc_ct2_pll_init()
821 nfc_ver = readl(rb + CT2_RSC_GPR15_REG); in bfa_ioc_ct2_pll_init()
825 if (bfa_ioc_ct2_nfc_halted(rb)) in bfa_ioc_ct2_pll_init()
826 bfa_ioc_ct2_nfc_resume(rb); in bfa_ioc_ct2_pll_init()
828 rb + CT2_CSI_FW_CTL_SET_REG); in bfa_ioc_ct2_pll_init()
831 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
838 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
845 r32 = readl(rb + CT2_CSI_FW_CTL_REG); in bfa_ioc_ct2_pll_init()
848 writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG)); in bfa_ioc_ct2_pll_init()
850 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_pll_init()
856 bfa_ioc_ct2_mac_reset(rb); in bfa_ioc_ct2_pll_init()
857 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_pll_init()
858 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_pll_init()
861 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_pll_init()
863 rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
864 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_pll_init()
866 rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
871 r32 = readl((rb + PSS_GPIO_OUT_REG)); in bfa_ioc_ct2_pll_init()
872 writel(r32 & ~1, rb + PSS_GPIO_OUT_REG); in bfa_ioc_ct2_pll_init()
873 r32 = readl((rb + PSS_GPIO_OE_REG)); in bfa_ioc_ct2_pll_init()
874 writel(r32 | 1, rb + PSS_GPIO_OE_REG); in bfa_ioc_ct2_pll_init()
881 writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK)); in bfa_ioc_ct2_pll_init()
882 writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK)); in bfa_ioc_ct2_pll_init()
885 r32 = readl(rb + HOST_SEM5_REG); in bfa_ioc_ct2_pll_init()
887 r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
889 writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
890 readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
892 r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
894 writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
895 readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
899 bfa_ioc_ct2_mem_init(rb); in bfa_ioc_ct2_pll_init()
901 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG)); in bfa_ioc_ct2_pll_init()
902 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG)); in bfa_ioc_ct2_pll_init()