55 #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)  argument
56 #define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)  argument
60 #define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)  argument
61 #define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)  argument
66 #define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)  argument
70 #define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)  argument
74 #define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)  argument
78 #define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)  argument
82 #define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)  argument
89 #define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)  argument
90 #define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)  argument
94 #define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)  argument
95 #define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)  argument
107 #define V_INTERFACE(x) ((x) << S_INTERFACE)  argument
108 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)  argument
111 #define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE)  argument
115 #define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE)  argument
119 #define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE)  argument
124 #define V_MAC_SPEED(x) ((x) << S_MAC_SPEED)  argument
125 #define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)  argument
128 #define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE)  argument
132 #define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX)  argument
136 #define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC)  argument
140 #define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE)  argument
144 #define V_MAC_RESET(x) ((x) << S_MAC_RESET)  argument
148 #define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)  argument
152 #define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)  argument
156 #define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE)  argument
160 #define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)  argument
164 #define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE)  argument
168 #define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE)  argument
172 #define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)  argument
176 #define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)  argument
183 #define V_MAC_IFS2(x) ((x) << S_MAC_IFS2)  argument
184 #define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2)  argument
188 #define V_MAC_IFS1(x) ((x) << S_MAC_IFS1)  argument
189 #define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1)  argument
205 #define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)  argument
206 #define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)  argument
210 #define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)  argument
211 #define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)  argument