Lines Matching refs:t3_write_reg
88 t3_write_reg(adapter, p->reg_addr + offset, p->val); in t3_write_regs()
108 t3_write_reg(adapter, addr, v | val); in t3_set_reg_field()
129 t3_write_reg(adap, addr_reg, start_idx); in t3_read_indirect()
166 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start); in t3_mc7_bd_read()
167 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0); in t3_mc7_bd_read()
201 t3_write_reg(adap, A_MI1_CFG, val); in mi1_init()
219 t3_write_reg(adapter, A_MI1_ADDR, addr); in t3_mi1_read()
220 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2)); in t3_mi1_read()
238 t3_write_reg(adapter, A_MI1_ADDR, addr); in t3_mi1_write()
239 t3_write_reg(adapter, A_MI1_DATA, val); in t3_mi1_write()
240 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); in t3_mi1_write()
262 t3_write_reg(adapter, A_MI1_ADDR, addr); in mi1_wr_addr()
263 t3_write_reg(adapter, A_MI1_DATA, reg_addr); in mi1_wr_addr()
264 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0)); in mi1_wr_addr()
282 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3)); in mi1_ext_read()
302 t3_write_reg(adapter, A_MI1_DATA, val); in mi1_ext_write()
303 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); in mi1_ext_write()
775 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); in sf1_read()
800 t3_write_reg(adapter, A_SF_DATA, val); in sf1_write()
801 t3_write_reg(adapter, A_SF_OP, in sf1_write()
929 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0); in t3_get_tp_version()
1155 t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr); in t3_cim_ctl_blk_read()
1177 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, 0); in t3_gate_rx_traffic()
1180 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, 0); in t3_gate_rx_traffic()
1193 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, rx_hash_high); in t3_open_rx_traffic()
1194 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, rx_hash_low); in t3_open_rx_traffic()
1222 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_link_changed()
1246 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, in t3_link_changed()
1275 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, 0); in t3_link_fault()
1277 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_link_fault()
1305 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, in t3_link_fault()
1421 t3_write_reg(adapter, reg, status); in t3_handle_intr_status()
1802 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause); in mc7_intr_handler()
1852 t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause); in mac_intr_handler()
1881 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause); in t3_phy_intr_handler()
1935 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause); in t3_slow_intr_handler()
1979 t3_write_reg(adapter, A_TP_INT_ENABLE, in t3_intr_enable()
1983 t3_write_reg(adapter, A_CPL_INTR_ENABLE, in t3_intr_enable()
1985 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, in t3_intr_enable()
1989 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK); in t3_intr_enable()
1990 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK); in t3_intr_enable()
1993 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter)); in t3_intr_enable()
1996 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK); in t3_intr_enable()
1998 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK); in t3_intr_enable()
1999 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask); in t3_intr_enable()
2012 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0); in t3_intr_disable()
2050 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff); in t3_intr_clear()
2053 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff); in t3_intr_clear()
2054 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff); in t3_intr_clear()
2062 t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset, in t3_xgm_intr_enable()
2070 t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset, in t3_xgm_intr_disable()
2086 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), XGM_INTR_MASK); in t3_port_intr_enable()
2103 t3_write_reg(adapter, XGM_REG(A_XGM_INT_ENABLE, idx), 0); in t3_port_intr_disable()
2120 t3_write_reg(adapter, XGM_REG(A_XGM_INT_CAUSE, idx), 0xffffffff); in t3_port_intr_clear()
2146 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); in t3_sge_write_context()
2147 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); in t3_sge_write_context()
2148 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff); in t3_sge_write_context()
2149 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); in t3_sge_write_context()
2151 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); in t3_sge_write_context()
2152 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); in t3_sge_write_context()
2153 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff); in t3_sge_write_context()
2154 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); in t3_sge_write_context()
2156 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_write_context()
2176 t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0); in clear_sge_ctxt()
2177 t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0); in clear_sge_ctxt()
2178 t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0); in clear_sge_ctxt()
2179 t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0); in clear_sge_ctxt()
2180 t3_write_reg(adap, A_SG_CONTEXT_MASK0, 0xffffffff); in clear_sge_ctxt()
2181 t3_write_reg(adap, A_SG_CONTEXT_MASK1, 0xffffffff); in clear_sge_ctxt()
2182 t3_write_reg(adap, A_SG_CONTEXT_MASK2, 0xffffffff); in clear_sge_ctxt()
2183 t3_write_reg(adap, A_SG_CONTEXT_MASK3, 0xffffffff); in clear_sge_ctxt()
2184 t3_write_reg(adap, A_SG_CONTEXT_CMD, in clear_sge_ctxt()
2220 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) | in t3_sge_init_ecntxt()
2222 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) | in t3_sge_init_ecntxt()
2225 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, base_addr); in t3_sge_init_ecntxt()
2227 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, in t3_sge_init_ecntxt()
2261 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, base_addr); in t3_sge_init_flcntxt()
2263 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, in t3_sge_init_flcntxt()
2266 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) | in t3_sge_init_flcntxt()
2269 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, in t3_sge_init_flcntxt()
2302 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) | in t3_sge_init_rspcntxt()
2304 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); in t3_sge_init_rspcntxt()
2308 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, in t3_sge_init_rspcntxt()
2310 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres); in t3_sge_init_rspcntxt()
2339 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size)); in t3_sge_init_cqcntxt()
2340 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, base_addr); in t3_sge_init_cqcntxt()
2342 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, in t3_sge_init_cqcntxt()
2346 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) | in t3_sge_init_cqcntxt()
2365 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); in t3_sge_enable_ecntxt()
2366 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_enable_ecntxt()
2367 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_enable_ecntxt()
2368 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID); in t3_sge_enable_ecntxt()
2369 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable)); in t3_sge_enable_ecntxt()
2370 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_enable_ecntxt()
2389 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); in t3_sge_disable_fl()
2390 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_fl()
2391 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE)); in t3_sge_disable_fl()
2392 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_fl()
2393 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0); in t3_sge_disable_fl()
2394 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_fl()
2413 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); in t3_sge_disable_rspcntxt()
2414 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_rspcntxt()
2415 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_disable_rspcntxt()
2416 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_rspcntxt()
2417 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); in t3_sge_disable_rspcntxt()
2418 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_rspcntxt()
2437 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); in t3_sge_disable_cqcntxt()
2438 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_cqcntxt()
2439 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_disable_cqcntxt()
2440 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_cqcntxt()
2441 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); in t3_sge_disable_cqcntxt()
2442 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_cqcntxt()
2466 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16); in t3_sge_cqcntxt_op()
2467 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) | in t3_sge_cqcntxt_op()
2477 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_cqcntxt_op()
2514 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val); in t3_config_rss()
2519 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE, in t3_config_rss()
2525 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config); in t3_config_rss()
2560 t3_write_reg((adap), A_ ## reg, (start)); \
2589 t3_write_reg(adap, A_TP_PMM_SIZE, in partition_mem()
2592 t3_write_reg(adap, A_TP_PMM_TX_BASE, 0); in partition_mem()
2593 t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size); in partition_mem()
2594 t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs); in partition_mem()
2598 t3_write_reg(adap, A_TP_PMM_RX_BASE, 0); in partition_mem()
2599 t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size); in partition_mem()
2600 t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs); in partition_mem()
2606 t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs); in partition_mem()
2611 t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m); in partition_mem()
2619 t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m); in partition_mem()
2620 t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m); in partition_mem()
2632 t3_write_reg(adap, A_TP_PIO_ADDR, addr); in tp_wr_indirect()
2633 t3_write_reg(adap, A_TP_PIO_DATA, val); in tp_wr_indirect()
2638 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU | in tp_config()
2641 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) | in tp_config()
2644 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) | in tp_config()
2650 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814); in tp_config()
2651 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105); in tp_config()
2663 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080); in tp_config()
2664 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000); in tp_config()
2680 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0); in tp_config()
2681 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0); in tp_config()
2682 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0); in tp_config()
2683 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000); in tp_config()
2708 t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) | in tp_set_timers()
2711 t3_write_reg(adap, A_TP_DACK_TIMER, in tp_set_timers()
2713 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100); in tp_set_timers()
2714 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504); in tp_set_timers()
2715 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908); in tp_set_timers()
2716 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c); in tp_set_timers()
2717 t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | in tp_set_timers()
2724 t3_write_reg(adap, A_TP_MSL, adap->params.rev > 0 ? 0 : 2 SECONDS); in tp_set_timers()
2725 t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN)); in tp_set_timers()
2726 t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS); in tp_set_timers()
2727 t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS); in tp_set_timers()
2728 t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS); in tp_set_timers()
2729 t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS); in tp_set_timers()
2730 t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS); in tp_set_timers()
2731 t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS); in tp_set_timers()
2732 t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS); in tp_set_timers()
2761 t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) | in t3_tp_set_coalescing_size()
2764 t3_write_reg(adap, A_TP_PARA_REG3, val); in t3_tp_set_coalescing_size()
2778 t3_write_reg(adap, A_TP_PARA_REG7, in t3_tp_set_max_rxsize()
2880 t3_write_reg(adap, A_TP_MTU_TABLE, in t3_load_mtus()
2889 t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | in t3_load_mtus()
2909 t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
2910 t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
2915 t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
2916 t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
2930 t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff); in ulp_config()
2946 t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, be32_to_cpu(*buf++)); in t3_set_proto_sram()
2947 t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, be32_to_cpu(*buf++)); in t3_set_proto_sram()
2948 t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, be32_to_cpu(*buf++)); in t3_set_proto_sram()
2949 t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, be32_to_cpu(*buf++)); in t3_set_proto_sram()
2950 t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, be32_to_cpu(*buf++)); in t3_set_proto_sram()
2952 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31); in t3_set_proto_sram()
2956 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, 0); in t3_set_proto_sram()
3027 t3_write_reg(adap, A_TP_TM_PIO_ADDR, in t3_config_sched()
3034 t3_write_reg(adap, A_TP_TM_PIO_DATA, v); in t3_config_sched()
3047 t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE); in tp_init()
3055 t3_write_reg(adap, A_TP_RESET, F_TPRESET); in tp_init()
3070 t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_ENFORCEPKT | in chan_init_hw()
3073 t3_write_reg(adap, A_PM1_TX_CFG, in chan_init_hw()
3078 t3_write_reg(adap, A_ULPTX_DMA_WEIGHT, in chan_init_hw()
3080 t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN | in chan_init_hw()
3083 t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000); in chan_init_hw()
3085 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP, in chan_init_hw()
3088 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, in chan_init_hw()
3099 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0); in calibrate_xgm()
3104 t3_write_reg(adapter, A_XGM_XAUI_IMP, in calibrate_xgm()
3112 t3_write_reg(adapter, A_XGM_RGMII_IMP, in calibrate_xgm()
3123 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET | in calibrate_xgm_t3b()
3152 t3_write_reg(adapter, addr, val); in wrreg_wait()
3186 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN); in mc7_init()
3191 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN); in mc7_init()
3202 t3_write_reg(adapter, mc7->offset + A_MC7_PARM, in mc7_init()
3208 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, in mc7_init()
3225 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100); in mc7_init()
3243 t3_write_reg(adapter, mc7->offset + A_MC7_REF, in mc7_init()
3247 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN); in mc7_init()
3248 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0); in mc7_init()
3249 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0); in mc7_init()
3250 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END, in mc7_init()
3252 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1)); in mc7_init()
3325 t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff); in config_pcie()
3385 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff); in t3_init_hw()
3386 t3_write_reg(adapter, A_PM1_RX_MODE, 0); in t3_init_hw()
3387 t3_write_reg(adapter, A_PM1_TX_MODE, 0); in t3_init_hw()
3392 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter)); in t3_init_hw()
3394 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); in t3_init_hw()
3395 t3_write_reg(adapter, A_CIM_BOOT_CFG, in t3_init_hw()
3518 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset, in mac_prep()
3531 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */ in early_hw_init()
3533 t3_write_reg(adapter, A_T3DBG_GPIO_EN, in early_hw_init()
3535 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0); in early_hw_init()
3536 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff)); in early_hw_init()
3542 t3_write_reg(adapter, A_XGM_PORT_CFG, val); in early_hw_init()
3546 t3_write_reg(adapter, A_XGM_PORT_CFG, val); in early_hw_init()
3548 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val); in early_hw_init()
3565 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE); in t3_reset_adapter()
3602 t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0); in init_parity()
3605 t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN | in init_parity()