734 				adapter->rx_ring[i]->reg_idx = rbase_offset +  in igb_cache_ring_register()
745 			adapter->rx_ring[i]->reg_idx = rbase_offset + i;  in igb_cache_ring_register()
747 			adapter->tx_ring[j]->reg_idx = rbase_offset + j;  in igb_cache_ring_register()
788 		rx_queue = q_vector->rx.ring->reg_idx;  in igb_assign_vector()
790 		tx_queue = q_vector->tx.ring->reg_idx;  in igb_assign_vector()
2984 	int reg_idx = ring->reg_idx;  in igb_configure_tx_ring()  local
2987 	wr32(E1000_TXDCTL(reg_idx), 0);  in igb_configure_tx_ring()
2991 	wr32(E1000_TDLEN(reg_idx),  in igb_configure_tx_ring()
2993 	wr32(E1000_TDBAL(reg_idx),  in igb_configure_tx_ring()
2995 	wr32(E1000_TDBAH(reg_idx), tdba >> 32);  in igb_configure_tx_ring()
2997 	ring->tail = hw->hw_addr + E1000_TDT(reg_idx);  in igb_configure_tx_ring()
2998 	wr32(E1000_TDH(reg_idx), 0);  in igb_configure_tx_ring()
3006 	wr32(E1000_TXDCTL(reg_idx), txdctl);  in igb_configure_tx_ring()
3347 	int reg_idx = ring->reg_idx;  in igb_configure_rx_ring()  local
3351 	wr32(E1000_RXDCTL(reg_idx), 0);  in igb_configure_rx_ring()
3354 	wr32(E1000_RDBAL(reg_idx),  in igb_configure_rx_ring()
3356 	wr32(E1000_RDBAH(reg_idx), rdba >> 32);  in igb_configure_rx_ring()
3357 	wr32(E1000_RDLEN(reg_idx),  in igb_configure_rx_ring()
3361 	ring->tail = hw->hw_addr + E1000_RDT(reg_idx);  in igb_configure_rx_ring()
3362 	wr32(E1000_RDH(reg_idx), 0);  in igb_configure_rx_ring()
3375 	wr32(E1000_SRRCTL(reg_idx), srrctl);  in igb_configure_rx_ring()
3378 	igb_set_vmolr(adapter, reg_idx & 0x7, true);  in igb_configure_rx_ring()
3386 	wr32(E1000_RXDCTL(reg_idx), rxdctl);  in igb_configure_rx_ring()
4270 		mss_l4len_idx |= tx_ring->reg_idx << 4;  in igb_tx_ctxtdesc()
4447 		olinfo_status |= tx_ring->reg_idx << 4;  in igb_tx_olinfo_status()
5133 	wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);  in igb_update_tx_dca()
5153 	wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);  in igb_update_rx_dca()
6106 				rd32(E1000_TDH(tx_ring->reg_idx)),  in igb_clean_tx_irq()