203 	if (addr >= EIE && addr <= ECON1)  in enc28j60_set_bank()
209 			spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,  in enc28j60_set_bank()
212 			spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,  in enc28j60_set_bank()
217 			spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,  in enc28j60_set_bank()
220 			spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,  in enc28j60_set_bank()
552 		nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),  in enc28j60_dump_regs()
639 		nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);  in enc28j60_lowpower()
641 		poll_ready(priv, ECON1, ECON1_TXRTS, 0);  in enc28j60_lowpower()
664 	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);  in enc28j60_hw_init()
762 	nolock_reg_bfset(priv, ECON1, ECON1_RXEN);  in enc28j60_hw_enable()
772 	nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);  in enc28j60_hw_disable()
918 		nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);  in enc28j60_hw_rx()
919 		nolock_reg_bfset(priv, ECON1, ECON1_RXRST);  in enc28j60_hw_rx()
920 		nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);  in enc28j60_hw_rx()
923 		nolock_reg_bfset(priv, ECON1, ECON1_RXEN);  in enc28j60_hw_rx()
1081 	locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);  in enc28j60_tx_clear()
1178 			locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);  in enc28j60_irq_work_handler()
1184 			nolock_reg_bfset(priv, ECON1, ECON1_TXRST);  in enc28j60_irq_work_handler()
1185 			nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);  in enc28j60_irq_work_handler()
1195 					locked_reg_bfset(priv, ECON1,  in enc28j60_irq_work_handler()
1274 	locked_reg_bfset(priv, ECON1, ECON1_TXRTS);  in enc28j60_hw_tx()