Lines Matching refs:gp
119 static u16 __phy_read(struct gem *gp, int phy_addr, int reg) in __phy_read() argument
129 writel(cmd, gp->regs + MIF_FRAME); in __phy_read()
132 cmd = readl(gp->regs + MIF_FRAME); in __phy_read()
147 struct gem *gp = netdev_priv(dev); in _phy_read() local
148 return __phy_read(gp, mii_id, reg); in _phy_read()
151 static inline u16 phy_read(struct gem *gp, int reg) in phy_read() argument
153 return __phy_read(gp, gp->mii_phy_addr, reg); in phy_read()
156 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val) in __phy_write() argument
167 writel(cmd, gp->regs + MIF_FRAME); in __phy_write()
170 cmd = readl(gp->regs + MIF_FRAME); in __phy_write()
180 struct gem *gp = netdev_priv(dev); in _phy_write() local
181 __phy_write(gp, mii_id, reg, val & 0xffff); in _phy_write()
184 static inline void phy_write(struct gem *gp, int reg, u16 val) in phy_write() argument
186 __phy_write(gp, gp->mii_phy_addr, reg, val); in phy_write()
189 static inline void gem_enable_ints(struct gem *gp) in gem_enable_ints() argument
192 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_enable_ints()
195 static inline void gem_disable_ints(struct gem *gp) in gem_disable_ints() argument
198 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_disable_ints()
199 (void)readl(gp->regs + GREG_IMASK); /* write posting */ in gem_disable_ints()
202 static void gem_get_cell(struct gem *gp) in gem_get_cell() argument
204 BUG_ON(gp->cell_enabled < 0); in gem_get_cell()
205 gp->cell_enabled++; in gem_get_cell()
207 if (gp->cell_enabled == 1) { in gem_get_cell()
209 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1); in gem_get_cell()
216 static void gem_put_cell(struct gem *gp) in gem_put_cell() argument
218 BUG_ON(gp->cell_enabled <= 0); in gem_put_cell()
219 gp->cell_enabled--; in gem_put_cell()
221 if (gp->cell_enabled == 0) { in gem_put_cell()
223 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0); in gem_put_cell()
229 static inline void gem_netif_stop(struct gem *gp) in gem_netif_stop() argument
231 gp->dev->trans_start = jiffies; /* prevent tx timeout */ in gem_netif_stop()
232 napi_disable(&gp->napi); in gem_netif_stop()
233 netif_tx_disable(gp->dev); in gem_netif_stop()
236 static inline void gem_netif_start(struct gem *gp) in gem_netif_start() argument
242 netif_wake_queue(gp->dev); in gem_netif_start()
243 napi_enable(&gp->napi); in gem_netif_start()
246 static void gem_schedule_reset(struct gem *gp) in gem_schedule_reset() argument
248 gp->reset_task_pending = 1; in gem_schedule_reset()
249 schedule_work(&gp->reset_task); in gem_schedule_reset()
252 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits) in gem_handle_mif_event() argument
254 if (netif_msg_intr(gp)) in gem_handle_mif_event()
255 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name); in gem_handle_mif_event()
258 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_pcs_interrupt() argument
260 u32 pcs_istat = readl(gp->regs + PCS_ISTAT); in gem_pcs_interrupt()
263 if (netif_msg_intr(gp)) in gem_pcs_interrupt()
265 gp->dev->name, pcs_istat); in gem_pcs_interrupt()
276 pcs_miistat = readl(gp->regs + PCS_MIISTAT); in gem_pcs_interrupt()
279 (readl(gp->regs + PCS_MIISTAT) & in gem_pcs_interrupt()
294 netif_carrier_on(gp->dev); in gem_pcs_interrupt()
297 netif_carrier_off(gp->dev); in gem_pcs_interrupt()
301 if (!timer_pending(&gp->link_timer)) in gem_pcs_interrupt()
308 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_txmac_interrupt() argument
310 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT); in gem_txmac_interrupt()
312 if (netif_msg_intr(gp)) in gem_txmac_interrupt()
314 gp->dev->name, txmac_stat); in gem_txmac_interrupt()
361 static int gem_rxmac_reset(struct gem *gp) in gem_rxmac_reset() argument
363 struct net_device *dev = gp->dev; in gem_rxmac_reset()
369 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); in gem_rxmac_reset()
371 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD)) in gem_rxmac_reset()
380 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, in gem_rxmac_reset()
381 gp->regs + MAC_RXCFG); in gem_rxmac_reset()
383 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB)) in gem_rxmac_reset()
393 writel(0, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
395 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE)) in gem_rxmac_reset()
407 writel(gp->swrst_base | GREG_SWRST_RXRST, in gem_rxmac_reset()
408 gp->regs + GREG_SWRST); in gem_rxmac_reset()
410 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST)) in gem_rxmac_reset()
421 struct gem_rxd *rxd = &gp->init_block->rxd[i]; in gem_rxmac_reset()
423 if (gp->rx_skbs[i] == NULL) { in gem_rxmac_reset()
428 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); in gem_rxmac_reset()
430 gp->rx_new = gp->rx_old = 0; in gem_rxmac_reset()
433 desc_dma = (u64) gp->gblock_dvma; in gem_rxmac_reset()
435 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); in gem_rxmac_reset()
436 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); in gem_rxmac_reset()
437 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); in gem_rxmac_reset()
440 writel(val, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
441 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) in gem_rxmac_reset()
444 gp->regs + RXDMA_BLANK); in gem_rxmac_reset()
448 gp->regs + RXDMA_BLANK); in gem_rxmac_reset()
449 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); in gem_rxmac_reset()
450 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); in gem_rxmac_reset()
451 writel(val, gp->regs + RXDMA_PTHRESH); in gem_rxmac_reset()
452 val = readl(gp->regs + RXDMA_CFG); in gem_rxmac_reset()
453 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
454 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); in gem_rxmac_reset()
455 val = readl(gp->regs + MAC_RXCFG); in gem_rxmac_reset()
456 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_rxmac_reset()
461 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_rxmac_interrupt() argument
463 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT); in gem_rxmac_interrupt()
466 if (netif_msg_intr(gp)) in gem_rxmac_interrupt()
468 gp->dev->name, rxmac_stat); in gem_rxmac_interrupt()
471 u32 smac = readl(gp->regs + MAC_SMACHINE); in gem_rxmac_interrupt()
477 ret = gem_rxmac_reset(gp); in gem_rxmac_interrupt()
495 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_mac_interrupt() argument
497 u32 mac_cstat = readl(gp->regs + MAC_CSTAT); in gem_mac_interrupt()
499 if (netif_msg_intr(gp)) in gem_mac_interrupt()
501 gp->dev->name, mac_cstat); in gem_mac_interrupt()
508 gp->pause_entered++; in gem_mac_interrupt()
511 gp->pause_last_time_recvd = (mac_cstat >> 16); in gem_mac_interrupt()
516 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_mif_interrupt() argument
518 u32 mif_status = readl(gp->regs + MIF_STATUS); in gem_mif_interrupt()
524 gem_handle_mif_event(gp, reg_val, changed_bits); in gem_mif_interrupt()
529 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_pci_interrupt() argument
531 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT); in gem_pci_interrupt()
533 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && in gem_pci_interrupt()
534 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { in gem_pci_interrupt()
555 pci_read_config_word(gp->pdev, PCI_STATUS, in gem_pci_interrupt()
579 pci_write_config_word(gp->pdev, in gem_pci_interrupt()
592 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_abnormal_irq() argument
596 if (netif_msg_rx_err(gp)) in gem_abnormal_irq()
598 gp->dev->name); in gem_abnormal_irq()
604 if (netif_msg_rx_err(gp)) in gem_abnormal_irq()
606 gp->dev->name); in gem_abnormal_irq()
613 if (gem_pcs_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
618 if (gem_txmac_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
623 if (gem_rxmac_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
628 if (gem_mac_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
633 if (gem_mif_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
638 if (gem_pci_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
645 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_tx() argument
649 entry = gp->tx_old; in gem_tx()
658 if (netif_msg_tx_done(gp)) in gem_tx()
660 gp->dev->name, entry); in gem_tx()
661 skb = gp->tx_skbs[entry]; in gem_tx()
678 gp->tx_skbs[entry] = NULL; in gem_tx()
682 txd = &gp->init_block->txd[entry]; in gem_tx()
687 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); in gem_tx()
694 gp->tx_old = entry; in gem_tx()
704 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) { in gem_tx()
709 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) in gem_tx()
715 static __inline__ void gem_post_rxds(struct gem *gp, int limit) in gem_post_rxds() argument
719 cluster_start = curr = (gp->rx_new & ~(4 - 1)); in gem_post_rxds()
727 &gp->init_block->rxd[cluster_start]; in gem_post_rxds()
729 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); in gem_post_rxds()
741 writel(kick, gp->regs + RXDMA_KICK); in gem_post_rxds()
759 static int gem_rx(struct gem *gp, int work_to_do) in gem_rx() argument
761 struct net_device *dev = gp->dev; in gem_rx()
766 if (netif_msg_rx_status(gp)) in gem_rx()
768 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new); in gem_rx()
770 entry = gp->rx_new; in gem_rx()
772 done = readl(gp->regs + RXDMA_DONE); in gem_rx()
774 struct gem_rxd *rxd = &gp->init_block->rxd[entry]; in gem_rx()
794 done = readl(gp->regs + RXDMA_DONE); in gem_rx()
802 skb = gp->rx_skbs[entry]; in gem_rx()
822 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC); in gem_rx()
827 pci_unmap_page(gp->pdev, dma_addr, in gem_rx()
828 RX_BUF_ALLOC_SIZE(gp), in gem_rx()
830 gp->rx_skbs[entry] = new_skb; in gem_rx()
831 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET)); in gem_rx()
832 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev, in gem_rx()
835 RX_BUF_ALLOC_SIZE(gp), in gem_rx()
851 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in gem_rx()
853 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in gem_rx()
862 skb->protocol = eth_type_trans(skb, gp->dev); in gem_rx()
864 napi_gro_receive(&gp->napi, skb); in gem_rx()
873 gem_post_rxds(gp, entry); in gem_rx()
875 gp->rx_new = entry; in gem_rx()
878 netdev_info(gp->dev, "Memory squeeze, deferring packet\n"); in gem_rx()
885 struct gem *gp = container_of(napi, struct gem, napi); in gem_poll() local
886 struct net_device *dev = gp->dev; in gem_poll()
892 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) { in gem_poll()
902 reset = gem_abnormal_irq(dev, gp, gp->status); in gem_poll()
905 gem_schedule_reset(gp); in gem_poll()
912 gem_tx(dev, gp, gp->status); in gem_poll()
919 work_done += gem_rx(gp, budget - work_done); in gem_poll()
924 gp->status = readl(gp->regs + GREG_STAT); in gem_poll()
925 } while (gp->status & GREG_STAT_NAPI); in gem_poll()
928 gem_enable_ints(gp); in gem_poll()
936 struct gem *gp = netdev_priv(dev); in gem_interrupt() local
938 if (napi_schedule_prep(&gp->napi)) { in gem_interrupt()
939 u32 gem_status = readl(gp->regs + GREG_STAT); in gem_interrupt()
942 napi_enable(&gp->napi); in gem_interrupt()
945 if (netif_msg_intr(gp)) in gem_interrupt()
947 gp->dev->name, gem_status); in gem_interrupt()
949 gp->status = gem_status; in gem_interrupt()
950 gem_disable_ints(gp); in gem_interrupt()
951 __napi_schedule(&gp->napi); in gem_interrupt()
964 struct gem *gp = netdev_priv(dev); in gem_poll_controller() local
966 disable_irq(gp->pdev->irq); in gem_poll_controller()
967 gem_interrupt(gp->pdev->irq, dev); in gem_poll_controller()
968 enable_irq(gp->pdev->irq); in gem_poll_controller()
974 struct gem *gp = netdev_priv(dev); in gem_tx_timeout() local
979 readl(gp->regs + TXDMA_CFG), in gem_tx_timeout()
980 readl(gp->regs + MAC_TXSTAT), in gem_tx_timeout()
981 readl(gp->regs + MAC_TXCFG)); in gem_tx_timeout()
983 readl(gp->regs + RXDMA_CFG), in gem_tx_timeout()
984 readl(gp->regs + MAC_RXSTAT), in gem_tx_timeout()
985 readl(gp->regs + MAC_RXCFG)); in gem_tx_timeout()
987 gem_schedule_reset(gp); in gem_tx_timeout()
1002 struct gem *gp = netdev_priv(dev); in gem_start_xmit() local
1016 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) { in gem_start_xmit()
1025 entry = gp->tx_new; in gem_start_xmit()
1026 gp->tx_skbs[entry] = skb; in gem_start_xmit()
1029 struct gem_txd *txd = &gp->init_block->txd[entry]; in gem_start_xmit()
1034 mapping = pci_map_page(gp->pdev, in gem_start_xmit()
1060 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data), in gem_start_xmit()
1072 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag, in gem_start_xmit()
1078 txd = &gp->init_block->txd[entry]; in gem_start_xmit()
1088 txd = &gp->init_block->txd[first_entry]; in gem_start_xmit()
1095 gp->tx_new = entry; in gem_start_xmit()
1096 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) { in gem_start_xmit()
1105 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) in gem_start_xmit()
1108 if (netif_msg_tx_queued(gp)) in gem_start_xmit()
1112 writel(gp->tx_new, gp->regs + TXDMA_KICK); in gem_start_xmit()
1117 static void gem_pcs_reset(struct gem *gp) in gem_pcs_reset() argument
1123 val = readl(gp->regs + PCS_MIICTRL); in gem_pcs_reset()
1125 writel(val, gp->regs + PCS_MIICTRL); in gem_pcs_reset()
1128 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) { in gem_pcs_reset()
1134 netdev_warn(gp->dev, "PCS reset bit would not clear\n"); in gem_pcs_reset()
1137 static void gem_pcs_reinit_adv(struct gem *gp) in gem_pcs_reinit_adv() argument
1144 val = readl(gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1146 writel(val, gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1151 val = readl(gp->regs + PCS_MIIADV); in gem_pcs_reinit_adv()
1154 writel(val, gp->regs + PCS_MIIADV); in gem_pcs_reinit_adv()
1159 val = readl(gp->regs + PCS_MIICTRL); in gem_pcs_reinit_adv()
1162 writel(val, gp->regs + PCS_MIICTRL); in gem_pcs_reinit_adv()
1164 val = readl(gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1166 writel(val, gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1172 val = readl(gp->regs + PCS_SCTRL); in gem_pcs_reinit_adv()
1173 if (gp->phy_type == phy_serialink) in gem_pcs_reinit_adv()
1177 writel(val, gp->regs + PCS_SCTRL); in gem_pcs_reinit_adv()
1182 static void gem_reset(struct gem *gp) in gem_reset() argument
1188 writel(0xffffffff, gp->regs + GREG_IMASK); in gem_reset()
1191 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST, in gem_reset()
1192 gp->regs + GREG_SWRST); in gem_reset()
1198 val = readl(gp->regs + GREG_SWRST); in gem_reset()
1204 netdev_err(gp->dev, "SW reset is ghetto\n"); in gem_reset()
1206 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes) in gem_reset()
1207 gem_pcs_reinit_adv(gp); in gem_reset()
1210 static void gem_start_dma(struct gem *gp) in gem_start_dma() argument
1215 val = readl(gp->regs + TXDMA_CFG); in gem_start_dma()
1216 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); in gem_start_dma()
1217 val = readl(gp->regs + RXDMA_CFG); in gem_start_dma()
1218 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); in gem_start_dma()
1219 val = readl(gp->regs + MAC_TXCFG); in gem_start_dma()
1220 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); in gem_start_dma()
1221 val = readl(gp->regs + MAC_RXCFG); in gem_start_dma()
1222 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_start_dma()
1224 (void) readl(gp->regs + MAC_RXCFG); in gem_start_dma()
1227 gem_enable_ints(gp); in gem_start_dma()
1229 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); in gem_start_dma()
1234 static void gem_stop_dma(struct gem *gp) in gem_stop_dma() argument
1239 val = readl(gp->regs + TXDMA_CFG); in gem_stop_dma()
1240 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); in gem_stop_dma()
1241 val = readl(gp->regs + RXDMA_CFG); in gem_stop_dma()
1242 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); in gem_stop_dma()
1243 val = readl(gp->regs + MAC_TXCFG); in gem_stop_dma()
1244 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); in gem_stop_dma()
1245 val = readl(gp->regs + MAC_RXCFG); in gem_stop_dma()
1246 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_stop_dma()
1248 (void) readl(gp->regs + MAC_RXCFG); in gem_stop_dma()
1255 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep) in gem_begin_auto_negotiation() argument
1262 if (gp->phy_type != phy_mii_mdio0 && in gem_begin_auto_negotiation()
1263 gp->phy_type != phy_mii_mdio1) in gem_begin_auto_negotiation()
1267 if (found_mii_phy(gp)) in gem_begin_auto_negotiation()
1268 features = gp->phy_mii.def->features; in gem_begin_auto_negotiation()
1273 if (gp->phy_mii.advertising != 0) in gem_begin_auto_negotiation()
1274 advertise &= gp->phy_mii.advertising; in gem_begin_auto_negotiation()
1276 autoneg = gp->want_autoneg; in gem_begin_auto_negotiation()
1277 speed = gp->phy_mii.speed; in gem_begin_auto_negotiation()
1278 duplex = gp->phy_mii.duplex; in gem_begin_auto_negotiation()
1313 if (!netif_device_present(gp->dev)) { in gem_begin_auto_negotiation()
1314 gp->phy_mii.autoneg = gp->want_autoneg = autoneg; in gem_begin_auto_negotiation()
1315 gp->phy_mii.speed = speed; in gem_begin_auto_negotiation()
1316 gp->phy_mii.duplex = duplex; in gem_begin_auto_negotiation()
1321 gp->want_autoneg = autoneg; in gem_begin_auto_negotiation()
1323 if (found_mii_phy(gp)) in gem_begin_auto_negotiation()
1324 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise); in gem_begin_auto_negotiation()
1325 gp->lstate = link_aneg; in gem_begin_auto_negotiation()
1327 if (found_mii_phy(gp)) in gem_begin_auto_negotiation()
1328 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex); in gem_begin_auto_negotiation()
1329 gp->lstate = link_force_ok; in gem_begin_auto_negotiation()
1333 gp->timer_ticks = 0; in gem_begin_auto_negotiation()
1334 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); in gem_begin_auto_negotiation()
1340 static int gem_set_link_modes(struct gem *gp) in gem_set_link_modes() argument
1342 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0); in gem_set_link_modes()
1350 if (found_mii_phy(gp)) { in gem_set_link_modes()
1351 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii)) in gem_set_link_modes()
1353 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL); in gem_set_link_modes()
1354 speed = gp->phy_mii.speed; in gem_set_link_modes()
1355 pause = gp->phy_mii.pause; in gem_set_link_modes()
1356 } else if (gp->phy_type == phy_serialink || in gem_set_link_modes()
1357 gp->phy_type == phy_serdes) { in gem_set_link_modes()
1358 u32 pcs_lpa = readl(gp->regs + PCS_MIILP); in gem_set_link_modes()
1360 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes) in gem_set_link_modes()
1365 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n", in gem_set_link_modes()
1380 writel(val, gp->regs + MAC_TXCFG); in gem_set_link_modes()
1384 (gp->phy_type == phy_mii_mdio0 || in gem_set_link_modes()
1385 gp->phy_type == phy_mii_mdio1)) { in gem_set_link_modes()
1394 writel(val, gp->regs + MAC_XIFCFG); in gem_set_link_modes()
1400 val = readl(gp->regs + MAC_TXCFG); in gem_set_link_modes()
1401 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); in gem_set_link_modes()
1403 val = readl(gp->regs + MAC_RXCFG); in gem_set_link_modes()
1404 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); in gem_set_link_modes()
1406 val = readl(gp->regs + MAC_TXCFG); in gem_set_link_modes()
1407 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); in gem_set_link_modes()
1409 val = readl(gp->regs + MAC_RXCFG); in gem_set_link_modes()
1410 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); in gem_set_link_modes()
1413 if (gp->phy_type == phy_serialink || in gem_set_link_modes()
1414 gp->phy_type == phy_serdes) { in gem_set_link_modes()
1415 u32 pcs_lpa = readl(gp->regs + PCS_MIILP); in gem_set_link_modes()
1422 writel(512, gp->regs + MAC_STIME); in gem_set_link_modes()
1424 writel(64, gp->regs + MAC_STIME); in gem_set_link_modes()
1425 val = readl(gp->regs + MAC_MCCFG); in gem_set_link_modes()
1430 writel(val, gp->regs + MAC_MCCFG); in gem_set_link_modes()
1432 gem_start_dma(gp); in gem_set_link_modes()
1436 if (netif_msg_link(gp)) { in gem_set_link_modes()
1438 netdev_info(gp->dev, in gem_set_link_modes()
1440 gp->rx_fifo_sz, in gem_set_link_modes()
1441 gp->rx_pause_off, in gem_set_link_modes()
1442 gp->rx_pause_on); in gem_set_link_modes()
1444 netdev_info(gp->dev, "Pause is disabled\n"); in gem_set_link_modes()
1451 static int gem_mdio_link_not_up(struct gem *gp) in gem_mdio_link_not_up() argument
1453 switch (gp->lstate) { in gem_mdio_link_not_up()
1455 netif_info(gp, link, gp->dev, in gem_mdio_link_not_up()
1457 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, in gem_mdio_link_not_up()
1458 gp->last_forced_speed, DUPLEX_HALF); in gem_mdio_link_not_up()
1459 gp->timer_ticks = 5; in gem_mdio_link_not_up()
1460 gp->lstate = link_force_ok; in gem_mdio_link_not_up()
1467 if (gp->phy_mii.def->magic_aneg) in gem_mdio_link_not_up()
1469 netif_info(gp, link, gp->dev, "switching to forced 100bt\n"); in gem_mdio_link_not_up()
1471 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100, in gem_mdio_link_not_up()
1473 gp->timer_ticks = 5; in gem_mdio_link_not_up()
1474 gp->lstate = link_force_try; in gem_mdio_link_not_up()
1481 if (gp->phy_mii.speed == SPEED_100) { in gem_mdio_link_not_up()
1482 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10, in gem_mdio_link_not_up()
1484 gp->timer_ticks = 5; in gem_mdio_link_not_up()
1485 netif_info(gp, link, gp->dev, in gem_mdio_link_not_up()
1497 struct gem *gp = (struct gem *) data; in gem_link_timer() local
1498 struct net_device *dev = gp->dev; in gem_link_timer()
1502 if (gp->reset_task_pending) in gem_link_timer()
1505 if (gp->phy_type == phy_serialink || in gem_link_timer()
1506 gp->phy_type == phy_serdes) { in gem_link_timer()
1507 u32 val = readl(gp->regs + PCS_MIISTAT); in gem_link_timer()
1510 val = readl(gp->regs + PCS_MIISTAT); in gem_link_timer()
1513 if (gp->lstate == link_up) in gem_link_timer()
1516 gp->lstate = link_up; in gem_link_timer()
1518 (void)gem_set_link_modes(gp); in gem_link_timer()
1522 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) { in gem_link_timer()
1528 if (gp->lstate == link_force_try && gp->want_autoneg) { in gem_link_timer()
1529 gp->lstate = link_force_ret; in gem_link_timer()
1530 gp->last_forced_speed = gp->phy_mii.speed; in gem_link_timer()
1531 gp->timer_ticks = 5; in gem_link_timer()
1532 if (netif_msg_link(gp)) in gem_link_timer()
1535 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising); in gem_link_timer()
1536 } else if (gp->lstate != link_up) { in gem_link_timer()
1537 gp->lstate = link_up; in gem_link_timer()
1539 if (gem_set_link_modes(gp)) in gem_link_timer()
1546 if (gp->lstate == link_up) { in gem_link_timer()
1547 gp->lstate = link_down; in gem_link_timer()
1548 netif_info(gp, link, dev, "Link down\n"); in gem_link_timer()
1550 gem_schedule_reset(gp); in gem_link_timer()
1553 } else if (++gp->timer_ticks > 10) { in gem_link_timer()
1554 if (found_mii_phy(gp)) in gem_link_timer()
1555 restart_aneg = gem_mdio_link_not_up(gp); in gem_link_timer()
1561 gem_begin_auto_negotiation(gp, NULL); in gem_link_timer()
1565 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); in gem_link_timer()
1568 static void gem_clean_rings(struct gem *gp) in gem_clean_rings() argument
1570 struct gem_init_block *gb = gp->init_block; in gem_clean_rings()
1579 if (gp->rx_skbs[i] != NULL) { in gem_clean_rings()
1580 skb = gp->rx_skbs[i]; in gem_clean_rings()
1582 pci_unmap_page(gp->pdev, dma_addr, in gem_clean_rings()
1583 RX_BUF_ALLOC_SIZE(gp), in gem_clean_rings()
1586 gp->rx_skbs[i] = NULL; in gem_clean_rings()
1594 if (gp->tx_skbs[i] != NULL) { in gem_clean_rings()
1598 skb = gp->tx_skbs[i]; in gem_clean_rings()
1599 gp->tx_skbs[i] = NULL; in gem_clean_rings()
1606 pci_unmap_page(gp->pdev, dma_addr, in gem_clean_rings()
1618 static void gem_init_rings(struct gem *gp) in gem_init_rings() argument
1620 struct gem_init_block *gb = gp->init_block; in gem_init_rings()
1621 struct net_device *dev = gp->dev; in gem_init_rings()
1625 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0; in gem_init_rings()
1627 gem_clean_rings(gp); in gem_init_rings()
1629 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN, in gem_init_rings()
1636 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL); in gem_init_rings()
1643 gp->rx_skbs[i] = skb; in gem_init_rings()
1644 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET)); in gem_init_rings()
1645 dma_addr = pci_map_page(gp->pdev, in gem_init_rings()
1648 RX_BUF_ALLOC_SIZE(gp), in gem_init_rings()
1652 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); in gem_init_rings()
1667 static void gem_init_phy(struct gem *gp) in gem_init_phy() argument
1672 mifcfg = readl(gp->regs + MIF_CFG); in gem_init_phy()
1674 writel(mifcfg, gp->regs + MIF_CFG); in gem_init_phy()
1676 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) { in gem_init_phy()
1685 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0); in gem_init_phy()
1691 phy_write(gp, MII_BMCR, BMCR_RESET); in gem_init_phy()
1693 if (phy_read(gp, MII_BMCR) != 0xffff) in gem_init_phy()
1696 netdev_warn(gp->dev, "GMAC PHY not responding !\n"); in gem_init_phy()
1700 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && in gem_init_phy()
1701 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { in gem_init_phy()
1705 if (gp->phy_type == phy_mii_mdio0 || in gem_init_phy()
1706 gp->phy_type == phy_mii_mdio1) { in gem_init_phy()
1708 } else if (gp->phy_type == phy_serialink) { in gem_init_phy()
1714 writel(val, gp->regs + PCS_DMODE); in gem_init_phy()
1717 if (gp->phy_type == phy_mii_mdio0 || in gem_init_phy()
1718 gp->phy_type == phy_mii_mdio1) { in gem_init_phy()
1720 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr); in gem_init_phy()
1723 if (gp->phy_mii.def && gp->phy_mii.def->ops->init) in gem_init_phy()
1724 gp->phy_mii.def->ops->init(&gp->phy_mii); in gem_init_phy()
1726 gem_pcs_reset(gp); in gem_init_phy()
1727 gem_pcs_reinit_adv(gp); in gem_init_phy()
1731 gp->timer_ticks = 0; in gem_init_phy()
1732 gp->lstate = link_down; in gem_init_phy()
1733 netif_carrier_off(gp->dev); in gem_init_phy()
1736 if (gp->phy_type == phy_mii_mdio0 || in gem_init_phy()
1737 gp->phy_type == phy_mii_mdio1) in gem_init_phy()
1738 netdev_info(gp->dev, "Found %s PHY\n", in gem_init_phy()
1739 gp->phy_mii.def ? gp->phy_mii.def->name : "no"); in gem_init_phy()
1741 gem_begin_auto_negotiation(gp, NULL); in gem_init_phy()
1744 static void gem_init_dma(struct gem *gp) in gem_init_dma() argument
1746 u64 desc_dma = (u64) gp->gblock_dvma; in gem_init_dma()
1750 writel(val, gp->regs + TXDMA_CFG); in gem_init_dma()
1752 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI); in gem_init_dma()
1753 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW); in gem_init_dma()
1756 writel(0, gp->regs + TXDMA_KICK); in gem_init_dma()
1760 writel(val, gp->regs + RXDMA_CFG); in gem_init_dma()
1762 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); in gem_init_dma()
1763 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); in gem_init_dma()
1765 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); in gem_init_dma()
1767 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); in gem_init_dma()
1768 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); in gem_init_dma()
1769 writel(val, gp->regs + RXDMA_PTHRESH); in gem_init_dma()
1771 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) in gem_init_dma()
1774 gp->regs + RXDMA_BLANK); in gem_init_dma()
1778 gp->regs + RXDMA_BLANK); in gem_init_dma()
1781 static u32 gem_setup_multicast(struct gem *gp) in gem_setup_multicast() argument
1786 if ((gp->dev->flags & IFF_ALLMULTI) || in gem_setup_multicast()
1787 (netdev_mc_count(gp->dev) > 256)) { in gem_setup_multicast()
1789 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2)); in gem_setup_multicast()
1791 } else if (gp->dev->flags & IFF_PROMISC) { in gem_setup_multicast()
1800 netdev_for_each_mc_addr(ha, gp->dev) { in gem_setup_multicast()
1806 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2)); in gem_setup_multicast()
1813 static void gem_init_mac(struct gem *gp) in gem_init_mac() argument
1815 unsigned char *e = &gp->dev->dev_addr[0]; in gem_init_mac()
1817 writel(0x1bf0, gp->regs + MAC_SNDPAUSE); in gem_init_mac()
1819 writel(0x00, gp->regs + MAC_IPG0); in gem_init_mac()
1820 writel(0x08, gp->regs + MAC_IPG1); in gem_init_mac()
1821 writel(0x04, gp->regs + MAC_IPG2); in gem_init_mac()
1822 writel(0x40, gp->regs + MAC_STIME); in gem_init_mac()
1823 writel(0x40, gp->regs + MAC_MINFSZ); in gem_init_mac()
1826 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ); in gem_init_mac()
1828 writel(0x07, gp->regs + MAC_PASIZE); in gem_init_mac()
1829 writel(0x04, gp->regs + MAC_JAMSIZE); in gem_init_mac()
1830 writel(0x10, gp->regs + MAC_ATTLIM); in gem_init_mac()
1831 writel(0x8808, gp->regs + MAC_MCTYPE); in gem_init_mac()
1833 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED); in gem_init_mac()
1835 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); in gem_init_mac()
1836 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); in gem_init_mac()
1837 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); in gem_init_mac()
1839 writel(0, gp->regs + MAC_ADDR3); in gem_init_mac()
1840 writel(0, gp->regs + MAC_ADDR4); in gem_init_mac()
1841 writel(0, gp->regs + MAC_ADDR5); in gem_init_mac()
1843 writel(0x0001, gp->regs + MAC_ADDR6); in gem_init_mac()
1844 writel(0xc200, gp->regs + MAC_ADDR7); in gem_init_mac()
1845 writel(0x0180, gp->regs + MAC_ADDR8); in gem_init_mac()
1847 writel(0, gp->regs + MAC_AFILT0); in gem_init_mac()
1848 writel(0, gp->regs + MAC_AFILT1); in gem_init_mac()
1849 writel(0, gp->regs + MAC_AFILT2); in gem_init_mac()
1850 writel(0, gp->regs + MAC_AF21MSK); in gem_init_mac()
1851 writel(0, gp->regs + MAC_AF0MSK); in gem_init_mac()
1853 gp->mac_rx_cfg = gem_setup_multicast(gp); in gem_init_mac()
1855 gp->mac_rx_cfg |= MAC_RXCFG_SFCS; in gem_init_mac()
1857 writel(0, gp->regs + MAC_NCOLL); in gem_init_mac()
1858 writel(0, gp->regs + MAC_FASUCC); in gem_init_mac()
1859 writel(0, gp->regs + MAC_ECOLL); in gem_init_mac()
1860 writel(0, gp->regs + MAC_LCOLL); in gem_init_mac()
1861 writel(0, gp->regs + MAC_DTIMER); in gem_init_mac()
1862 writel(0, gp->regs + MAC_PATMPS); in gem_init_mac()
1863 writel(0, gp->regs + MAC_RFCTR); in gem_init_mac()
1864 writel(0, gp->regs + MAC_LERR); in gem_init_mac()
1865 writel(0, gp->regs + MAC_AERR); in gem_init_mac()
1866 writel(0, gp->regs + MAC_FCSERR); in gem_init_mac()
1867 writel(0, gp->regs + MAC_RXCVERR); in gem_init_mac()
1872 writel(0, gp->regs + MAC_TXCFG); in gem_init_mac()
1873 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG); in gem_init_mac()
1874 writel(0, gp->regs + MAC_MCCFG); in gem_init_mac()
1875 writel(0, gp->regs + MAC_XIFCFG); in gem_init_mac()
1881 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK); in gem_init_mac()
1882 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); in gem_init_mac()
1887 writel(0xffffffff, gp->regs + MAC_MCMASK); in gem_init_mac()
1891 if (gp->has_wol) in gem_init_mac()
1892 writel(0, gp->regs + WOL_WAKECSR); in gem_init_mac()
1895 static void gem_init_pause_thresholds(struct gem *gp) in gem_init_pause_thresholds() argument
1904 if (gp->rx_fifo_sz <= (2 * 1024)) { in gem_init_pause_thresholds()
1905 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz; in gem_init_pause_thresholds()
1907 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63; in gem_init_pause_thresholds()
1908 int off = (gp->rx_fifo_sz - (max_frame * 2)); in gem_init_pause_thresholds()
1911 gp->rx_pause_off = off; in gem_init_pause_thresholds()
1912 gp->rx_pause_on = on; in gem_init_pause_thresholds()
1920 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) in gem_init_pause_thresholds()
1927 writel(cfg, gp->regs + GREG_CFG); in gem_init_pause_thresholds()
1932 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) { in gem_init_pause_thresholds()
1935 writel(cfg, gp->regs + GREG_CFG); in gem_init_pause_thresholds()
1939 static int gem_check_invariants(struct gem *gp) in gem_check_invariants() argument
1941 struct pci_dev *pdev = gp->pdev; in gem_check_invariants()
1949 gp->phy_type = phy_mii_mdio0; in gem_check_invariants()
1950 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; in gem_check_invariants()
1951 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; in gem_check_invariants()
1952 gp->swrst_base = 0; in gem_check_invariants()
1954 mif_cfg = readl(gp->regs + MIF_CFG); in gem_check_invariants()
1957 writel(mif_cfg, gp->regs + MIF_CFG); in gem_check_invariants()
1958 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE); in gem_check_invariants()
1959 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG); in gem_check_invariants()
1965 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC) in gem_check_invariants()
1966 gp->mii_phy_addr = 1; in gem_check_invariants()
1968 gp->mii_phy_addr = 0; in gem_check_invariants()
1973 mif_cfg = readl(gp->regs + MIF_CFG); in gem_check_invariants()
1992 gp->phy_type = phy_mii_mdio1; in gem_check_invariants()
1994 writel(mif_cfg, gp->regs + MIF_CFG); in gem_check_invariants()
1996 gp->phy_type = phy_mii_mdio0; in gem_check_invariants()
1998 writel(mif_cfg, gp->regs + MIF_CFG); in gem_check_invariants()
2003 p = of_get_property(gp->of_node, "shared-pins", NULL); in gem_check_invariants()
2005 gp->phy_type = phy_serdes; in gem_check_invariants()
2008 gp->phy_type = phy_serialink; in gem_check_invariants()
2010 if (gp->phy_type == phy_mii_mdio1 || in gem_check_invariants()
2011 gp->phy_type == phy_mii_mdio0) { in gem_check_invariants()
2015 gp->mii_phy_addr = i; in gem_check_invariants()
2016 if (phy_read(gp, MII_BMCR) != 0xffff) in gem_check_invariants()
2024 gp->phy_type = phy_serdes; in gem_check_invariants()
2029 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; in gem_check_invariants()
2030 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; in gem_check_invariants()
2034 if (gp->tx_fifo_sz != (9 * 1024) || in gem_check_invariants()
2035 gp->rx_fifo_sz != (20 * 1024)) { in gem_check_invariants()
2037 gp->tx_fifo_sz, gp->rx_fifo_sz); in gem_check_invariants()
2040 gp->swrst_base = 0; in gem_check_invariants()
2042 if (gp->tx_fifo_sz != (2 * 1024) || in gem_check_invariants()
2043 gp->rx_fifo_sz != (2 * 1024)) { in gem_check_invariants()
2045 gp->tx_fifo_sz, gp->rx_fifo_sz); in gem_check_invariants()
2048 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT; in gem_check_invariants()
2055 static void gem_reinit_chip(struct gem *gp) in gem_reinit_chip() argument
2058 gem_reset(gp); in gem_reinit_chip()
2061 gem_disable_ints(gp); in gem_reinit_chip()
2064 gem_init_rings(gp); in gem_reinit_chip()
2067 gem_init_pause_thresholds(gp); in gem_reinit_chip()
2070 gem_init_dma(gp); in gem_reinit_chip()
2071 gem_init_mac(gp); in gem_reinit_chip()
2075 static void gem_stop_phy(struct gem *gp, int wol) in gem_stop_phy() argument
2087 mifcfg = readl(gp->regs + MIF_CFG); in gem_stop_phy()
2089 writel(mifcfg, gp->regs + MIF_CFG); in gem_stop_phy()
2091 if (wol && gp->has_wol) { in gem_stop_phy()
2092 unsigned char *e = &gp->dev->dev_addr[0]; in gem_stop_phy()
2097 gp->regs + MAC_RXCFG); in gem_stop_phy()
2098 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0); in gem_stop_phy()
2099 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1); in gem_stop_phy()
2100 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2); in gem_stop_phy()
2102 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT); in gem_stop_phy()
2104 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0) in gem_stop_phy()
2106 writel(csr, gp->regs + WOL_WAKECSR); in gem_stop_phy()
2108 writel(0, gp->regs + MAC_RXCFG); in gem_stop_phy()
2109 (void)readl(gp->regs + MAC_RXCFG); in gem_stop_phy()
2117 writel(0, gp->regs + MAC_TXCFG); in gem_stop_phy()
2118 writel(0, gp->regs + MAC_XIFCFG); in gem_stop_phy()
2119 writel(0, gp->regs + TXDMA_CFG); in gem_stop_phy()
2120 writel(0, gp->regs + RXDMA_CFG); in gem_stop_phy()
2123 gem_reset(gp); in gem_stop_phy()
2124 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST); in gem_stop_phy()
2125 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); in gem_stop_phy()
2127 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend) in gem_stop_phy()
2128 gp->phy_mii.def->ops->suspend(&gp->phy_mii); in gem_stop_phy()
2133 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG); in gem_stop_phy()
2134 writel(0, gp->regs + MIF_BBCLK); in gem_stop_phy()
2135 writel(0, gp->regs + MIF_BBDATA); in gem_stop_phy()
2136 writel(0, gp->regs + MIF_BBOENAB); in gem_stop_phy()
2137 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG); in gem_stop_phy()
2138 (void) readl(gp->regs + MAC_XIFCFG); in gem_stop_phy()
2144 struct gem *gp = netdev_priv(dev); in gem_do_start() local
2148 gem_get_cell(gp); in gem_do_start()
2151 rc = pci_enable_device(gp->pdev); in gem_do_start()
2158 gem_put_cell(gp); in gem_do_start()
2161 pci_set_master(gp->pdev); in gem_do_start()
2164 gem_reinit_chip(gp); in gem_do_start()
2167 rc = request_irq(gp->pdev->irq, gem_interrupt, in gem_do_start()
2172 gem_reset(gp); in gem_do_start()
2173 gem_clean_rings(gp); in gem_do_start()
2174 gem_put_cell(gp); in gem_do_start()
2184 gem_netif_start(gp); in gem_do_start()
2190 gem_init_phy(gp); in gem_do_start()
2197 struct gem *gp = netdev_priv(dev); in gem_do_stop() local
2200 gem_netif_stop(gp); in gem_do_stop()
2207 gem_disable_ints(gp); in gem_do_stop()
2210 del_timer_sync(&gp->link_timer); in gem_do_stop()
2221 gp->reset_task_pending = 0; in gem_do_stop()
2224 gem_stop_dma(gp); in gem_do_stop()
2227 gem_reset(gp); in gem_do_stop()
2231 gem_clean_rings(gp); in gem_do_stop()
2234 free_irq(gp->pdev->irq, (void *) dev); in gem_do_stop()
2237 gem_stop_phy(gp, wol); in gem_do_stop()
2240 pci_disable_device(gp->pdev); in gem_do_stop()
2244 gem_put_cell(gp); in gem_do_stop()
2249 struct gem *gp = container_of(work, struct gem, reset_task); in gem_reset_task() local
2259 if (!netif_device_present(gp->dev) || in gem_reset_task()
2260 !netif_running(gp->dev) || in gem_reset_task()
2261 !gp->reset_task_pending) { in gem_reset_task()
2267 del_timer_sync(&gp->link_timer); in gem_reset_task()
2270 gem_netif_stop(gp); in gem_reset_task()
2273 gem_reinit_chip(gp); in gem_reset_task()
2274 if (gp->lstate == link_up) in gem_reset_task()
2275 gem_set_link_modes(gp); in gem_reset_task()
2278 gem_netif_start(gp); in gem_reset_task()
2281 gp->reset_task_pending = 0; in gem_reset_task()
2286 if (gp->lstate != link_up) in gem_reset_task()
2287 gem_begin_auto_negotiation(gp, NULL); in gem_reset_task()
2289 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); in gem_reset_task()
2316 struct gem *gp = netdev_priv(dev); in gem_suspend() local
2332 (gp->wake_on_lan && netif_running(dev)) ? in gem_suspend()
2341 gp->asleep_wol = !!gp->wake_on_lan; in gem_suspend()
2342 gem_do_stop(dev, gp->asleep_wol); in gem_suspend()
2353 struct gem *gp = netdev_priv(dev); in gem_resume() local
2375 if (gp->asleep_wol) in gem_resume()
2376 gem_put_cell(gp); in gem_resume()
2387 struct gem *gp = netdev_priv(dev); in gem_get_stats() local
2400 if (WARN_ON(!gp->cell_enabled)) in gem_get_stats()
2403 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR); in gem_get_stats()
2404 writel(0, gp->regs + MAC_FCSERR); in gem_get_stats()
2406 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR); in gem_get_stats()
2407 writel(0, gp->regs + MAC_AERR); in gem_get_stats()
2409 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR); in gem_get_stats()
2410 writel(0, gp->regs + MAC_LERR); in gem_get_stats()
2412 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL); in gem_get_stats()
2414 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL)); in gem_get_stats()
2415 writel(0, gp->regs + MAC_ECOLL); in gem_get_stats()
2416 writel(0, gp->regs + MAC_LCOLL); in gem_get_stats()
2424 struct gem *gp = netdev_priv(dev); in gem_set_mac_address() local
2437 if (WARN_ON(!gp->cell_enabled)) in gem_set_mac_address()
2440 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); in gem_set_mac_address()
2441 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); in gem_set_mac_address()
2442 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); in gem_set_mac_address()
2449 struct gem *gp = netdev_priv(dev); in gem_set_multicast() local
2457 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled)) in gem_set_multicast()
2460 rxcfg = readl(gp->regs + MAC_RXCFG); in gem_set_multicast()
2461 rxcfg_new = gem_setup_multicast(gp); in gem_set_multicast()
2465 gp->mac_rx_cfg = rxcfg_new; in gem_set_multicast()
2467 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_set_multicast()
2468 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) { in gem_set_multicast()
2477 writel(rxcfg, gp->regs + MAC_RXCFG); in gem_set_multicast()
2490 struct gem *gp = netdev_priv(dev); in gem_change_mtu() local
2502 if (WARN_ON(!gp->cell_enabled)) in gem_change_mtu()
2505 gem_netif_stop(gp); in gem_change_mtu()
2506 gem_reinit_chip(gp); in gem_change_mtu()
2507 if (gp->lstate == link_up) in gem_change_mtu()
2508 gem_set_link_modes(gp); in gem_change_mtu()
2509 gem_netif_start(gp); in gem_change_mtu()
2516 struct gem *gp = netdev_priv(dev); in gem_get_drvinfo() local
2520 strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info)); in gem_get_drvinfo()
2525 struct gem *gp = netdev_priv(dev); in gem_get_settings() local
2527 if (gp->phy_type == phy_mii_mdio0 || in gem_get_settings()
2528 gp->phy_type == phy_mii_mdio1) { in gem_get_settings()
2529 if (gp->phy_mii.def) in gem_get_settings()
2530 cmd->supported = gp->phy_mii.def->features; in gem_get_settings()
2541 cmd->autoneg = gp->want_autoneg; in gem_get_settings()
2542 ethtool_cmd_speed_set(cmd, gp->phy_mii.speed); in gem_get_settings()
2543 cmd->duplex = gp->phy_mii.duplex; in gem_get_settings()
2544 cmd->advertising = gp->phy_mii.advertising; in gem_get_settings()
2563 if (gp->phy_type == phy_serdes) { in gem_get_settings()
2571 if (gp->lstate == link_up) in gem_get_settings()
2584 struct gem *gp = netdev_priv(dev); in gem_set_settings() local
2605 if (netif_device_present(gp->dev)) { in gem_set_settings()
2606 del_timer_sync(&gp->link_timer); in gem_set_settings()
2607 gem_begin_auto_negotiation(gp, cmd); in gem_set_settings()
2615 struct gem *gp = netdev_priv(dev); in gem_nway_reset() local
2617 if (!gp->want_autoneg) in gem_nway_reset()
2621 if (netif_device_present(gp->dev)) { in gem_nway_reset()
2622 del_timer_sync(&gp->link_timer); in gem_nway_reset()
2623 gem_begin_auto_negotiation(gp, NULL); in gem_nway_reset()
2631 struct gem *gp = netdev_priv(dev); in gem_get_msglevel() local
2632 return gp->msg_enable; in gem_get_msglevel()
2637 struct gem *gp = netdev_priv(dev); in gem_set_msglevel() local
2638 gp->msg_enable = value; in gem_set_msglevel()
2649 struct gem *gp = netdev_priv(dev); in gem_get_wol() local
2652 if (gp->has_wol) { in gem_get_wol()
2654 wol->wolopts = gp->wake_on_lan; in gem_get_wol()
2663 struct gem *gp = netdev_priv(dev); in gem_set_wol() local
2665 if (!gp->has_wol) in gem_set_wol()
2667 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK; in gem_set_wol()
2685 struct gem *gp = netdev_priv(dev); in gem_ioctl() local
2696 data->phy_id = gp->mii_phy_addr; in gem_ioctl()
2700 data->val_out = __phy_read(gp, data->phy_id & 0x1f, in gem_ioctl()
2706 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, in gem_ioctl()
2766 static int gem_get_device_address(struct gem *gp) in gem_get_device_address() argument
2769 struct net_device *dev = gp->dev; in gem_get_device_address()
2772 addr = of_get_property(gp->of_node, "local-mac-address", NULL); in gem_get_device_address()
2784 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr); in gem_get_device_address()
2794 struct gem *gp = netdev_priv(dev); in gem_remove_one() local
2799 cancel_work_sync(&gp->reset_task); in gem_remove_one()
2804 gp->init_block, in gem_remove_one()
2805 gp->gblock_dvma); in gem_remove_one()
2806 iounmap(gp->regs); in gem_remove_one()
2834 struct gem *gp; in gem_init_one() local
2883 dev = alloc_etherdev(sizeof(*gp)); in gem_init_one()
2890 gp = netdev_priv(dev); in gem_init_one()
2898 gp->pdev = pdev; in gem_init_one()
2899 gp->dev = dev; in gem_init_one()
2901 gp->msg_enable = DEFAULT_MSG; in gem_init_one()
2903 init_timer(&gp->link_timer); in gem_init_one()
2904 gp->link_timer.function = gem_link_timer; in gem_init_one()
2905 gp->link_timer.data = (unsigned long) gp; in gem_init_one()
2907 INIT_WORK(&gp->reset_task, gem_reset_task); in gem_init_one()
2909 gp->lstate = link_down; in gem_init_one()
2910 gp->timer_ticks = 0; in gem_init_one()
2913 gp->regs = ioremap(gemreg_base, gemreg_len); in gem_init_one()
2914 if (!gp->regs) { in gem_init_one()
2924 gp->of_node = pci_device_to_OF_node(pdev); in gem_init_one()
2929 gp->has_wol = 1; in gem_init_one()
2932 gem_get_cell(gp); in gem_init_one()
2935 gem_reset(gp); in gem_init_one()
2938 gp->phy_mii.dev = dev; in gem_init_one()
2939 gp->phy_mii.mdio_read = _phy_read; in gem_init_one()
2940 gp->phy_mii.mdio_write = _phy_write; in gem_init_one()
2942 gp->phy_mii.platform_data = gp->of_node; in gem_init_one()
2945 gp->want_autoneg = 1; in gem_init_one()
2948 if (gem_check_invariants(gp)) { in gem_init_one()
2956 gp->init_block = (struct gem_init_block *) in gem_init_one()
2958 &gp->gblock_dvma); in gem_init_one()
2959 if (!gp->init_block) { in gem_init_one()
2965 err = gem_get_device_address(gp); in gem_init_one()
2970 netif_napi_add(dev, &gp->napi, gem_poll, 64); in gem_init_one()
2995 gem_put_cell(gp); in gem_init_one()
3005 gem_put_cell(gp); in gem_init_one()
3006 iounmap(gp->regs); in gem_init_one()