234 static void write_scc(struct scc_priv *priv, int reg, int val);
295 		write_scc(&info->priv[0], R9, FHWRES);  in dmascc_exit()
494 	write_scc(priv, R9, FHWRES | MIE | NV);  in setup_adapter()
497 	write_scc(priv, R15, SHDLCE);  in setup_adapter()
512 	write_scc(priv, R15, 0);  in setup_adapter()
525 		write_scc(priv, R15, CTSIE);  in setup_adapter()
526 		write_scc(priv, R0, RES_EXT_INT);  in setup_adapter()
527 		write_scc(priv, R1, EXT_INT_ENAB);  in setup_adapter()
543 		write_scc(priv, R1, 0);  in setup_adapter()
544 		write_scc(priv, R15, 0);  in setup_adapter()
545 		write_scc(priv, R0, RES_EXT_INT);  in setup_adapter()
608 	write_scc(&info->priv[0], R9, FHWRES);  in setup_adapter()
621 static void write_scc(struct scc_priv *priv, int reg, int val)  in write_scc()  function
755 	write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);  in scc_open()
757 	write_scc(priv, R4, SDLC | X1CLK);  in scc_open()
759 	write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);  in scc_open()
761 	write_scc(priv, R3, Rx8);  in scc_open()
763 	write_scc(priv, R5, Tx8);  in scc_open()
765 	write_scc(priv, R6, 0);  in scc_open()
767 	write_scc(priv, R7, FLAG);  in scc_open()
771 		write_scc(priv, R15, SHDLCE);  in scc_open()
773 		write_scc(priv, R7, AUTOEOM);  in scc_open()
774 		write_scc(priv, R15, 0);  in scc_open()
778 		write_scc(priv, R15, SHDLCE);  in scc_open()
800 				write_scc(priv, R7, AUTOEOM | TXFIFOE);  in scc_open()
802 				write_scc(priv, R7, AUTOEOM);  in scc_open()
804 			write_scc(priv, R7, AUTOEOM | RXFIFOH);  in scc_open()
806 		write_scc(priv, R15, 0);  in scc_open()
810 	write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));  in scc_open()
815 		write_scc(priv, R12, priv->param.brg_tc & 0xFF);  in scc_open()
816 		write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);  in scc_open()
819 		write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);  in scc_open()
821 		write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);  in scc_open()
824 		write_scc(priv, R14, DTRREQ | BRSRC);  in scc_open()
834 	write_scc(priv, R11, priv->param.clocks);  in scc_open()
853 	write_scc(priv, R15, DCDIE);  in scc_open()
877 	write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);  in scc_close()
949 		write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);  in scc_send_packet()
950 		write_scc(priv, R15, 0);  in scc_send_packet()
986 		write_scc(priv, R15, TxUIE);  in tx_on()
993 			write_scc(priv, R1,  in tx_on()
1004 		write_scc(priv, R15, TxUIE);  in tx_on()
1005 		write_scc(priv, R1,  in tx_on()
1011 		write_scc(priv, R0, RES_EOM_L);  in tx_on()
1039 		write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |  in rx_on()
1045 		write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |  in rx_on()
1048 	write_scc(priv, R0, ERR_RES);  in rx_on()
1049 	write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);  in rx_on()
1056 	write_scc(priv, R3, Rx8);  in rx_off()
1061 		write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);  in rx_off()
1077 			write_scc(priv, R15, r15 | CTSIE);  in start_timer()
1109 		write_scc(&info->priv[0], R0, RES_H_IUS);  in z8530_isr()
1164 		write_scc(priv, R0, ERR_RES);  in rx_isr()
1196 			write_scc(priv, R0, ERR_RES);  in special_condition()
1295 		write_scc(priv, R0, RES_Tx_P);  in tx_isr()
1306 		write_scc(priv, R0, RES_EOM_L);  in tx_isr()
1319 	write_scc(priv, R0, RES_EXT_INT);  in es_isr()
1341 			write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);  in es_isr()
1347 			write_scc(priv, R0, RES_EXT_INT);  in es_isr()
1348 			write_scc(priv, R0, RES_EXT_INT);  in es_isr()
1360 		write_scc(priv, R15, 0);  in es_isr()
1378 				write_scc(priv, R15, 0);  in es_isr()
1386 				write_scc(priv, R15, 0);  in es_isr()
1408 		write_scc(priv, R5, TxCRC_ENAB | Tx8);  in tm_isr()
1411 			write_scc(priv, R15, 0);  in tm_isr()
1415 		write_scc(priv, R15, DCDIE);  in tm_isr()
1430 			write_scc(priv, R5,  in tm_isr()
1432 			write_scc(priv, R15, 0);  in tm_isr()
1437 				write_scc(priv, R15, DCDIE);  in tm_isr()
1442 		write_scc(priv, R15, DCDIE);  in tm_isr()