Lines Matching refs:iobase
212 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
362 static inline void register_bank(int iobase, int bank) in register_bank() argument
364 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), in register_bank()
365 iobase + IRCC_MASTER); in register_bank()
752 int iobase = self->io.fir_base; in smsc_ircc_init_chip() local
754 register_bank(iobase, 0); in smsc_ircc_init_chip()
755 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); in smsc_ircc_init_chip()
756 outb(0x00, iobase + IRCC_MASTER); in smsc_ircc_init_chip()
758 register_bank(iobase, 1); in smsc_ircc_init_chip()
759 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), in smsc_ircc_init_chip()
760 iobase + IRCC_SCE_CFGA); in smsc_ircc_init_chip()
763 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), in smsc_ircc_init_chip()
764 iobase + IRCC_SCE_CFGB); in smsc_ircc_init_chip()
766 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), in smsc_ircc_init_chip()
767 iobase + IRCC_SCE_CFGB); in smsc_ircc_init_chip()
769 (void) inb(iobase + IRCC_FIFO_THRESHOLD); in smsc_ircc_init_chip()
770 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD); in smsc_ircc_init_chip()
772 register_bank(iobase, 4); in smsc_ircc_init_chip()
773 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); in smsc_ircc_init_chip()
775 register_bank(iobase, 0); in smsc_ircc_init_chip()
776 outb(0, iobase + IRCC_LCR_A); in smsc_ircc_init_chip()
781 outb(0x00, iobase + IRCC_MASTER); in smsc_ircc_init_chip()
1131 int iobase; in smsc_ircc_set_sir_speed() local
1139 iobase = self->io.sir_base; in smsc_ircc_set_sir_speed()
1145 outb(0, iobase + UART_IER); in smsc_ircc_set_sir_speed()
1162 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */ in smsc_ircc_set_sir_speed()
1163 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ in smsc_ircc_set_sir_speed()
1164 outb(divisor >> 8, iobase + UART_DLM); in smsc_ircc_set_sir_speed()
1165 outb(lcr, iobase + UART_LCR); /* Set 8N1 */ in smsc_ircc_set_sir_speed()
1166 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ in smsc_ircc_set_sir_speed()
1169 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER); in smsc_ircc_set_sir_speed()
1252 int iobase = self->io.fir_base; in smsc_ircc_dma_xmit() local
1258 register_bank(iobase, 0); in smsc_ircc_dma_xmit()
1259 outb(0x00, iobase + IRCC_LCR_B); in smsc_ircc_dma_xmit()
1261 register_bank(iobase, 1); in smsc_ircc_dma_xmit()
1262 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_xmit()
1263 iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_xmit()
1268 register_bank(iobase, 4); in smsc_ircc_dma_xmit()
1269 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO); in smsc_ircc_dma_xmit()
1270 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; in smsc_ircc_dma_xmit()
1271 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI); in smsc_ircc_dma_xmit()
1274 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI); in smsc_ircc_dma_xmit()
1275 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO); in smsc_ircc_dma_xmit()
1280 register_bank(iobase, 1); in smsc_ircc_dma_xmit()
1281 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | in smsc_ircc_dma_xmit()
1282 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_xmit()
1290 register_bank(iobase, 0); in smsc_ircc_dma_xmit()
1291 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); in smsc_ircc_dma_xmit()
1292 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); in smsc_ircc_dma_xmit()
1295 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); in smsc_ircc_dma_xmit()
1307 int iobase = self->io.fir_base; in smsc_ircc_dma_xmit_complete() local
1312 register_bank(iobase, 0); in smsc_ircc_dma_xmit_complete()
1313 outb(0x00, iobase + IRCC_LCR_B); in smsc_ircc_dma_xmit_complete()
1315 register_bank(iobase, 1); in smsc_ircc_dma_xmit_complete()
1316 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_xmit_complete()
1317 iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_xmit_complete()
1320 register_bank(iobase, 0); in smsc_ircc_dma_xmit_complete()
1321 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { in smsc_ircc_dma_xmit_complete()
1326 register_bank(iobase, 0); in smsc_ircc_dma_xmit_complete()
1327 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER); in smsc_ircc_dma_xmit_complete()
1328 outb(0x00, iobase + IRCC_MASTER); in smsc_ircc_dma_xmit_complete()
1352 int iobase = self->io.fir_base; in smsc_ircc_dma_receive() local
1355 register_bank(iobase, 1); in smsc_ircc_dma_receive()
1356 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_receive()
1357 iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_receive()
1361 register_bank(iobase, 0); in smsc_ircc_dma_receive()
1362 outb(0x00, iobase + IRCC_LCR_B); in smsc_ircc_dma_receive()
1365 register_bank(iobase, 1); in smsc_ircc_dma_receive()
1366 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, in smsc_ircc_dma_receive()
1367 iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_receive()
1373 register_bank(iobase, 4); in smsc_ircc_dma_receive()
1374 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); in smsc_ircc_dma_receive()
1375 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); in smsc_ircc_dma_receive()
1382 register_bank(iobase, 1); in smsc_ircc_dma_receive()
1383 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | in smsc_ircc_dma_receive()
1384 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); in smsc_ircc_dma_receive()
1387 register_bank(iobase, 0); in smsc_ircc_dma_receive()
1388 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); in smsc_ircc_dma_receive()
1389 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); in smsc_ircc_dma_receive()
1392 register_bank(iobase, 0); in smsc_ircc_dma_receive()
1394 iobase + IRCC_LCR_B); in smsc_ircc_dma_receive()
1409 int iobase = self->io.fir_base; in smsc_ircc_dma_receive_complete() local
1411 register_bank(iobase, 0); in smsc_ircc_dma_receive_complete()
1416 register_bank(iobase, 0); in smsc_ircc_dma_receive_complete()
1417 outb(0x00, iobase + IRCC_LCR_B); in smsc_ircc_dma_receive_complete()
1419 register_bank(iobase, 0); in smsc_ircc_dma_receive_complete()
1420 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); in smsc_ircc_dma_receive_complete()
1421 lsr= inb(iobase + IRCC_LSR); in smsc_ircc_dma_receive_complete()
1422 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; in smsc_ircc_dma_receive_complete()
1480 int iobase; in smsc_ircc_sir_receive() local
1484 iobase = self->io.sir_base; in smsc_ircc_sir_receive()
1492 inb(iobase + UART_RX)); in smsc_ircc_sir_receive()
1499 } while (inb(iobase + UART_LSR) & UART_LSR_DR); in smsc_ircc_sir_receive()
1513 int iobase, iir, lcra, lsr; in smsc_ircc_interrupt() local
1525 iobase = self->io.fir_base; in smsc_ircc_interrupt()
1527 register_bank(iobase, 0); in smsc_ircc_interrupt()
1528 iir = inb(iobase + IRCC_IIR); in smsc_ircc_interrupt()
1534 outb(0, iobase + IRCC_IER); in smsc_ircc_interrupt()
1535 lcra = inb(iobase + IRCC_LCR_A); in smsc_ircc_interrupt()
1536 lsr = inb(iobase + IRCC_LSR); in smsc_ircc_interrupt()
1555 register_bank(iobase, 0); in smsc_ircc_interrupt()
1556 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); in smsc_ircc_interrupt()
1573 int iobase; in smsc_ircc_interrupt_sir() local
1579 iobase = self->io.sir_base; in smsc_ircc_interrupt_sir()
1581 iir = inb(iobase + UART_IIR) & UART_IIR_ID; in smsc_ircc_interrupt_sir()
1586 lsr = inb(iobase + UART_LSR); in smsc_ircc_interrupt_sir()
1589 __func__, iir, lsr, iobase); in smsc_ircc_interrupt_sir()
1614 iir = inb(iobase + UART_IIR) & UART_IIR_ID; in smsc_ircc_interrupt_sir()
1673 int iobase = self->io.fir_base; in smsc_ircc_stop_interrupts() local
1678 register_bank(iobase, 0); in smsc_ircc_stop_interrupts()
1679 outb(0, iobase + IRCC_IER); in smsc_ircc_stop_interrupts()
1680 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); in smsc_ircc_stop_interrupts()
1681 outb(0x00, iobase + IRCC_MASTER); in smsc_ircc_stop_interrupts()
1935 int iobase; in smsc_ircc_sir_stop() local
1938 iobase = self->io.sir_base; in smsc_ircc_sir_stop()
1941 outb(0, iobase + UART_MCR); in smsc_ircc_sir_stop()
1944 outb(0, iobase + UART_IER); in smsc_ircc_sir_stop()
1958 int iobase; in smsc_ircc_sir_write_wakeup() local
1965 iobase = self->io.sir_base; in smsc_ircc_sir_write_wakeup()
1970 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size, in smsc_ircc_sir_write_wakeup()
2004 outb(fcr, iobase + UART_FCR); in smsc_ircc_sir_write_wakeup()
2007 outb(UART_IER_RDI, iobase + UART_IER); in smsc_ircc_sir_write_wakeup()
2018 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) in smsc_ircc_sir_write() argument
2023 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { in smsc_ircc_sir_write()
2031 outb(buf[actual], iobase + UART_TX); in smsc_ircc_sir_write()
2116 int iobase = self->io.sir_base; in smsc_ircc_sir_wait_hw_transmitter_finish() local
2120 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) in smsc_ircc_sir_wait_hw_transmitter_finish()
2528 unsigned short iobase = conf->cfg_base; in preconfigure_smsc_chip() local
2531 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state in preconfigure_smsc_chip()
2532 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID in preconfigure_smsc_chip()
2533 tmpbyte = inb(iobase +1); // Read device ID in preconfigure_smsc_chip()
2539 outb(0x24, iobase); // select CR24 - UART1 base addr in preconfigure_smsc_chip()
2540 outb(0x00, iobase + 1); // disable UART1 in preconfigure_smsc_chip()
2541 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr in preconfigure_smsc_chip()
2542 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8 in preconfigure_smsc_chip()
2543 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2551 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select in preconfigure_smsc_chip()
2552 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2555 outb(tmpbyte, iobase + 1); in preconfigure_smsc_chip()
2556 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; in preconfigure_smsc_chip()
2563 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr in preconfigure_smsc_chip()
2564 outb((conf->fir_io >> 3), iobase + 1); in preconfigure_smsc_chip()
2565 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2572 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select in preconfigure_smsc_chip()
2573 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA in preconfigure_smsc_chip()
2574 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; in preconfigure_smsc_chip()
2580 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode in preconfigure_smsc_chip()
2581 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2584 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed in preconfigure_smsc_chip()
2586 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel in preconfigure_smsc_chip()
2587 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2588 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down in preconfigure_smsc_chip()
2591 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux in preconfigure_smsc_chip()
2592 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2593 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port in preconfigure_smsc_chip()
2595 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power in preconfigure_smsc_chip()
2596 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2597 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down in preconfigure_smsc_chip()
2599 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle in preconfigure_smsc_chip()
2600 tmpbyte = inb(iobase + 1); in preconfigure_smsc_chip()
2601 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done in preconfigure_smsc_chip()
2603 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration in preconfigure_smsc_chip()